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Searched refs:nxv8i64 (Results 1 – 19 of 19) sorted by relevance

/external/llvm-project/llvm/test/CodeGen/AArch64/
Dsve-split-int-reduce.ll57 %res = call i64 @llvm.vector.reduce.or.nxv8i64(<vscale x 8 x i64> %a)
208 %res = call i64 @llvm.vector.reduce.smax.nxv8i64(<vscale x 8 x i64> %a)
216 declare i64 @llvm.vector.reduce.or.nxv8i64(<vscale x 8 x i64>)
233 declare i64 @llvm.vector.reduce.smax.nxv8i64(<vscale x 8 x i64>)
Dsve-split-store.ll127 …call void @llvm.masked.store.nxv8i64(<vscale x 8 x i64> %data, <vscale x 8 x i64> *%a, i32 1, <vsc…
138 declare void @llvm.masked.store.nxv8i64(<vscale x 8 x i64>, <vscale x 8 x i64>*, i32, <vscale x 8 x…
Dsve-intrinsics-ldN-reg+reg-addr-mode.ll217 define <vscale x 8 x i64> @ld4.nxv8i64(<vscale x 2 x i1> %Pg, i64 *%addr, i64 %a) {
218 ; CHECK-LABEL: ld4.nxv8i64:
222 %res = call <vscale x 8 x i64> @llvm.aarch64.sve.ld4.nxv8i64.nxv2i1.p0i64(<vscale x 2 x i1> %Pg, i6…
256 declare <vscale x 8 x i64> @llvm.aarch64.sve.ld4.nxv8i64.nxv2i1.p0i64(<vscale x 2 x i1>, i64*)
Dsve-split-load.ll139 …%load = call <vscale x 8 x i64> @llvm.masked.load.nxv8i64(<vscale x 8 x i64> *%a, i32 1, <vscale x…
150 declare <vscale x 8 x i64> @llvm.masked.load.nxv8i64(<vscale x 8 x i64>*, i32, <vscale x 8 x i1>, <…
Dsve-intrinsics-create-tuple.ll697 …%tuple = tail call <vscale x 8 x i64> @llvm.aarch64.sve.tuple.create4.nxv8i64.nxv2i64(<vscale x 2 …
702 …%extract = tail call <vscale x 2 x i64> @llvm.aarch64.sve.tuple.get.nxv2i64.nxv8i64(<vscale x 8 x …
711 …%tuple = tail call <vscale x 8 x i64> @llvm.aarch64.sve.tuple.create4.nxv8i64.nxv2i64(<vscale x 2 …
716 …%extract = tail call <vscale x 2 x i64> @llvm.aarch64.sve.tuple.get.nxv2i64.nxv8i64(<vscale x 8 x …
777 declare <vscale x 8 x i64> @llvm.aarch64.sve.tuple.create4.nxv8i64.nxv2i64(<vscale x 2 x i64>, <vs…
796 declare <vscale x 2 x i64> @llvm.aarch64.sve.tuple.get.nxv2i64.nxv8i64(<vscale x 8 x i64>, i32 imma…
Dsve-intrinsics-ldN-reg+imm-addr-mode.ll451 define <vscale x 8 x i64> @ld4.nxv8i64(<vscale x 2 x i1> %Pg, <vscale x 2 x i64> *%addr) {
452 ; CHECK-LABEL: ld4.nxv8i64:
457 %res = call <vscale x 8 x i64> @llvm.aarch64.sve.ld4.nxv8i64.nxv2i1.p0i64(<vscale x 2 x i1> %Pg, i6…
492 declare <vscale x 8 x i64> @llvm.aarch64.sve.ld4.nxv8i64.nxv2i1.p0i64(<vscale x 2 x i1>, i64*)
Dsve-calling-convention-tuple-types.ll387 …%tuple = tail call <vscale x 8 x i64> @llvm.aarch64.sve.tuple.create4.nxv8i64.nxv2i64(<vscale x 2 …
398 …%tuple = tail call <vscale x 8 x i64> @llvm.aarch64.sve.tuple.create4.nxv8i64.nxv2i64(<vscale x 2 …
501 declare <vscale x 8 x i64> @llvm.aarch64.sve.tuple.create4.nxv8i64.nxv2i64(<vscale x 2 x i64>, <vsc…
Dsve-intrinsics-int-arith.ll355 …%tuple = tail call <vscale x 8 x i64> @llvm.aarch64.sve.tuple.create4.nxv8i64.nxv2i64(<vscale x 2 …
405 declare <vscale x 8 x i64> @llvm.aarch64.sve.tuple.create4.nxv8i64.nxv2i64(<vscale x 2 x i64>, <vsc…
Dsve-intrinsics-loads.ll513 …%res = call <vscale x 8 x i64> @llvm.aarch64.sve.ld4.nxv8i64.nxv2i1.p0i64(<vscale x 2 x i1> %pred,…
565 declare <vscale x 8 x i64> @llvm.aarch64.sve.ld4.nxv8i64.nxv2i1.p0i64(<vscale x 2 x i1>, i64*)
Dsve-intrinsics-stores.ll493 …%tuple = tail call <vscale x 8 x i64> @llvm.aarch64.sve.tuple.create4.nxv8i64.nxv2i64(<vscale x 2 …
578 declare <vscale x 8 x i64> @llvm.aarch64.sve.tuple.create4.nxv8i64.nxv2i64(<vscale x 2 x i64>, <vsc…
/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/Support/
DMachineValueType.h181 nxv8i64 = 115, // n x 8 x i64 enumerator
504 case nxv8i64: in getVectorElementType()
610 case nxv8i64: in getVectorNumElements()
800 case nxv8i64: in getSizeInBits()
1058 if (NumElements == 8) return MVT::nxv8i64; in getScalableVectorVT()
/external/llvm-project/llvm/include/llvm/Support/
DMachineValueType.h202 nxv8i64 = 136, // n x 8 x i64 enumerator
576 case nxv8i64: in getVectorElementType()
722 case nxv8i64: in getVectorNumElements()
938 case nxv8i64: in getSizeInBits()
1267 if (NumElements == 8) return MVT::nxv8i64; in getScalableVectorVT()
/external/llvm-project/llvm/lib/Target/RISCV/Utils/
DRISCVBaseInfo.h303 constexpr MVT vint64m8_t = MVT::nxv8i64;
/external/llvm-project/llvm/lib/Target/RISCV/
DRISCVRegisterInfo.td282 // i64* N/A N/A N/A nxv1i64 nxv2i64 nxv4i64 nxv8i64
315 defvar vint64m8_t = nxv8i64;
/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/
DValueTypes.cpp287 case MVT::nxv8i64: in getTypeForEVT()
/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/
DValueTypes.td147 def nxv8i64 : ValueType<512, 115>; // n x 8 x i64 vector value
/external/llvm-project/llvm/include/llvm/CodeGen/
DValueTypes.td169 def nxv8i64 : ValueType<512, 136>; // n x 8 x i64 vector value
/external/llvm-project/llvm/lib/CodeGen/
DValueTypes.cpp440 case MVT::nxv8i64: in getTypeForEVT()
/external/llvm-project/llvm/utils/TableGen/
DCodeGenTarget.cpp202 case MVT::nxv8i64: return "MVT::nxv8i64"; in getEnumName()