/external/arm-trusted-firmware/include/arch/aarch32/ |
D | arch_helpers.h | 22 #define _DEFINE_COPROCR_WRITE_FUNC(_name, coproc, opc1, CRn, CRm, opc2) \ argument 25 __asm__ volatile ("mcr "#coproc","#opc1",%0,"#CRn","#CRm","#opc2 : : "r" (v));\ 28 #define _DEFINE_COPROCR_READ_FUNC(_name, coproc, opc1, CRn, CRm, opc2) \ argument 32 __asm__ volatile ("mrc "#coproc","#opc1",%0,"#CRn","#CRm","#opc2 : "=r" (v));\ 41 #define _DEFINE_COPROCR_WRITE_FUNC_64(_name, coproc, opc1, CRm) \ argument 44 __asm__ volatile ("mcrr "#coproc","#opc1", %Q0, %R0,"#CRm : : "r" (v));\ 47 #define _DEFINE_COPROCR_READ_FUNC_64(_name, coproc, opc1, CRm) \ argument 50 __asm__ volatile ("mrrc "#coproc","#opc1", %Q0, %R0,"#CRm : "=r" (v));\ 109 #define _DEFINE_TLBIOP_FUNC(_op, coproc, opc1, CRn, CRm, opc2) \ argument 113 __asm__ volatile ("mcr "#coproc","#opc1",%0,"#CRn","#CRm","#opc2 : : "r" (v));\ [all …]
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D | asm_macros.S | 32 .macro ldcopr reg, coproc, opc1, CRn, CRm, opc2 33 mrc \coproc, \opc1, \reg, \CRn, \CRm, \opc2 36 .macro ldcopr16 reg1, reg2, coproc, opc1, CRm 37 mrrc \coproc, \opc1, \reg1, \reg2, \CRm 40 .macro stcopr reg, coproc, opc1, CRn, CRm, opc2 41 mcr \coproc, \opc1, \reg, \CRn, \CRm, \opc2 44 .macro stcopr16 reg1, reg2, coproc, opc1, CRm 45 mcrr \coproc, \opc1, \reg1, \reg2, \CRm
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/external/llvm-project/flang/test/Semantics/ |
D | symbol15.f90 | 49 real, pointer :: opc1 component 99 real, pointer :: opc1 component
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/external/arm-trusted-firmware/lib/aarch32/ |
D | cache_helpers.S | 22 .macro do_dcache_maintenance_by_mva op, coproc, opc1, CRn, CRm, opc2 31 stcopr r0, \coproc, \opc1, \CRn, \CRm, \opc2
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/external/llvm/lib/Target/ARM/ |
D | ARMInstrThumb2.td | 4151 : T2Cop<Op, oops, iops, opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2", 4159 bits<3> opc1; 4166 let Inst{23-21} = opc1; 4174 : T2Cop<Op, oops, iops, opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm", pattern> { 4182 bits<4> opc1; 4188 let Inst{7-4} = opc1; 4195 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn, 4197 [(int_arm_mcr imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn, 4200 def : t2InstAlias<"mcr${p} $cop, $opc1, $Rt, $CRn, $CRm", 4201 (t2MCR p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn, [all …]
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D | ARMInstrInfo.td | 4812 def CDP : ABI<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1, 4814 NoItinerary, "cdp", "\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2", 4815 [(int_arm_cdp imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn, 4818 bits<4> opc1; 4831 let Inst{23-20} = opc1; 4834 def CDP2 : ABXI<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1, 4836 NoItinerary, "cdp2\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2", 4837 [(int_arm_cdp2 imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn, 4841 bits<4> opc1; 4854 let Inst{23-20} = opc1; [all …]
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/external/llvm-project/llvm/lib/Target/ARM/ |
D | ARMInstrInfo.td | 4536 class SMLAL<bits<2> opc1, string asm> 4537 : AMulxyI64<0b0001010, opc1, 5307 def CDP : ABI<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1, 5309 NoItinerary, "cdp", "\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2", 5310 [(int_arm_cdp timm:$cop, timm:$opc1, timm:$CRd, timm:$CRn, 5313 bits<4> opc1; 5326 let Inst{23-20} = opc1; 5331 def CDP2 : ABXI<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1, 5333 NoItinerary, "cdp2\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2", 5334 [(int_arm_cdp2 timm:$cop, timm:$opc1, timm:$CRd, timm:$CRn, [all …]
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D | ARMInstrThumb2.td | 4454 : T2Cop<Op, oops, iops, opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2", 4462 bits<3> opc1; 4469 let Inst{23-21} = opc1; 4479 : T2Cop<Op, oops, iops, opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm", pattern> { 4487 bits<4> opc1; 4493 let Inst{7-4} = opc1; 4502 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn, 4504 [(int_arm_mcr timm:$cop, timm:$opc1, GPR:$Rt, timm:$CRn, 4507 def : t2InstAlias<"mcr${p} $cop, $opc1, $Rt, $CRn, $CRm", 4508 (t2MCR p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn, [all …]
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
D | ARMInstrInfo.td | 4386 class SMLAL<bits<2> opc1, string asm> 4387 : AMulxyI64<0b0001010, opc1, 5157 def CDP : ABI<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1, 5159 NoItinerary, "cdp", "\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2", 5160 [(int_arm_cdp timm:$cop, timm:$opc1, timm:$CRd, timm:$CRn, 5163 bits<4> opc1; 5176 let Inst{23-20} = opc1; 5181 def CDP2 : ABXI<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1, 5183 NoItinerary, "cdp2\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2", 5184 [(int_arm_cdp2 timm:$cop, timm:$opc1, timm:$CRd, timm:$CRn, [all …]
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D | ARMInstrThumb2.td | 4385 : T2Cop<Op, oops, iops, opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2", 4393 bits<3> opc1; 4400 let Inst{23-21} = opc1; 4410 : T2Cop<Op, oops, iops, opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm", pattern> { 4418 bits<4> opc1; 4424 let Inst{7-4} = opc1; 4433 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn, 4435 [(int_arm_mcr timm:$cop, timm:$opc1, GPR:$Rt, timm:$CRn, 4438 def : t2InstAlias<"mcr${p} $cop, $opc1, $Rt, $CRn, $CRm", 4439 (t2MCR p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn, [all …]
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/external/llvm-project/llvm/lib/Target/XCore/ |
D | XCoreInstrInfo.td | 213 multiclass F3R_2RUS<bits<5> opc1, bits<5> opc2, string OpcStr, SDNode OpNode> { 214 def _3r: _F3R<opc1, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c), 222 multiclass F3R_2RUS_np<bits<5> opc1, bits<5> opc2, string OpcStr> { 223 def _3r: _F3R<opc1, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c), 229 multiclass F3R_2RBITP<bits<5> opc1, bits<5> opc2, string OpcStr, 231 def _3r: _F3R<opc1, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c), 250 multiclass FL3R_L2RUS<bits<9> opc1, bits<9> opc2, string OpcStr, 252 def _l3r: _FL3R<opc1, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c), 261 multiclass FL3R_L2RBITP<bits<9> opc1, bits<9> opc2, string OpcStr, 263 def _l3r: _FL3R<opc1, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/XCore/ |
D | XCoreInstrInfo.td | 213 multiclass F3R_2RUS<bits<5> opc1, bits<5> opc2, string OpcStr, SDNode OpNode> { 214 def _3r: _F3R<opc1, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c), 222 multiclass F3R_2RUS_np<bits<5> opc1, bits<5> opc2, string OpcStr> { 223 def _3r: _F3R<opc1, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c), 229 multiclass F3R_2RBITP<bits<5> opc1, bits<5> opc2, string OpcStr, 231 def _3r: _F3R<opc1, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c), 250 multiclass FL3R_L2RUS<bits<9> opc1, bits<9> opc2, string OpcStr, 252 def _l3r: _FL3R<opc1, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c), 261 multiclass FL3R_L2RBITP<bits<9> opc1, bits<9> opc2, string OpcStr, 263 def _l3r: _FL3R<opc1, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
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/external/llvm/lib/Target/XCore/ |
D | XCoreInstrInfo.td | 221 multiclass F3R_2RUS<bits<5> opc1, bits<5> opc2, string OpcStr, SDNode OpNode> { 222 def _3r: _F3R<opc1, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c), 230 multiclass F3R_2RUS_np<bits<5> opc1, bits<5> opc2, string OpcStr> { 231 def _3r: _F3R<opc1, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c), 237 multiclass F3R_2RBITP<bits<5> opc1, bits<5> opc2, string OpcStr, 239 def _3r: _F3R<opc1, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c), 258 multiclass FL3R_L2RUS<bits<9> opc1, bits<9> opc2, string OpcStr, 260 def _l3r: _FL3R<opc1, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c), 269 multiclass FL3R_L2RBITP<bits<9> opc1, bits<9> opc2, string OpcStr, 271 def _l3r: _FL3R<opc1, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
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/external/mesa3d/src/gallium/drivers/nouveau/codegen/ |
D | nv50_ir_emit_gk110.cpp | 48 void emitForm_21(const Instruction *, uint32_t opc2, uint32_t opc1); 426 uint32_t opc1) in emitForm_21() argument 436 code[1] = opc1 << 20; in emitForm_21() 1848 uint64_t opc1, opc2; in emitSUCalc() local 1857 case OP_SUCLAMP: opc1 = 0xb00; opc2 = 0x580; break; in emitSUCalc() 1858 case OP_SUBFM: opc1 = 0xb68; opc2 = 0x1e8; break; in emitSUCalc() 1859 case OP_SUEAU: opc1 = 0xb6c; opc2 = 0x1ec; break; in emitSUCalc() 1864 emitForm_21(i, opc2, opc1); in emitSUCalc()
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/external/llvm/lib/Target/Hexagon/ |
D | HexagonInstrInfo.td | 5116 class T_shift_imm_acc_r <string opc1, string opc2, SDNode OpNode1, 5120 "$Rx "#opc2#opc1#"($Rs, #$u5)", 5146 class T_shift_reg_acc_r <string opc1, string opc2, SDNode OpNode1, 5150 "$Rx "#opc2#opc1#"($Rs, $Rt)", 5173 class T_shift_imm_acc_p <string opc1, string opc2, SDNode OpNode1, 5177 "$Rxx "#opc2#opc1#"($Rss, #$u6)", 5203 class T_shift_reg_acc_p <string opc1, string opc2, SDNode OpNode1, 5207 "$Rxx "#opc2#opc1#"($Rss, $Rt)", 5238 multiclass xtype_imm_acc<string opc1, SDNode OpNode, bits<2>minOp> { 5240 defm _acc : xtype_imm_base< opc1, "+= ", OpNode, add, 0b001, minOp>; [all …]
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/external/llvm/lib/Target/X86/ |
D | X86InstrControl.td | 85 multiclass ICBr<bits<8> opc1, bits<8> opc4, string asm, PatFrag Cond> { 86 def _1 : Ii8PCRel <opc1, RawFrm, (outs), (ins brtarget8:$dst), asm,
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/external/capstone/arch/AArch64/ |
D | ARMMappingInsnOp.inc | 106 { /* ARM_CDP, ARM_INS_CDP: cdp${p} $cop, $opc1, $crd, $crn, $crm, $opc2 */ 109 { /* ARM_CDP2, ARM_INS_CDP2: cdp2 $cop, $opc1, $crd, $crn, $crm, $opc2 */ 442 { /* ARM_MCR, ARM_INS_MCR: mcr${p} $cop, $opc1, $rt, $crn, $crm, $opc2 */ 445 { /* ARM_MCR2, ARM_INS_MCR2: mcr2 $cop, $opc1, $rt, $crn, $crm, $opc2 */ 448 { /* ARM_MCRR, ARM_INS_MCRR: mcrr${p} $cop, $opc1, $rt, $rt2, $crm */ 451 { /* ARM_MCRR2, ARM_INS_MCRR2: mcrr2 $cop, $opc1, $rt, $rt2, $crm */ 484 { /* ARM_MRC, ARM_INS_MRC: mrc${p} $cop, $opc1, $rt, $crn, $crm, $opc2 */ 487 { /* ARM_MRC2, ARM_INS_MRC2: mrc2 $cop, $opc1, $rt, $crn, $crm, $opc2 */ 490 { /* ARM_MRRC, ARM_INS_MRRC: mrrc${p} $cop, $opc1, $rt, $rt2, $crm */ 493 { /* ARM_MRRC2, ARM_INS_MRRC2: mrrc2 $cop, $opc1, $rt, $rt2, $crm */ [all …]
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/external/capstone/arch/ARM/ |
D | ARMMappingInsnOp.inc | 106 { /* ARM_CDP, ARM_INS_CDP: cdp${p} $cop, $opc1, $crd, $crn, $crm, $opc2 */ 109 { /* ARM_CDP2, ARM_INS_CDP2: cdp2 $cop, $opc1, $crd, $crn, $crm, $opc2 */ 442 { /* ARM_MCR, ARM_INS_MCR: mcr${p} $cop, $opc1, $rt, $crn, $crm, $opc2 */ 445 { /* ARM_MCR2, ARM_INS_MCR2: mcr2 $cop, $opc1, $rt, $crn, $crm, $opc2 */ 448 { /* ARM_MCRR, ARM_INS_MCRR: mcrr${p} $cop, $opc1, $rt, $rt2, $crm */ 451 { /* ARM_MCRR2, ARM_INS_MCRR2: mcrr2 $cop, $opc1, $rt, $rt2, $crm */ 484 { /* ARM_MRC, ARM_INS_MRC: mrc${p} $cop, $opc1, $rt, $crn, $crm, $opc2 */ 487 { /* ARM_MRC2, ARM_INS_MRC2: mrc2 $cop, $opc1, $rt, $crn, $crm, $opc2 */ 490 { /* ARM_MRRC, ARM_INS_MRRC: mrrc${p} $cop, $opc1, $rt, $rt2, $crm */ 493 { /* ARM_MRRC2, ARM_INS_MRRC2: mrrc2 $cop, $opc1, $rt, $rt2, $crm */ [all …]
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D | ARMGenAsmWriter.inc | 8929 // (MCR p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn, c_imm:$CRm, 0, pred:$p) 8940 // (MCR2 p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn, c_imm:$CRm, 0) 8984 // (MRC GPRwithAPSR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm, 0, pred:$p) 8995 // (MRC2 GPRwithAPSR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm, 0) 11000 // (t2MCR p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn, c_imm:$CRm, 0, pred:$p) 11011 // (t2MCR2 p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn, c_imm:$CRm, 0, pred:$p) 11031 // (t2MRC GPRwithAPSR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm, 0, pred:$p) 11042 // (t2MRC2 GPRwithAPSR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm, 0, pred:$p)
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D | ARMDisassembler.c | 5182 unsigned opc1 = fieldFromInstruction_4(Val, 4, 4); in DecodeMRRC2() local 5194 MCOperand_CreateImm0(Inst, opc1); in DecodeMRRC2()
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
D | AArch64InstrFormats.td | 4186 class BaseMemTag<bits<2> opc1, bits<2> opc2, string asm_insn, 4193 let Inst{23-22} = opc1; 4226 class BaseMemTagStore<bits<2> opc1, bits<2> opc2, string asm_insn, 4228 : BaseMemTag<opc1, opc2, asm_insn, asm_opnds, cstr, oops, iops> { 4238 multiclass MemTagStore<bits<2> opc1, string insn> { 4240 BaseMemTagStore<opc1, 0b10, insn, "\t$Rt, [$Rn, $offset]", "", 4243 BaseMemTagStore<opc1, 0b11, insn, "\t$Rt, [$Rn, $offset]!", 4248 BaseMemTagStore<opc1, 0b01, insn, "\t$Rt, [$Rn], $offset", 10316 bit opc1, bit opc2, RegisterOperand dst_reg, 10342 let Inst{15} = opc1; [all …]
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/external/llvm-project/llvm/lib/Target/AArch64/ |
D | AArch64InstrFormats.td | 4322 class BaseMemTag<bits<2> opc1, bits<2> opc2, string asm_insn, 4329 let Inst{23-22} = opc1; 4362 class BaseMemTagStore<bits<2> opc1, bits<2> opc2, string asm_insn, 4364 : BaseMemTag<opc1, opc2, asm_insn, asm_opnds, cstr, oops, iops> { 4374 multiclass MemTagStore<bits<2> opc1, string insn> { 4376 BaseMemTagStore<opc1, 0b10, insn, "\t$Rt, [$Rn, $offset]", "", 4379 BaseMemTagStore<opc1, 0b11, insn, "\t$Rt, [$Rn, $offset]!", 4384 BaseMemTagStore<opc1, 0b01, insn, "\t$Rt, [$Rn], $offset", 10714 bit opc1, bit opc2, RegisterOperand dst_reg, 10740 let Inst{15} = opc1; [all …]
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/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/ARM/ |
D | ARMGenGlobalISel.inc | 30886 // MIs[0] opc1 30892 … }):$opc1, GPRnopc:{ *:[i32] }:$Rt, GPRnopc:{ *:[i32] }:$Rt2, (timm:{ *:[i32] }):$CRm) => (MCRR … 30895 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // opc1 30914 // MIs[0] opc1 30920 … }):$opc1, GPRnopc:{ *:[i32] }:$Rt, GPRnopc:{ *:[i32] }:$Rt2, (timm:{ *:[i32] }):$CRm) => (MCRR2… 30923 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // opc1 30940 // MIs[0] opc1 30946 …32] }):$opc1, GPR:{ *:[i32] }:$Rt, GPR:{ *:[i32] }:$Rt2, (timm:{ *:[i32] }):$CRm) => (t2MCRR (ti… 30949 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // opc1 30968 // MIs[0] opc1 [all …]
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D | ARMGenMCCodeEmitter.inc | 7452 // op: opc1 7677 // op: opc1 7872 // op: opc1 7896 // op: opc1 12644 // op: opc1 15247 // op: opc1 15513 // op: opc1 15725 // op: opc1 15830 // op: opc1 15857 // op: opc1
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/external/llvm/lib/Target/ARM/Disassembler/ |
D | ARMDisassembler.cpp | 5274 unsigned opc1 = fieldFromInstruction(Val, 4, 4); in DecoderForMRRC2AndMCRR2() local 5302 Inst.addOperand(MCOperand::createImm(opc1)); in DecoderForMRRC2AndMCRR2()
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