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Searched refs:orv (Results 1 – 24 of 24) sorted by relevance

/external/llvm-project/llvm/test/MC/AArch64/SVE/
Dorv-diagnostics.s7 orv d0, p7, z31.b define
12 orv d0, p7, z31.h define
17 orv d0, p7, z31.s define
22 orv v0.2d, p7, z31.d label
31 orv h0, p8, z31.h label
36 orv h0, p7.b, z31.h label
41 orv h0, p7.q, z31.h label
51 orv d0, p7, z31.d define
57 orv d0, p7, z31.d define
Dorv.s10 orv b0, p7, z31.b label
16 orv h0, p7, z31.h label
22 orv s0, p7, z31.s label
28 orv d0, p7, z31.d define
/external/llvm-project/llvm/test/CodeGen/AArch64/
Dsve-int-reduce-pred.ll277 ; CHECK-NEXT: orv b0, p0, z0.b
280 %out = call i8 @llvm.aarch64.sve.orv.nxv16i8(<vscale x 16 x i1> %pg,
288 ; CHECK-NEXT: orv h0, p0, z0.h
291 %out = call i16 @llvm.aarch64.sve.orv.nxv8i16(<vscale x 8 x i1> %pg,
299 ; CHECK-NEXT: orv s0, p0, z0.s
302 %out = call i32 @llvm.aarch64.sve.orv.nxv4i32(<vscale x 4 x i1> %pg,
310 ; CHECK-NEXT: orv d0, p0, z0.d
313 %out = call i64 @llvm.aarch64.sve.orv.nxv2i64(<vscale x 2 x i1> %pg,
430 declare i8 @llvm.aarch64.sve.orv.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>)
431 declare i16 @llvm.aarch64.sve.orv.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>)
[all …]
Dsve-fixed-length-log-reduce.ll677 ; CHECK: orv b[[REDUCE:[0-9]+]], [[PG]], z0.b
688 ; CHECK: orv b[[REDUCE:[0-9]+]], [[PG]], z0.b
699 ; CHECK-NEXT: orv b[[REDUCE:[0-9]+]], [[PG]], [[OP]].b
711 ; VBITS_GE_512-NEXT: orv b[[REDUCE:[0-9]+]], [[PG]], [[OP]].b
721 ; VBITS_EQ_256-DAG: orv b[[REDUCE:[0-9]+]], [[PG]], [[OR]].b
734 ; VBITS_GE_1024-NEXT: orv b[[REDUCE:[0-9]+]], [[PG]], [[OP]].b
746 ; VBITS_GE_2048-NEXT: orv b[[REDUCE:[0-9]+]], [[PG]], [[OP]].b
758 ; CHECK: orv h[[REDUCE:[0-9]+]], [[PG]], z0.h
769 ; CHECK: orv h[[REDUCE:[0-9]+]], [[PG]], z0.h
780 ; CHECK-NEXT: orv h[[REDUCE:[0-9]+]], [[PG]], [[OP]].h
[all …]
Dsve-int-reduce.ll60 ; CHECK-NEXT: orv b0, p0, z0.b
71 ; CHECK-NEXT: orv h0, p0, z0.h
82 ; CHECK-NEXT: orv s0, p0, z0.s
93 ; CHECK-NEXT: orv d0, p0, z0.d
Dsve-split-int-reduce.ll39 ; CHECK-NEXT: orv d0, p0, z0.d
54 ; CHECK-NEXT: orv d0, p0, z0.d
/external/vixl/test/aarch64/
Dtest-disasm-sve-aarch64.cc2850 COMPARE_PREFIX(orv(b4, p0, z16.VnB()), "orv b4, p0, z16.b"); in TEST()
2851 COMPARE_PREFIX(orv(h6, p2, z18.VnH()), "orv h6, p2, z18.h"); in TEST()
2852 COMPARE_PREFIX(orv(s8, p4, z20.VnS()), "orv s8, p4, z20.s"); in TEST()
2853 COMPARE_PREFIX(orv(d10, p6, z22.VnD()), "orv d10, p6, z22.d"); in TEST()
/external/vixl/src/aarch64/
Dsimulator-aarch64.h4230 LogicVRegister orv(VectorFormat vform,
Dassembler-aarch64.h5103 void orv(const VRegister& vd, const PRegister& pg, const ZRegister& zn);
Dassembler-sve-aarch64.cc3269 void Assembler::orv(const VRegister& vd, in orv() function in vixl::aarch64::Assembler
Dlogic-aarch64.cc2279 LogicVRegister Simulator::orv(VectorFormat vform, in orv() function in vixl::aarch64::Simulator
Dmacro-assembler-aarch64.h5468 orv(vd, pg, zn); in Orv()
Dsimulator-aarch64.cc9328 orv(vform, vd, pg, zn); in VisitSVEIntReduction()
/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/AArch64/
DAArch64GenAsmMatcher.inc12546 "\003orr\004orrs\003orv\005pacda\005pacdb\006pacdza\006pacdzb\005pacga\005"
16872 …{ 3504 /* orv */, AArch64::ORV_VPZ_H, Convert__Reg1_0__SVEPredicate3bAnyReg1_1__SVEVectorHReg1_2, …
16873 …{ 3504 /* orv */, AArch64::ORV_VPZ_S, Convert__Reg1_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_2, …
16874 …{ 3504 /* orv */, AArch64::ORV_VPZ_D, Convert__Reg1_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_2, …
16875 …{ 3504 /* orv */, AArch64::ORV_VPZ_B, Convert__Reg1_0__SVEPredicate3bAnyReg1_1__SVEVectorBReg1_2, …
24245 …{ 3504 /* orv */, AArch64::ORV_VPZ_H, Convert__Reg1_0__SVEPredicate3bAnyReg1_1__SVEVectorHReg1_2, …
24246 …{ 3504 /* orv */, AArch64::ORV_VPZ_S, Convert__Reg1_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_2, …
24247 …{ 3504 /* orv */, AArch64::ORV_VPZ_D, Convert__Reg1_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_2, …
24248 …{ 3504 /* orv */, AArch64::ORV_VPZ_B, Convert__Reg1_0__SVEPredicate3bAnyReg1_1__SVEVectorBReg1_2, …
35419 { 3504 /* orv */, 2 /* 1 */, MCK_SVEPredicate3bAnyReg, AMFBS_HasSVE },
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64SVEInstrInfo.td128 defm ORV_VPZ : sve_int_reduce_2<0b000, "orv", AArch64orv_pred>;
/external/llvm-project/llvm/lib/Target/AArch64/
DAArch64SVEInstrInfo.td329 defm ORV_VPZ : sve_int_reduce_2<0b000, "orv", AArch64orv_p>;
/external/cldr/tools/java/org/unicode/cldr/util/data/languages/
DentityToCode.tsv2207 http://www.wikidata.org/entity/Q35228 orv
/external/cldr/tools/java/org/unicode/cldr/util/data/
Diso-639-3_Name_Index.tab5287 orv Old Russian Russian, Old
Diso-639-3.tab5051 orv I H Old Russian
Dlanguage-subtag-registry27566 Subtag: orv
/external/hyphenation-patterns/hu/
Dhyph-hu.pat.txt39825 1orv.
39827 2orvá
/external/swiftshader/third_party/llvm-10.0/configs/common/include/llvm/IR/
DIntrinsicImpl.inc686 "llvm.aarch64.sve.orv",
10819 1, // llvm.aarch64.sve.orv
/external/cldr/tools/java/org/unicode/cldr/util/data/transforms/
Dinternal_raw_IPA-old.txt43451 corvus %8306 kˈorvəs, kˈɔrvəs
65613 ethchlorvynol ɛθklˈorvənˌol
Dinternal_raw_IPA.txt36729 corvus %22407 kˈorvəs, kˈɔrvəs
55367 ethchlorvynol %28983 ɛθklˈorvənˌol