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Searched refs:plat_params_from_bl2_t (Results 1 – 12 of 12) sorted by relevance

/external/arm-trusted-firmware/plat/nvidia/tegra/common/
Dtegra_bl31_setup.c47 static plat_params_from_bl2_t plat_bl31_params_from_bl2 = {
82 plat_params_from_bl2_t *bl31_get_plat_params(void) in bl31_get_plat_params()
95 plat_params_from_bl2_t *plat_params = (plat_params_from_bl2_t *)arg1; in bl31_early_platform_setup2()
280 const plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params(); in bl31_plat_arch_setup()
Dtegra_pm.c156 const plat_params_from_bl2_t *plat_params; in tegra_pwr_domain_on_finish()
/external/arm-trusted-firmware/plat/nvidia/tegra/soc/t210/
Dplat_setup.c155 plat_params_from_bl2_t *plat_get_bl31_plat_params(void) in plat_get_bl31_plat_params()
165 const plat_params_from_bl2_t *plat_params = bl31_get_plat_params(); in plat_early_platform_setup()
204 const plat_params_from_bl2_t *plat_params = bl31_get_plat_params(); in plat_late_platform_setup()
281 const plat_params_from_bl2_t *plat_params = bl31_get_plat_params(); in plat_supports_system_suspend()
Dplat_psci_handlers.c47 const plat_params_from_bl2_t *plat_params = bl31_get_plat_params(); in tegra_soc_validate_power_state()
347 const plat_params_from_bl2_t *plat_params = bl31_get_plat_params(); in tegra_soc_pwr_domain_power_down_wfi()
435 const plat_params_from_bl2_t *plat_params = bl31_get_plat_params(); in tegra_soc_pwr_domain_on_finish()
/external/arm-trusted-firmware/plat/nvidia/tegra/include/
Dtegra_private.h52 } plat_params_from_bl2_t; typedef
85 plat_params_from_bl2_t *plat_get_bl31_plat_params(void);
127 plat_params_from_bl2_t *bl31_get_plat_params(void);
/external/arm-trusted-firmware/plat/nvidia/tegra/soc/t186/
Dplat_setup.c189 const plat_params_from_bl2_t *plat_params = bl31_get_plat_params(); in plat_early_platform_setup()
274 plat_params_from_bl2_t *plat_get_bl31_plat_params(void) in plat_get_bl31_plat_params()
280 return (plat_params_from_bl2_t *)(uintptr_t)val; in plat_get_bl31_plat_params()
326 const plat_params_from_bl2_t *plat_bl31_params = plat_get_bl31_plat_params(); in plat_relocate_bl32_image()
Dplat_psci_handlers.c106 const plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params(); in tegra_soc_pwr_domain_suspend()
283 const plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params(); in tegra_soc_pwr_domain_power_down_wfi()
376 const plat_params_from_bl2_t *plat_params = bl31_get_plat_params(); in tegra_soc_pwr_domain_on_finish()
/external/arm-trusted-firmware/plat/nvidia/tegra/soc/t132/
Dplat_setup.c139 plat_params_from_bl2_t *plat_get_bl31_plat_params(void) in plat_get_bl31_plat_params()
149 plat_params_from_bl2_t *plat_params = bl31_get_plat_params(); in plat_early_platform_setup()
/external/arm-trusted-firmware/plat/nvidia/tegra/soc/t194/
Dplat_setup.c242 const plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params(); in plat_early_platform_setup()
385 plat_params_from_bl2_t *plat_get_bl31_plat_params(void) in plat_get_bl31_plat_params()
394 return (plat_params_from_bl2_t *)(uintptr_t)val; in plat_get_bl31_plat_params()
Dplat_psci_handlers.c118 plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params(); in tegra_soc_pwr_domain_suspend()
267 plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params(); in tegra_soc_pwr_domain_power_down_wfi()
346 const plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params(); in tegra_soc_pwr_domain_on_finish()
Dplat_secondary.c32 plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params(); in plat_secondary_setup()
/external/arm-trusted-firmware/plat/nvidia/tegra/drivers/memctrl/
Dmemctrl_v2.c123 const plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params(); in tegra_mc_save_context()