1 /*
2 * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
3 * Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8 #include <arch_helpers.h>
9 #include <assert.h>
10 #include <common/bl_common.h>
11 #include <drivers/console.h>
12 #include <lib/xlat_tables/xlat_tables_v2.h>
13 #include <memctrl.h>
14 #include <plat/common/platform.h>
15 #include <tegra_def.h>
16 #include <tegra_platform.h>
17 #include <tegra_private.h>
18
19 /* sets of MMIO ranges setup */
20 #define MMIO_RANGE_0_ADDR 0x50000000
21 #define MMIO_RANGE_1_ADDR 0x60000000
22 #define MMIO_RANGE_2_ADDR 0x70000000
23 #define MMIO_RANGE_SIZE 0x200000
24
25 /*
26 * Table of regions to map using the MMU.
27 */
28 static const mmap_region_t tegra_mmap[] = {
29 MAP_REGION_FLAT(MMIO_RANGE_0_ADDR, MMIO_RANGE_SIZE,
30 MT_DEVICE | MT_RW | MT_SECURE),
31 MAP_REGION_FLAT(MMIO_RANGE_1_ADDR, MMIO_RANGE_SIZE,
32 MT_DEVICE | MT_RW | MT_SECURE),
33 MAP_REGION_FLAT(MMIO_RANGE_2_ADDR, MMIO_RANGE_SIZE,
34 MT_DEVICE | MT_RW | MT_SECURE),
35 {0}
36 };
37
38 /*******************************************************************************
39 * Set up the pagetables as per the platform memory map & initialize the MMU
40 ******************************************************************************/
plat_get_mmio_map(void)41 const mmap_region_t *plat_get_mmio_map(void)
42 {
43 /* MMIO space */
44 return tegra_mmap;
45 }
46
47 /*******************************************************************************
48 * The Tegra power domain tree has a single system level power domain i.e. a
49 * single root node. The first entry in the power domain descriptor specifies
50 * the number of power domains at the highest power level.
51 *******************************************************************************
52 */
53 const unsigned char tegra_power_domain_tree_desc[] = {
54 /* No of root nodes */
55 1,
56 /* No of clusters */
57 PLATFORM_CLUSTER_COUNT,
58 /* No of CPU cores */
59 PLATFORM_CORE_COUNT,
60 };
61
62 /*******************************************************************************
63 * This function returns the Tegra default topology tree information.
64 ******************************************************************************/
plat_get_power_domain_tree_desc(void)65 const unsigned char *plat_get_power_domain_tree_desc(void)
66 {
67 return tegra_power_domain_tree_desc;
68 }
69
plat_get_syscnt_freq2(void)70 unsigned int plat_get_syscnt_freq2(void)
71 {
72 return 12000000;
73 }
74
75 /*******************************************************************************
76 * Maximum supported UART controllers
77 ******************************************************************************/
78 #define TEGRA132_MAX_UART_PORTS 5
79
80 /*******************************************************************************
81 * This variable holds the UART port base addresses
82 ******************************************************************************/
83 static uint32_t tegra132_uart_addresses[TEGRA132_MAX_UART_PORTS + 1] = {
84 0, /* undefined - treated as an error case */
85 TEGRA_UARTA_BASE,
86 TEGRA_UARTB_BASE,
87 TEGRA_UARTC_BASE,
88 TEGRA_UARTD_BASE,
89 TEGRA_UARTE_BASE,
90 };
91
92 /*******************************************************************************
93 * Enable console corresponding to the console ID
94 ******************************************************************************/
plat_enable_console(int32_t id)95 void plat_enable_console(int32_t id)
96 {
97 static console_t uart_console;
98 uint32_t console_clock;
99
100 if ((id > 0) && (id < TEGRA132_MAX_UART_PORTS)) {
101 /*
102 * Reference clock used by the FPGAs is a lot slower.
103 */
104 if (tegra_platform_is_fpga()) {
105 console_clock = TEGRA_BOOT_UART_CLK_13_MHZ;
106 } else {
107 console_clock = TEGRA_BOOT_UART_CLK_408_MHZ;
108 }
109
110 (void)console_16550_register(tegra132_uart_addresses[id],
111 console_clock,
112 TEGRA_CONSOLE_BAUDRATE,
113 &uart_console);
114 console_set_scope(&uart_console, CONSOLE_FLAG_BOOT |
115 CONSOLE_FLAG_RUNTIME | CONSOLE_FLAG_CRASH);
116 }
117 }
118
119 /*******************************************************************************
120 * Initialize the GIC and SGIs
121 ******************************************************************************/
plat_gic_setup(void)122 void plat_gic_setup(void)
123 {
124 tegra_gic_setup(NULL, 0);
125 tegra_gic_init();
126 }
127
128 /*******************************************************************************
129 * Return pointer to the BL31 params from previous bootloader
130 ******************************************************************************/
plat_get_bl31_params(void)131 struct tegra_bl31_params *plat_get_bl31_params(void)
132 {
133 return NULL;
134 }
135
136 /*******************************************************************************
137 * Return pointer to the BL31 platform params from previous bootloader
138 ******************************************************************************/
plat_get_bl31_plat_params(void)139 plat_params_from_bl2_t *plat_get_bl31_plat_params(void)
140 {
141 return NULL;
142 }
143
144 /*******************************************************************************
145 * Handler for early platform setup
146 ******************************************************************************/
plat_early_platform_setup(void)147 void plat_early_platform_setup(void)
148 {
149 plat_params_from_bl2_t *plat_params = bl31_get_plat_params();
150
151 /* Verify chip id is t132 */
152 assert(tegra_chipid_is_t132());
153
154 /*
155 * Do initial security configuration to allow DRAM/device access.
156 */
157 tegra_memctrl_tzdram_setup(plat_params->tzdram_base,
158 (uint32_t)plat_params->tzdram_size);
159 }
160
161 /*******************************************************************************
162 * Handler for late platform setup
163 ******************************************************************************/
plat_late_platform_setup(void)164 void plat_late_platform_setup(void)
165 {
166 ; /* do nothing */
167 }
168
169 /*******************************************************************************
170 * Handler to indicate support for System Suspend
171 ******************************************************************************/
plat_supports_system_suspend(void)172 bool plat_supports_system_suspend(void)
173 {
174 return true;
175 }
176
177 /*******************************************************************************
178 * Platform specific runtime setup.
179 ******************************************************************************/
plat_runtime_setup(void)180 void plat_runtime_setup(void)
181 {
182 /*
183 * During cold boot, it is observed that the arbitration
184 * bit is set in the Memory controller leading to false
185 * error interrupts in the non-secure world. To avoid
186 * this, clean the interrupt status register before
187 * booting into the non-secure world
188 */
189 tegra_memctrl_clear_pending_interrupts();
190
191 /*
192 * During boot, USB3 and flash media (SDMMC/SATA) devices need
193 * access to IRAM. Because these clients connect to the MC and
194 * do not have a direct path to the IRAM, the MC implements AHB
195 * redirection during boot to allow path to IRAM. In this mode
196 * accesses to a programmed memory address aperture are directed
197 * to the AHB bus, allowing access to the IRAM. This mode must be
198 * disabled before we jump to the non-secure world.
199 */
200 tegra_memctrl_disable_ahb_redirection();
201 }
202