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123

/external/llvm-project/llvm/lib/Target/PowerPC/
DPPCInstr64Bit.td281 def LDAT : X_RD5_RS5_IM5<31, 614, (outs g8rc:$rD), (ins g8rc:$rA, u5imm:$FC),
282 "ldat $rD, $rA, $FC", IIC_LdStLoad>, isPPC64,
291 def STDAT : X_RD5_RS5_IM5<31, 742, (outs), (ins g8rc:$rS, g8rc:$rA, u5imm:$FC),
292 "stdat $rS, $rA, $FC", IIC_LdStStore>, isPPC64,
487 defm NAND8: XForm_6r<31, 476, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
488 "nand", "$rA, $rS, $rB", IIC_IntSimple,
489 [(set i64:$rA, (not (and i64:$rS, i64:$rB)))]>;
490 defm AND8 : XForm_6r<31, 28, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
491 "and", "$rA, $rS, $rB", IIC_IntSimple,
492 [(set i64:$rA, (and i64:$rS, i64:$rB))]>;
[all …]
DPPCInstrInfo.td2125 def LWAT : X_RD5_RS5_IM5<31, 582, (outs gprc:$rD), (ins gprc:$rA, u5imm:$FC),
2126 "lwat $rD, $rA, $FC", IIC_LdStLoad>,
2144 def STWAT : X_RD5_RS5_IM5<31, 710, (outs), (ins gprc:$rS, gprc:$rA, u5imm:$FC),
2145 "stwat $rS, $rA, $FC", IIC_LdStStore>,
2151 def TWI : DForm_base<3, (outs), (ins u5imm:$to, gprc:$rA, s16imm:$imm),
2152 "twi $to, $rA, $imm", IIC_IntTrapW, []>;
2153 def TW : XForm_1<31, 4, (outs), (ins u5imm:$to, gprc:$rA, gprc:$rB),
2154 "tw $to, $rA, $rB", IIC_IntTrapW, []>;
2155 def TDI : DForm_base<2, (outs), (ins u5imm:$to, g8rc:$rA, s16imm:$imm),
2156 "tdi $to, $rA, $imm", IIC_IntTrapD, []>;
[all …]
DREADME_P9.txt23 (set i64:$rD, (int_ppc_altivec_vextublx i64:$rA, v16i8:$vB))
24 (set i64:$rD, (int_ppc_altivec_vextuhlx i64:$rA, v8i16:$vB))
25 (set i64:$rD, (int_ppc_altivec_vextuwlx i64:$rA, v4i32:$vB))
28 (set i64:$rD, (int_ppc_altivec_vextubrx i64:$rA, v16i8:$vB))
29 (set i64:$rD, (int_ppc_altivec_vextuhrx i64:$rA, v8i16:$vB))
30 (set i64:$rD, (int_ppc_altivec_vextuwrx i64:$rA, v4i32:$vB))
94 (set v4i32:$rT, (ineg v4i32:$rA)) // vnegw
95 (set v2i64:$rT, (ineg v2i64:$rA)) // vnegd
386 // Note: rA and rB are the unsigned integer value.
387 (set f128:$XT, (int_ppc_vsx_xsiexpdp i64:$rA, i64:$rB))
[all …]
DPPCInstrPrefix.td318 : VXForm_1<xo, (outs vrrc:$vD), (ins vrrc:$vDi, gprc:$rA, vrrc:$vB),
319 !strconcat(opc, " $vD, $rA, $vB"), IIC_VecGeneral, pattern>,
325 : VXForm_1<xo, (outs vrrc:$vD), (ins vrrc:$vDi, gprc:$rA, gprc:$rB),
326 !strconcat(opc, " $vD, $rA, $rB"), IIC_VecGeneral, pattern>,
1954 (int_ppc_altivec_vinsbvlx v16i8:$vDi, i32:$rA,
1959 (int_ppc_altivec_vinsbvrx v16i8:$vDi, i32:$rA,
1964 (int_ppc_altivec_vinshvlx v8i16:$vDi, i32:$rA,
1969 (int_ppc_altivec_vinshvrx v8i16:$vDi, i32:$rA,
1974 (int_ppc_altivec_vinswvlx v4i32:$vDi, i32:$rA,
1979 (int_ppc_altivec_vinswvrx v4i32:$vDi, i32:$rA,
[all …]
DPPCInstrAltivec.td362 def DST : DSS_Form<0, 342, (outs), (ins u5imm:$STRM, gprc:$rA, gprc:$rB),
363 "dst $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/,
364 [(int_ppc_altivec_dst i32:$rA, i32:$rB, imm:$STRM)]>,
367 def DSTT : DSS_Form<1, 342, (outs), (ins u5imm:$STRM, gprc:$rA, gprc:$rB),
368 "dstt $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/,
369 [(int_ppc_altivec_dstt i32:$rA, i32:$rB, imm:$STRM)]>,
372 def DSTST : DSS_Form<0, 374, (outs), (ins u5imm:$STRM, gprc:$rA, gprc:$rB),
373 "dstst $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/,
374 [(int_ppc_altivec_dstst i32:$rA, i32:$rB, imm:$STRM)]>,
377 def DSTSTT : DSS_Form<1, 374, (outs), (ins u5imm:$STRM, gprc:$rA, gprc:$rB),
[all …]
DPPCInstrVSX.td1298 def MFVSRD : XX1_RS6_RD5_XO<31, 51, (outs g8rc:$rA), (ins vsfrc:$XT),
1299 "mfvsrd $rA, $XT", IIC_VecGeneral,
1300 [(set i64:$rA, (PPCmfvsr f64:$XT))]>,
1304 def MFVRD : XX1_RS6_RD5_XO<31, 51, (outs g8rc:$rA), (ins vsrc:$XT),
1305 "mfvsrd $rA, $XT", IIC_VecGeneral,
1308 def MFVSRWZ : XX1_RS6_RD5_XO<31, 115, (outs gprc:$rA), (ins vsfrc:$XT),
1309 "mfvsrwz $rA, $XT", IIC_VecGeneral,
1310 [(set i32:$rA, (PPCmfvsr f64:$XT))]>;
1313 def MFVRWZ : XX1_RS6_RD5_XO<31, 115, (outs gprc:$rA), (ins vsrc:$XT),
1314 "mfvsrwz $rA, $XT", IIC_VecGeneral,
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/
DPPCInstr64Bit.td261 def LDAT : X_RD5_RS5_IM5<31, 614, (outs g8rc:$rD), (ins g8rc:$rA, u5imm:$FC),
262 "ldat $rD, $rA, $FC", IIC_LdStLoad>, isPPC64,
271 def STDAT : X_RD5_RS5_IM5<31, 742, (outs), (ins g8rc:$rS, g8rc:$rA, u5imm:$FC),
272 "stdat $rS, $rA, $FC", IIC_LdStStore>, isPPC64,
449 defm NAND8: XForm_6r<31, 476, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
450 "nand", "$rA, $rS, $rB", IIC_IntSimple,
451 [(set i64:$rA, (not (and i64:$rS, i64:$rB)))]>;
452 defm AND8 : XForm_6r<31, 28, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
453 "and", "$rA, $rS, $rB", IIC_IntSimple,
454 [(set i64:$rA, (and i64:$rS, i64:$rB))]>;
[all …]
DPPCInstrInfo.td1933 def LWAT : X_RD5_RS5_IM5<31, 582, (outs gprc:$rD), (ins gprc:$rA, u5imm:$FC),
1934 "lwat $rD, $rA, $FC", IIC_LdStLoad>,
1952 def STWAT : X_RD5_RS5_IM5<31, 710, (outs), (ins gprc:$rS, gprc:$rA, u5imm:$FC),
1953 "stwat $rS, $rA, $FC", IIC_LdStStore>,
1959 def TWI : DForm_base<3, (outs), (ins u5imm:$to, gprc:$rA, s16imm:$imm),
1960 "twi $to, $rA, $imm", IIC_IntTrapW, []>;
1961 def TW : XForm_1<31, 4, (outs), (ins u5imm:$to, gprc:$rA, gprc:$rB),
1962 "tw $to, $rA, $rB", IIC_IntTrapW, []>;
1963 def TDI : DForm_base<2, (outs), (ins u5imm:$to, g8rc:$rA, s16imm:$imm),
1964 "tdi $to, $rA, $imm", IIC_IntTrapD, []>;
[all …]
DREADME_P9.txt23 (set i64:$rD, (int_ppc_altivec_vextublx i64:$rA, v16i8:$vB))
24 (set i64:$rD, (int_ppc_altivec_vextuhlx i64:$rA, v8i16:$vB))
25 (set i64:$rD, (int_ppc_altivec_vextuwlx i64:$rA, v4i32:$vB))
28 (set i64:$rD, (int_ppc_altivec_vextubrx i64:$rA, v16i8:$vB))
29 (set i64:$rD, (int_ppc_altivec_vextuhrx i64:$rA, v8i16:$vB))
30 (set i64:$rD, (int_ppc_altivec_vextuwrx i64:$rA, v4i32:$vB))
94 (set v4i32:$rT, (ineg v4i32:$rA)) // vnegw
95 (set v2i64:$rT, (ineg v2i64:$rA)) // vnegd
386 // Note: rA and rB are the unsigned integer value.
387 (set f128:$XT, (int_ppc_vsx_xsiexpdp i64:$rA, i64:$rB))
[all …]
DPPCInstrAltivec.td362 def DST : DSS_Form<0, 342, (outs), (ins u5imm:$STRM, gprc:$rA, gprc:$rB),
363 "dst $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/,
364 [(int_ppc_altivec_dst i32:$rA, i32:$rB, imm:$STRM)]>,
367 def DSTT : DSS_Form<1, 342, (outs), (ins u5imm:$STRM, gprc:$rA, gprc:$rB),
368 "dstt $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/,
369 [(int_ppc_altivec_dstt i32:$rA, i32:$rB, imm:$STRM)]>,
372 def DSTST : DSS_Form<0, 374, (outs), (ins u5imm:$STRM, gprc:$rA, gprc:$rB),
373 "dstst $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/,
374 [(int_ppc_altivec_dstst i32:$rA, i32:$rB, imm:$STRM)]>,
377 def DSTSTT : DSS_Form<1, 374, (outs), (ins u5imm:$STRM, gprc:$rA, gprc:$rB),
[all …]
DPPCInstrVSX.td1646 def MFVSRD : XX1_RS6_RD5_XO<31, 51, (outs g8rc:$rA), (ins vsfrc:$XT),
1647 "mfvsrd $rA, $XT", IIC_VecGeneral,
1648 [(set i64:$rA, (PPCmfvsr f64:$XT))]>,
1651 def MFVRD : XX1_RS6_RD5_XO<31, 51, (outs g8rc:$rA), (ins vsrc:$XT),
1652 "mfvsrd $rA, $XT", IIC_VecGeneral,
1655 def MFVSRWZ : XX1_RS6_RD5_XO<31, 115, (outs gprc:$rA), (ins vsfrc:$XT),
1656 "mfvsrwz $rA, $XT", IIC_VecGeneral,
1657 [(set i32:$rA, (PPCmfvsr f64:$XT))]>;
1659 def MFVRWZ : XX1_RS6_RD5_XO<31, 115, (outs gprc:$rA), (ins vsrc:$XT),
1660 "mfvsrwz $rA, $XT", IIC_VecGeneral,
[all …]
/external/llvm/lib/Target/PowerPC/
DPPCInstr64Bit.td249 def LDAT : X_RD5_RS5_IM5<31, 614, (outs g8rc:$rD), (ins g8rc:$rA, u5imm:$FC),
250 "ldat $rD, $rA, $FC", IIC_LdStLoad>, isPPC64,
259 def STDAT : X_RD5_RS5_IM5<31, 742, (outs), (ins g8rc:$rS, g8rc:$rA, u5imm:$FC),
260 "stdat $rS, $rA, $FC", IIC_LdStStore>, isPPC64,
430 defm NAND8: XForm_6r<31, 476, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
431 "nand", "$rA, $rS, $rB", IIC_IntSimple,
432 [(set i64:$rA, (not (and i64:$rS, i64:$rB)))]>;
433 defm AND8 : XForm_6r<31, 28, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
434 "and", "$rA, $rS, $rB", IIC_IntSimple,
435 [(set i64:$rA, (and i64:$rS, i64:$rB))]>;
[all …]
DPPCInstrInfo.td1600 def LWAT : X_RD5_RS5_IM5<31, 582, (outs gprc:$rD), (ins gprc:$rA, u5imm:$FC),
1601 "lwat $rD, $rA, $FC", IIC_LdStLoad>,
1619 def STWAT : X_RD5_RS5_IM5<31, 710, (outs), (ins gprc:$rS, gprc:$rA, u5imm:$FC),
1620 "stwat $rS, $rA, $FC", IIC_LdStStore>,
1626 def TWI : DForm_base<3, (outs), (ins u5imm:$to, gprc:$rA, s16imm:$imm),
1627 "twi $to, $rA, $imm", IIC_IntTrapW, []>;
1628 def TW : XForm_1<31, 4, (outs), (ins u5imm:$to, gprc:$rA, gprc:$rB),
1629 "tw $to, $rA, $rB", IIC_IntTrapW, []>;
1630 def TDI : DForm_base<2, (outs), (ins u5imm:$to, g8rc:$rA, s16imm:$imm),
1631 "tdi $to, $rA, $imm", IIC_IntTrapD, []>;
[all …]
DREADME_P9.txt23 (set i64:$rD, (int_ppc_altivec_vextublx i64:$rA, v16i8:$vB))
24 (set i64:$rD, (int_ppc_altivec_vextuhlx i64:$rA, v8i16:$vB))
25 (set i64:$rD, (int_ppc_altivec_vextuwlx i64:$rA, v4i32:$vB))
28 (set i64:$rD, (int_ppc_altivec_vextubrx i64:$rA, v16i8:$vB))
29 (set i64:$rD, (int_ppc_altivec_vextuhrx i64:$rA, v8i16:$vB))
30 (set i64:$rD, (int_ppc_altivec_vextuwrx i64:$rA, v4i32:$vB))
94 (set v4i32:$rT, (ineg v4i32:$rA)) // vnegw
95 (set v2i64:$rT, (ineg v2i64:$rA)) // vnegd
386 // Note: rA and rB are the unsigned integer value.
387 (set f128:$XT, (int_ppc_vsx_xsiexpdp i64:$rA, i64:$rB))
[all …]
DPPCInstrAltivec.td357 def DST : DSS_Form<0, 342, (outs), (ins u5imm:$STRM, gprc:$rA, gprc:$rB),
358 "dst $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/,
359 [(int_ppc_altivec_dst i32:$rA, i32:$rB, imm:$STRM)]>,
362 def DSTT : DSS_Form<1, 342, (outs), (ins u5imm:$STRM, gprc:$rA, gprc:$rB),
363 "dstt $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/,
364 [(int_ppc_altivec_dstt i32:$rA, i32:$rB, imm:$STRM)]>,
367 def DSTST : DSS_Form<0, 374, (outs), (ins u5imm:$STRM, gprc:$rA, gprc:$rB),
368 "dstst $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/,
369 [(int_ppc_altivec_dstst i32:$rA, i32:$rB, imm:$STRM)]>,
372 def DSTSTT : DSS_Form<1, 374, (outs), (ins u5imm:$STRM, gprc:$rA, gprc:$rB),
[all …]
DPPCInstrVSX.td1243 def MFVSRD : XX1_RS6_RD5_XO<31, 51, (outs g8rc:$rA), (ins vsfrc:$XT),
1244 "mfvsrd $rA, $XT", IIC_VecGeneral,
1245 [(set i64:$rA, (PPCmfvsr f64:$XT))]>,
1247 def MFVSRWZ : XX1_RS6_RD5_XO<31, 115, (outs gprc:$rA), (ins vsfrc:$XT),
1248 "mfvsrwz $rA, $XT", IIC_VecGeneral,
1249 [(set i32:$rA, (PPCmfvsr f64:$XT))]>;
1250 def MTVSRD : XX1_RS6_RD5_XO<31, 179, (outs vsfrc:$XT), (ins g8rc:$rA),
1251 "mtvsrd $XT, $rA", IIC_VecGeneral,
1252 [(set f64:$XT, (PPCmtvsra i64:$rA))]>,
1254 def MTVSRWA : XX1_RS6_RD5_XO<31, 211, (outs vsfrc:$XT), (ins gprc:$rA),
[all …]
/external/llvm-project/llvm/test/Transforms/InstCombine/
Dcast_phi.ll104 %rA.sroa.8.0 = phi i32 [ %rA.sroa.8.2, %.bb12 ], [ %1, %.bb2 ]
105 %rA.sroa.0.0 = phi i32 [ %rA.sroa.0.2, %.bb12 ], [ %1, %.bb2 ]
123 %11 = bitcast i32 %rA.sroa.8.0 to float
126 %13 = bitcast i32 %rA.sroa.0.0 to float
132 %rA.sroa.8.1 = phi i32 [ %12, %.bb4 ], [ %rA.sroa.8.0, %.bb3 ]
133 %rA.sroa.0.1 = phi i32 [ %14, %.bb4 ], [ %rA.sroa.0.0, %.bb3 ]
137 store i32 %rA.sroa.0.1, i32* %2, align 4
138 store i32 %rA.sroa.8.1, i32* %3, align 4
153 %19 = bitcast i32 %rA.sroa.8.1 to float
156 %21 = bitcast i32 %rA.sroa.0.1 to float
[all …]
/external/mesa3d/src/gallium/drivers/nouveau/codegen/
Dnv50_ir_util.cpp180 for (Range *rA = this->head; rA; rA = rA->next) in overlaps()
182 if (rB->bgn < rA->end && in overlaps()
183 rB->end > rA->bgn) in overlaps()
/external/neven/Embedded/common/src/b_BasicEm/
DMath.c1048 …ltiplyFlt16( const int16 *x1A, int16 row1A, int16 col1A, const int16 *x2A, int16 col2A, int16 *rA ) in bbs_matMultiplyFlt16() argument
1071 *rA++ = ( sumL + ( 1 << 14 ) ) >> 15; /* round result to 1.15 */ in bbs_matMultiplyFlt16()
1075 else mmul( ( int16* ) x1A, row1A, col1A, ( int16* ) x2A, col1A, col2A, rA ); in bbs_matMultiplyFlt16()
1102 *rA++ = ( sumL + ( 1 << 14 ) ) >> 15; /* round result to 1.15 */ in bbs_matMultiplyFlt16()
1123 *rA++ = ( sumL + ( 1 << 14 ) ) >> 15; /* round result to 1.15 */ in bbs_matMultiplyFlt16()
1132 const int16 *x2A, int16 col2A, int16 *rA ) in bbs_matMultiplyTranspFlt16() argument
1156 *rA++ = ( sumL + ( 1 << 14 ) ) >> 15; /* round result to 1.15 */ in bbs_matMultiplyTranspFlt16()
1167 uint16 bbs_matTrans( int16 *xA, int16 rowA, int16 colA, int16 *rA ) in bbs_matTrans() argument
1177 *rA++ = *sL; in bbs_matTrans()
DMath.h181 const int16 *x2A, int16 col2A, int16 *rA );
185 const int16 *x2A, int16 row2A, int16 *rA );
/external/capstone/arch/PowerPC/
DPPCGenAsmWriter.inc6638 // (CMPD CR0, g8rc:$rA, g8rc:$rB)
6648 // (CMPDI CR0, g8rc:$rA, s16imm64:$imm)
6660 // (CMPLD CR0, g8rc:$rA, g8rc:$rB)
6670 // (CMPLDI CR0, g8rc:$rA, u16imm64:$imm)
6682 // (CMPLW CR0, gprc:$rA, gprc:$rB)
6692 // (CMPLWI CR0, gprc:$rA, u16imm:$imm)
6704 // (CMPW CR0, gprc:$rA, gprc:$rB)
6714 // (CMPWI CR0, gprc:$rA, s16imm:$imm)
6725 // (CNTLZW gprc:$rA, gprc:$rS)
6736 // (CNTLZWo gprc:$rA, gprc:$rS)
[all …]
/external/llvm-project/lld/test/ELF/
Dppc32-tls-ie.s40 ## In IE, these instructions (op rT, rA, x@tls) are not changed.
/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/PowerPC/
DPPCGenAsmWriter.inc8344 // (CMPD CR0, g8rc:$rA, g8rc:$rB) - 386
8348 // (CMPDI CR0, g8rc:$rA, s16imm64:$imm) - 389
8351 // (CMPLD CR0, g8rc:$rA, g8rc:$rB) - 391
8355 // (CMPLDI CR0, g8rc:$rA, u16imm64:$imm) - 394
8358 // (CMPLW CR0, gprc:$rA, gprc:$rB) - 396
8362 // (CMPLWI CR0, gprc:$rA, u16imm:$imm) - 399
8365 // (CMPW CR0, gprc:$rA, gprc:$rB) - 401
8369 // (CMPWI CR0, gprc:$rA, s16imm:$imm) - 404
8372 // (CNTLZW gprc:$rA, gprc:$rS) - 406
8375 // (CNTLZW_rec gprc:$rA, gprc:$rS) - 408
[all …]
/external/ImageMagick/PerlMagick/t/reference/filter/
DChannel.miff12 …������K=O����������’�~{|{zpkihhkiaYmvG.1762-691,@z^QV\bQggggfilmmjd�������rA�����ެ���ѵ��~~||zvjhf…
/external/llvm-project/llvm/test/Verifier/
Dvp-intrinsics.ll14 %rA = call <8 x i32> @llvm.vp.ashr.v8i32(<8 x i32> %i0, <8 x i32> %i1, <8 x i1> %m, i32 %n)

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