1//===- PPCInstrVSX.td - The PowerPC VSX Extension --*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the VSX extension to the PowerPC instruction set. 11// 12//===----------------------------------------------------------------------===// 13 14// *********************************** NOTE *********************************** 15// ** For POWER8 Little Endian, the VSX swap optimization relies on knowing ** 16// ** which VMX and VSX instructions are lane-sensitive and which are not. ** 17// ** A lane-sensitive instruction relies, implicitly or explicitly, on ** 18// ** whether lanes are numbered from left to right. An instruction like ** 19// ** VADDFP is not lane-sensitive, because each lane of the result vector ** 20// ** relies only on the corresponding lane of the source vectors. However, ** 21// ** an instruction like VMULESB is lane-sensitive, because "even" and ** 22// ** "odd" lanes are different for big-endian and little-endian numbering. ** 23// ** ** 24// ** When adding new VMX and VSX instructions, please consider whether they ** 25// ** are lane-sensitive. If so, they must be added to a switch statement ** 26// ** in PPCVSXSwapRemoval::gatherVectorInstructions(). ** 27// **************************************************************************** 28 29def PPCRegVSRCAsmOperand : AsmOperandClass { 30 let Name = "RegVSRC"; let PredicateMethod = "isVSRegNumber"; 31} 32def vsrc : RegisterOperand<VSRC> { 33 let ParserMatchClass = PPCRegVSRCAsmOperand; 34} 35 36def PPCRegVSFRCAsmOperand : AsmOperandClass { 37 let Name = "RegVSFRC"; let PredicateMethod = "isVSRegNumber"; 38} 39def vsfrc : RegisterOperand<VSFRC> { 40 let ParserMatchClass = PPCRegVSFRCAsmOperand; 41} 42 43def PPCRegVSSRCAsmOperand : AsmOperandClass { 44 let Name = "RegVSSRC"; let PredicateMethod = "isVSRegNumber"; 45} 46def vssrc : RegisterOperand<VSSRC> { 47 let ParserMatchClass = PPCRegVSSRCAsmOperand; 48} 49 50// Little-endian-specific nodes. 51def SDT_PPClxvd2x : SDTypeProfile<1, 1, [ 52 SDTCisVT<0, v2f64>, SDTCisPtrTy<1> 53]>; 54def SDT_PPCstxvd2x : SDTypeProfile<0, 2, [ 55 SDTCisVT<0, v2f64>, SDTCisPtrTy<1> 56]>; 57def SDT_PPCxxswapd : SDTypeProfile<1, 1, [ 58 SDTCisSameAs<0, 1> 59]>; 60def SDTVecConv : SDTypeProfile<1, 2, [ 61 SDTCisVec<0>, SDTCisVec<1>, SDTCisPtrTy<2> 62]>; 63 64def PPClxvd2x : SDNode<"PPCISD::LXVD2X", SDT_PPClxvd2x, 65 [SDNPHasChain, SDNPMayLoad]>; 66def PPCstxvd2x : SDNode<"PPCISD::STXVD2X", SDT_PPCstxvd2x, 67 [SDNPHasChain, SDNPMayStore]>; 68def PPCxxswapd : SDNode<"PPCISD::XXSWAPD", SDT_PPCxxswapd, [SDNPHasChain]>; 69def PPCmfvsr : SDNode<"PPCISD::MFVSR", SDTUnaryOp, []>; 70def PPCmtvsra : SDNode<"PPCISD::MTVSRA", SDTUnaryOp, []>; 71def PPCmtvsrz : SDNode<"PPCISD::MTVSRZ", SDTUnaryOp, []>; 72def PPCsvec2fp : SDNode<"PPCISD::SINT_VEC_TO_FP", SDTVecConv, []>; 73def PPCuvec2fp: SDNode<"PPCISD::UINT_VEC_TO_FP", SDTVecConv, []>; 74def PPCswapNoChain : SDNode<"PPCISD::SWAP_NO_CHAIN", SDT_PPCxxswapd>; 75 76multiclass XX3Form_Rcr<bits<6> opcode, bits<7> xo, string asmbase, 77 string asmstr, InstrItinClass itin, Intrinsic Int, 78 ValueType OutTy, ValueType InTy> { 79 let BaseName = asmbase in { 80 def NAME : XX3Form_Rc<opcode, xo, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB), 81 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 82 [(set OutTy:$XT, (Int InTy:$XA, InTy:$XB))]>; 83 let Defs = [CR6] in 84 def o : XX3Form_Rc<opcode, xo, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB), 85 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 86 [(set InTy:$XT, 87 (InTy (PPCvcmp_o InTy:$XA, InTy:$XB, xo)))]>, 88 isDOT; 89 } 90} 91 92def HasVSX : Predicate<"PPCSubTarget->hasVSX()">; 93def IsLittleEndian : Predicate<"PPCSubTarget->isLittleEndian()">; 94def IsBigEndian : Predicate<"!PPCSubTarget->isLittleEndian()">; 95 96let Predicates = [HasVSX] in { 97let AddedComplexity = 400 in { // Prefer VSX patterns over non-VSX patterns. 98let hasSideEffects = 0 in { // VSX instructions don't have side effects. 99let Uses = [RM] in { 100 101 // Load indexed instructions 102 let mayLoad = 1 in { 103 def LXSDX : XX1Form<31, 588, 104 (outs vsfrc:$XT), (ins memrr:$src), 105 "lxsdx $XT, $src", IIC_LdStLFD, 106 [(set f64:$XT, (load xoaddr:$src))]>; 107 108 def LXVD2X : XX1Form<31, 844, 109 (outs vsrc:$XT), (ins memrr:$src), 110 "lxvd2x $XT, $src", IIC_LdStLFD, 111 [(set v2f64:$XT, (int_ppc_vsx_lxvd2x xoaddr:$src))]>; 112 113 def LXVDSX : XX1Form<31, 332, 114 (outs vsrc:$XT), (ins memrr:$src), 115 "lxvdsx $XT, $src", IIC_LdStLFD, []>; 116 117 def LXVW4X : XX1Form<31, 780, 118 (outs vsrc:$XT), (ins memrr:$src), 119 "lxvw4x $XT, $src", IIC_LdStLFD, 120 [(set v4i32:$XT, (int_ppc_vsx_lxvw4x xoaddr:$src))]>; 121 } // mayLoad 122 123 // Store indexed instructions 124 let mayStore = 1 in { 125 def STXSDX : XX1Form<31, 716, 126 (outs), (ins vsfrc:$XT, memrr:$dst), 127 "stxsdx $XT, $dst", IIC_LdStSTFD, 128 [(store f64:$XT, xoaddr:$dst)]>; 129 130 def STXVD2X : XX1Form<31, 972, 131 (outs), (ins vsrc:$XT, memrr:$dst), 132 "stxvd2x $XT, $dst", IIC_LdStSTFD, 133 [(store v2f64:$XT, xoaddr:$dst)]>; 134 135 def STXVW4X : XX1Form<31, 908, 136 (outs), (ins vsrc:$XT, memrr:$dst), 137 "stxvw4x $XT, $dst", IIC_LdStSTFD, 138 [(store v4i32:$XT, xoaddr:$dst)]>; 139 140 } // mayStore 141 142 // Add/Mul Instructions 143 let isCommutable = 1 in { 144 def XSADDDP : XX3Form<60, 32, 145 (outs vsfrc:$XT), (ins vsfrc:$XA, vsfrc:$XB), 146 "xsadddp $XT, $XA, $XB", IIC_VecFP, 147 [(set f64:$XT, (fadd f64:$XA, f64:$XB))]>; 148 def XSMULDP : XX3Form<60, 48, 149 (outs vsfrc:$XT), (ins vsfrc:$XA, vsfrc:$XB), 150 "xsmuldp $XT, $XA, $XB", IIC_VecFP, 151 [(set f64:$XT, (fmul f64:$XA, f64:$XB))]>; 152 153 def XVADDDP : XX3Form<60, 96, 154 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB), 155 "xvadddp $XT, $XA, $XB", IIC_VecFP, 156 [(set v2f64:$XT, (fadd v2f64:$XA, v2f64:$XB))]>; 157 158 def XVADDSP : XX3Form<60, 64, 159 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB), 160 "xvaddsp $XT, $XA, $XB", IIC_VecFP, 161 [(set v4f32:$XT, (fadd v4f32:$XA, v4f32:$XB))]>; 162 163 def XVMULDP : XX3Form<60, 112, 164 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB), 165 "xvmuldp $XT, $XA, $XB", IIC_VecFP, 166 [(set v2f64:$XT, (fmul v2f64:$XA, v2f64:$XB))]>; 167 168 def XVMULSP : XX3Form<60, 80, 169 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB), 170 "xvmulsp $XT, $XA, $XB", IIC_VecFP, 171 [(set v4f32:$XT, (fmul v4f32:$XA, v4f32:$XB))]>; 172 } 173 174 // Subtract Instructions 175 def XSSUBDP : XX3Form<60, 40, 176 (outs vsfrc:$XT), (ins vsfrc:$XA, vsfrc:$XB), 177 "xssubdp $XT, $XA, $XB", IIC_VecFP, 178 [(set f64:$XT, (fsub f64:$XA, f64:$XB))]>; 179 180 def XVSUBDP : XX3Form<60, 104, 181 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB), 182 "xvsubdp $XT, $XA, $XB", IIC_VecFP, 183 [(set v2f64:$XT, (fsub v2f64:$XA, v2f64:$XB))]>; 184 def XVSUBSP : XX3Form<60, 72, 185 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB), 186 "xvsubsp $XT, $XA, $XB", IIC_VecFP, 187 [(set v4f32:$XT, (fsub v4f32:$XA, v4f32:$XB))]>; 188 189 // FMA Instructions 190 let BaseName = "XSMADDADP" in { 191 let isCommutable = 1 in 192 def XSMADDADP : XX3Form<60, 33, 193 (outs vsfrc:$XT), (ins vsfrc:$XTi, vsfrc:$XA, vsfrc:$XB), 194 "xsmaddadp $XT, $XA, $XB", IIC_VecFP, 195 [(set f64:$XT, (fma f64:$XA, f64:$XB, f64:$XTi))]>, 196 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">, 197 AltVSXFMARel; 198 let IsVSXFMAAlt = 1 in 199 def XSMADDMDP : XX3Form<60, 41, 200 (outs vsfrc:$XT), (ins vsfrc:$XTi, vsfrc:$XA, vsfrc:$XB), 201 "xsmaddmdp $XT, $XA, $XB", IIC_VecFP, []>, 202 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">, 203 AltVSXFMARel; 204 } 205 206 let BaseName = "XSMSUBADP" in { 207 let isCommutable = 1 in 208 def XSMSUBADP : XX3Form<60, 49, 209 (outs vsfrc:$XT), (ins vsfrc:$XTi, vsfrc:$XA, vsfrc:$XB), 210 "xsmsubadp $XT, $XA, $XB", IIC_VecFP, 211 [(set f64:$XT, (fma f64:$XA, f64:$XB, (fneg f64:$XTi)))]>, 212 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">, 213 AltVSXFMARel; 214 let IsVSXFMAAlt = 1 in 215 def XSMSUBMDP : XX3Form<60, 57, 216 (outs vsfrc:$XT), (ins vsfrc:$XTi, vsfrc:$XA, vsfrc:$XB), 217 "xsmsubmdp $XT, $XA, $XB", IIC_VecFP, []>, 218 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">, 219 AltVSXFMARel; 220 } 221 222 let BaseName = "XSNMADDADP" in { 223 let isCommutable = 1 in 224 def XSNMADDADP : XX3Form<60, 161, 225 (outs vsfrc:$XT), (ins vsfrc:$XTi, vsfrc:$XA, vsfrc:$XB), 226 "xsnmaddadp $XT, $XA, $XB", IIC_VecFP, 227 [(set f64:$XT, (fneg (fma f64:$XA, f64:$XB, f64:$XTi)))]>, 228 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">, 229 AltVSXFMARel; 230 let IsVSXFMAAlt = 1 in 231 def XSNMADDMDP : XX3Form<60, 169, 232 (outs vsfrc:$XT), (ins vsfrc:$XTi, vsfrc:$XA, vsfrc:$XB), 233 "xsnmaddmdp $XT, $XA, $XB", IIC_VecFP, []>, 234 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">, 235 AltVSXFMARel; 236 } 237 238 let BaseName = "XSNMSUBADP" in { 239 let isCommutable = 1 in 240 def XSNMSUBADP : XX3Form<60, 177, 241 (outs vsfrc:$XT), (ins vsfrc:$XTi, vsfrc:$XA, vsfrc:$XB), 242 "xsnmsubadp $XT, $XA, $XB", IIC_VecFP, 243 [(set f64:$XT, (fneg (fma f64:$XA, f64:$XB, (fneg f64:$XTi))))]>, 244 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">, 245 AltVSXFMARel; 246 let IsVSXFMAAlt = 1 in 247 def XSNMSUBMDP : XX3Form<60, 185, 248 (outs vsfrc:$XT), (ins vsfrc:$XTi, vsfrc:$XA, vsfrc:$XB), 249 "xsnmsubmdp $XT, $XA, $XB", IIC_VecFP, []>, 250 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">, 251 AltVSXFMARel; 252 } 253 254 let BaseName = "XVMADDADP" in { 255 let isCommutable = 1 in 256 def XVMADDADP : XX3Form<60, 97, 257 (outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB), 258 "xvmaddadp $XT, $XA, $XB", IIC_VecFP, 259 [(set v2f64:$XT, (fma v2f64:$XA, v2f64:$XB, v2f64:$XTi))]>, 260 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">, 261 AltVSXFMARel; 262 let IsVSXFMAAlt = 1 in 263 def XVMADDMDP : XX3Form<60, 105, 264 (outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB), 265 "xvmaddmdp $XT, $XA, $XB", IIC_VecFP, []>, 266 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">, 267 AltVSXFMARel; 268 } 269 270 let BaseName = "XVMADDASP" in { 271 let isCommutable = 1 in 272 def XVMADDASP : XX3Form<60, 65, 273 (outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB), 274 "xvmaddasp $XT, $XA, $XB", IIC_VecFP, 275 [(set v4f32:$XT, (fma v4f32:$XA, v4f32:$XB, v4f32:$XTi))]>, 276 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">, 277 AltVSXFMARel; 278 let IsVSXFMAAlt = 1 in 279 def XVMADDMSP : XX3Form<60, 73, 280 (outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB), 281 "xvmaddmsp $XT, $XA, $XB", IIC_VecFP, []>, 282 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">, 283 AltVSXFMARel; 284 } 285 286 let BaseName = "XVMSUBADP" in { 287 let isCommutable = 1 in 288 def XVMSUBADP : XX3Form<60, 113, 289 (outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB), 290 "xvmsubadp $XT, $XA, $XB", IIC_VecFP, 291 [(set v2f64:$XT, (fma v2f64:$XA, v2f64:$XB, (fneg v2f64:$XTi)))]>, 292 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">, 293 AltVSXFMARel; 294 let IsVSXFMAAlt = 1 in 295 def XVMSUBMDP : XX3Form<60, 121, 296 (outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB), 297 "xvmsubmdp $XT, $XA, $XB", IIC_VecFP, []>, 298 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">, 299 AltVSXFMARel; 300 } 301 302 let BaseName = "XVMSUBASP" in { 303 let isCommutable = 1 in 304 def XVMSUBASP : XX3Form<60, 81, 305 (outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB), 306 "xvmsubasp $XT, $XA, $XB", IIC_VecFP, 307 [(set v4f32:$XT, (fma v4f32:$XA, v4f32:$XB, (fneg v4f32:$XTi)))]>, 308 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">, 309 AltVSXFMARel; 310 let IsVSXFMAAlt = 1 in 311 def XVMSUBMSP : XX3Form<60, 89, 312 (outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB), 313 "xvmsubmsp $XT, $XA, $XB", IIC_VecFP, []>, 314 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">, 315 AltVSXFMARel; 316 } 317 318 let BaseName = "XVNMADDADP" in { 319 let isCommutable = 1 in 320 def XVNMADDADP : XX3Form<60, 225, 321 (outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB), 322 "xvnmaddadp $XT, $XA, $XB", IIC_VecFP, 323 [(set v2f64:$XT, (fneg (fma v2f64:$XA, v2f64:$XB, v2f64:$XTi)))]>, 324 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">, 325 AltVSXFMARel; 326 let IsVSXFMAAlt = 1 in 327 def XVNMADDMDP : XX3Form<60, 233, 328 (outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB), 329 "xvnmaddmdp $XT, $XA, $XB", IIC_VecFP, []>, 330 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">, 331 AltVSXFMARel; 332 } 333 334 let BaseName = "XVNMADDASP" in { 335 let isCommutable = 1 in 336 def XVNMADDASP : XX3Form<60, 193, 337 (outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB), 338 "xvnmaddasp $XT, $XA, $XB", IIC_VecFP, 339 [(set v4f32:$XT, (fneg (fma v4f32:$XA, v4f32:$XB, v4f32:$XTi)))]>, 340 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">, 341 AltVSXFMARel; 342 let IsVSXFMAAlt = 1 in 343 def XVNMADDMSP : XX3Form<60, 201, 344 (outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB), 345 "xvnmaddmsp $XT, $XA, $XB", IIC_VecFP, []>, 346 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">, 347 AltVSXFMARel; 348 } 349 350 let BaseName = "XVNMSUBADP" in { 351 let isCommutable = 1 in 352 def XVNMSUBADP : XX3Form<60, 241, 353 (outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB), 354 "xvnmsubadp $XT, $XA, $XB", IIC_VecFP, 355 [(set v2f64:$XT, (fneg (fma v2f64:$XA, v2f64:$XB, (fneg v2f64:$XTi))))]>, 356 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">, 357 AltVSXFMARel; 358 let IsVSXFMAAlt = 1 in 359 def XVNMSUBMDP : XX3Form<60, 249, 360 (outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB), 361 "xvnmsubmdp $XT, $XA, $XB", IIC_VecFP, []>, 362 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">, 363 AltVSXFMARel; 364 } 365 366 let BaseName = "XVNMSUBASP" in { 367 let isCommutable = 1 in 368 def XVNMSUBASP : XX3Form<60, 209, 369 (outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB), 370 "xvnmsubasp $XT, $XA, $XB", IIC_VecFP, 371 [(set v4f32:$XT, (fneg (fma v4f32:$XA, v4f32:$XB, (fneg v4f32:$XTi))))]>, 372 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">, 373 AltVSXFMARel; 374 let IsVSXFMAAlt = 1 in 375 def XVNMSUBMSP : XX3Form<60, 217, 376 (outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB), 377 "xvnmsubmsp $XT, $XA, $XB", IIC_VecFP, []>, 378 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">, 379 AltVSXFMARel; 380 } 381 382 // Division Instructions 383 def XSDIVDP : XX3Form<60, 56, 384 (outs vsfrc:$XT), (ins vsfrc:$XA, vsfrc:$XB), 385 "xsdivdp $XT, $XA, $XB", IIC_FPDivD, 386 [(set f64:$XT, (fdiv f64:$XA, f64:$XB))]>; 387 def XSSQRTDP : XX2Form<60, 75, 388 (outs vsfrc:$XT), (ins vsfrc:$XB), 389 "xssqrtdp $XT, $XB", IIC_FPSqrtD, 390 [(set f64:$XT, (fsqrt f64:$XB))]>; 391 392 def XSREDP : XX2Form<60, 90, 393 (outs vsfrc:$XT), (ins vsfrc:$XB), 394 "xsredp $XT, $XB", IIC_VecFP, 395 [(set f64:$XT, (PPCfre f64:$XB))]>; 396 def XSRSQRTEDP : XX2Form<60, 74, 397 (outs vsfrc:$XT), (ins vsfrc:$XB), 398 "xsrsqrtedp $XT, $XB", IIC_VecFP, 399 [(set f64:$XT, (PPCfrsqrte f64:$XB))]>; 400 401 def XSTDIVDP : XX3Form_1<60, 61, 402 (outs crrc:$crD), (ins vsfrc:$XA, vsfrc:$XB), 403 "xstdivdp $crD, $XA, $XB", IIC_FPCompare, []>; 404 def XSTSQRTDP : XX2Form_1<60, 106, 405 (outs crrc:$crD), (ins vsfrc:$XB), 406 "xstsqrtdp $crD, $XB", IIC_FPCompare, []>; 407 408 def XVDIVDP : XX3Form<60, 120, 409 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB), 410 "xvdivdp $XT, $XA, $XB", IIC_FPDivD, 411 [(set v2f64:$XT, (fdiv v2f64:$XA, v2f64:$XB))]>; 412 def XVDIVSP : XX3Form<60, 88, 413 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB), 414 "xvdivsp $XT, $XA, $XB", IIC_FPDivS, 415 [(set v4f32:$XT, (fdiv v4f32:$XA, v4f32:$XB))]>; 416 417 def XVSQRTDP : XX2Form<60, 203, 418 (outs vsrc:$XT), (ins vsrc:$XB), 419 "xvsqrtdp $XT, $XB", IIC_FPSqrtD, 420 [(set v2f64:$XT, (fsqrt v2f64:$XB))]>; 421 def XVSQRTSP : XX2Form<60, 139, 422 (outs vsrc:$XT), (ins vsrc:$XB), 423 "xvsqrtsp $XT, $XB", IIC_FPSqrtS, 424 [(set v4f32:$XT, (fsqrt v4f32:$XB))]>; 425 426 def XVTDIVDP : XX3Form_1<60, 125, 427 (outs crrc:$crD), (ins vsrc:$XA, vsrc:$XB), 428 "xvtdivdp $crD, $XA, $XB", IIC_FPCompare, []>; 429 def XVTDIVSP : XX3Form_1<60, 93, 430 (outs crrc:$crD), (ins vsrc:$XA, vsrc:$XB), 431 "xvtdivsp $crD, $XA, $XB", IIC_FPCompare, []>; 432 433 def XVTSQRTDP : XX2Form_1<60, 234, 434 (outs crrc:$crD), (ins vsrc:$XB), 435 "xvtsqrtdp $crD, $XB", IIC_FPCompare, []>; 436 def XVTSQRTSP : XX2Form_1<60, 170, 437 (outs crrc:$crD), (ins vsrc:$XB), 438 "xvtsqrtsp $crD, $XB", IIC_FPCompare, []>; 439 440 def XVREDP : XX2Form<60, 218, 441 (outs vsrc:$XT), (ins vsrc:$XB), 442 "xvredp $XT, $XB", IIC_VecFP, 443 [(set v2f64:$XT, (PPCfre v2f64:$XB))]>; 444 def XVRESP : XX2Form<60, 154, 445 (outs vsrc:$XT), (ins vsrc:$XB), 446 "xvresp $XT, $XB", IIC_VecFP, 447 [(set v4f32:$XT, (PPCfre v4f32:$XB))]>; 448 449 def XVRSQRTEDP : XX2Form<60, 202, 450 (outs vsrc:$XT), (ins vsrc:$XB), 451 "xvrsqrtedp $XT, $XB", IIC_VecFP, 452 [(set v2f64:$XT, (PPCfrsqrte v2f64:$XB))]>; 453 def XVRSQRTESP : XX2Form<60, 138, 454 (outs vsrc:$XT), (ins vsrc:$XB), 455 "xvrsqrtesp $XT, $XB", IIC_VecFP, 456 [(set v4f32:$XT, (PPCfrsqrte v4f32:$XB))]>; 457 458 // Compare Instructions 459 def XSCMPODP : XX3Form_1<60, 43, 460 (outs crrc:$crD), (ins vsfrc:$XA, vsfrc:$XB), 461 "xscmpodp $crD, $XA, $XB", IIC_FPCompare, []>; 462 def XSCMPUDP : XX3Form_1<60, 35, 463 (outs crrc:$crD), (ins vsfrc:$XA, vsfrc:$XB), 464 "xscmpudp $crD, $XA, $XB", IIC_FPCompare, []>; 465 466 defm XVCMPEQDP : XX3Form_Rcr<60, 99, 467 "xvcmpeqdp", "$XT, $XA, $XB", IIC_VecFPCompare, 468 int_ppc_vsx_xvcmpeqdp, v2i64, v2f64>; 469 defm XVCMPEQSP : XX3Form_Rcr<60, 67, 470 "xvcmpeqsp", "$XT, $XA, $XB", IIC_VecFPCompare, 471 int_ppc_vsx_xvcmpeqsp, v4i32, v4f32>; 472 defm XVCMPGEDP : XX3Form_Rcr<60, 115, 473 "xvcmpgedp", "$XT, $XA, $XB", IIC_VecFPCompare, 474 int_ppc_vsx_xvcmpgedp, v2i64, v2f64>; 475 defm XVCMPGESP : XX3Form_Rcr<60, 83, 476 "xvcmpgesp", "$XT, $XA, $XB", IIC_VecFPCompare, 477 int_ppc_vsx_xvcmpgesp, v4i32, v4f32>; 478 defm XVCMPGTDP : XX3Form_Rcr<60, 107, 479 "xvcmpgtdp", "$XT, $XA, $XB", IIC_VecFPCompare, 480 int_ppc_vsx_xvcmpgtdp, v2i64, v2f64>; 481 defm XVCMPGTSP : XX3Form_Rcr<60, 75, 482 "xvcmpgtsp", "$XT, $XA, $XB", IIC_VecFPCompare, 483 int_ppc_vsx_xvcmpgtsp, v4i32, v4f32>; 484 485 // Move Instructions 486 def XSABSDP : XX2Form<60, 345, 487 (outs vsfrc:$XT), (ins vsfrc:$XB), 488 "xsabsdp $XT, $XB", IIC_VecFP, 489 [(set f64:$XT, (fabs f64:$XB))]>; 490 def XSNABSDP : XX2Form<60, 361, 491 (outs vsfrc:$XT), (ins vsfrc:$XB), 492 "xsnabsdp $XT, $XB", IIC_VecFP, 493 [(set f64:$XT, (fneg (fabs f64:$XB)))]>; 494 def XSNEGDP : XX2Form<60, 377, 495 (outs vsfrc:$XT), (ins vsfrc:$XB), 496 "xsnegdp $XT, $XB", IIC_VecFP, 497 [(set f64:$XT, (fneg f64:$XB))]>; 498 def XSCPSGNDP : XX3Form<60, 176, 499 (outs vsfrc:$XT), (ins vsfrc:$XA, vsfrc:$XB), 500 "xscpsgndp $XT, $XA, $XB", IIC_VecFP, 501 [(set f64:$XT, (fcopysign f64:$XB, f64:$XA))]>; 502 503 def XVABSDP : XX2Form<60, 473, 504 (outs vsrc:$XT), (ins vsrc:$XB), 505 "xvabsdp $XT, $XB", IIC_VecFP, 506 [(set v2f64:$XT, (fabs v2f64:$XB))]>; 507 508 def XVABSSP : XX2Form<60, 409, 509 (outs vsrc:$XT), (ins vsrc:$XB), 510 "xvabssp $XT, $XB", IIC_VecFP, 511 [(set v4f32:$XT, (fabs v4f32:$XB))]>; 512 513 def XVCPSGNDP : XX3Form<60, 240, 514 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB), 515 "xvcpsgndp $XT, $XA, $XB", IIC_VecFP, 516 [(set v2f64:$XT, (fcopysign v2f64:$XB, v2f64:$XA))]>; 517 def XVCPSGNSP : XX3Form<60, 208, 518 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB), 519 "xvcpsgnsp $XT, $XA, $XB", IIC_VecFP, 520 [(set v4f32:$XT, (fcopysign v4f32:$XB, v4f32:$XA))]>; 521 522 def XVNABSDP : XX2Form<60, 489, 523 (outs vsrc:$XT), (ins vsrc:$XB), 524 "xvnabsdp $XT, $XB", IIC_VecFP, 525 [(set v2f64:$XT, (fneg (fabs v2f64:$XB)))]>; 526 def XVNABSSP : XX2Form<60, 425, 527 (outs vsrc:$XT), (ins vsrc:$XB), 528 "xvnabssp $XT, $XB", IIC_VecFP, 529 [(set v4f32:$XT, (fneg (fabs v4f32:$XB)))]>; 530 531 def XVNEGDP : XX2Form<60, 505, 532 (outs vsrc:$XT), (ins vsrc:$XB), 533 "xvnegdp $XT, $XB", IIC_VecFP, 534 [(set v2f64:$XT, (fneg v2f64:$XB))]>; 535 def XVNEGSP : XX2Form<60, 441, 536 (outs vsrc:$XT), (ins vsrc:$XB), 537 "xvnegsp $XT, $XB", IIC_VecFP, 538 [(set v4f32:$XT, (fneg v4f32:$XB))]>; 539 540 // Conversion Instructions 541 def XSCVDPSP : XX2Form<60, 265, 542 (outs vsfrc:$XT), (ins vsfrc:$XB), 543 "xscvdpsp $XT, $XB", IIC_VecFP, []>; 544 def XSCVDPSXDS : XX2Form<60, 344, 545 (outs vsfrc:$XT), (ins vsfrc:$XB), 546 "xscvdpsxds $XT, $XB", IIC_VecFP, 547 [(set f64:$XT, (PPCfctidz f64:$XB))]>; 548 def XSCVDPSXWS : XX2Form<60, 88, 549 (outs vsfrc:$XT), (ins vsfrc:$XB), 550 "xscvdpsxws $XT, $XB", IIC_VecFP, 551 [(set f64:$XT, (PPCfctiwz f64:$XB))]>; 552 def XSCVDPUXDS : XX2Form<60, 328, 553 (outs vsfrc:$XT), (ins vsfrc:$XB), 554 "xscvdpuxds $XT, $XB", IIC_VecFP, 555 [(set f64:$XT, (PPCfctiduz f64:$XB))]>; 556 def XSCVDPUXWS : XX2Form<60, 72, 557 (outs vsfrc:$XT), (ins vsfrc:$XB), 558 "xscvdpuxws $XT, $XB", IIC_VecFP, 559 [(set f64:$XT, (PPCfctiwuz f64:$XB))]>; 560 def XSCVSPDP : XX2Form<60, 329, 561 (outs vsfrc:$XT), (ins vsfrc:$XB), 562 "xscvspdp $XT, $XB", IIC_VecFP, []>; 563 def XSCVSXDDP : XX2Form<60, 376, 564 (outs vsfrc:$XT), (ins vsfrc:$XB), 565 "xscvsxddp $XT, $XB", IIC_VecFP, 566 [(set f64:$XT, (PPCfcfid f64:$XB))]>; 567 def XSCVUXDDP : XX2Form<60, 360, 568 (outs vsfrc:$XT), (ins vsfrc:$XB), 569 "xscvuxddp $XT, $XB", IIC_VecFP, 570 [(set f64:$XT, (PPCfcfidu f64:$XB))]>; 571 572 def XVCVDPSP : XX2Form<60, 393, 573 (outs vsrc:$XT), (ins vsrc:$XB), 574 "xvcvdpsp $XT, $XB", IIC_VecFP, []>; 575 def XVCVDPSXDS : XX2Form<60, 472, 576 (outs vsrc:$XT), (ins vsrc:$XB), 577 "xvcvdpsxds $XT, $XB", IIC_VecFP, 578 [(set v2i64:$XT, (fp_to_sint v2f64:$XB))]>; 579 def XVCVDPSXWS : XX2Form<60, 216, 580 (outs vsrc:$XT), (ins vsrc:$XB), 581 "xvcvdpsxws $XT, $XB", IIC_VecFP, []>; 582 def XVCVDPUXDS : XX2Form<60, 456, 583 (outs vsrc:$XT), (ins vsrc:$XB), 584 "xvcvdpuxds $XT, $XB", IIC_VecFP, 585 [(set v2i64:$XT, (fp_to_uint v2f64:$XB))]>; 586 def XVCVDPUXWS : XX2Form<60, 200, 587 (outs vsrc:$XT), (ins vsrc:$XB), 588 "xvcvdpuxws $XT, $XB", IIC_VecFP, []>; 589 590 def XVCVSPDP : XX2Form<60, 457, 591 (outs vsrc:$XT), (ins vsrc:$XB), 592 "xvcvspdp $XT, $XB", IIC_VecFP, []>; 593 def XVCVSPSXDS : XX2Form<60, 408, 594 (outs vsrc:$XT), (ins vsrc:$XB), 595 "xvcvspsxds $XT, $XB", IIC_VecFP, []>; 596 def XVCVSPSXWS : XX2Form<60, 152, 597 (outs vsrc:$XT), (ins vsrc:$XB), 598 "xvcvspsxws $XT, $XB", IIC_VecFP, []>; 599 def XVCVSPUXDS : XX2Form<60, 392, 600 (outs vsrc:$XT), (ins vsrc:$XB), 601 "xvcvspuxds $XT, $XB", IIC_VecFP, []>; 602 def XVCVSPUXWS : XX2Form<60, 136, 603 (outs vsrc:$XT), (ins vsrc:$XB), 604 "xvcvspuxws $XT, $XB", IIC_VecFP, []>; 605 def XVCVSXDDP : XX2Form<60, 504, 606 (outs vsrc:$XT), (ins vsrc:$XB), 607 "xvcvsxddp $XT, $XB", IIC_VecFP, 608 [(set v2f64:$XT, (sint_to_fp v2i64:$XB))]>; 609 def XVCVSXDSP : XX2Form<60, 440, 610 (outs vsrc:$XT), (ins vsrc:$XB), 611 "xvcvsxdsp $XT, $XB", IIC_VecFP, []>; 612 def XVCVSXWDP : XX2Form<60, 248, 613 (outs vsrc:$XT), (ins vsrc:$XB), 614 "xvcvsxwdp $XT, $XB", IIC_VecFP, []>; 615 def XVCVSXWSP : XX2Form<60, 184, 616 (outs vsrc:$XT), (ins vsrc:$XB), 617 "xvcvsxwsp $XT, $XB", IIC_VecFP, 618 [(set v4f32:$XT, (sint_to_fp v4i32:$XB))]>; 619 def XVCVUXDDP : XX2Form<60, 488, 620 (outs vsrc:$XT), (ins vsrc:$XB), 621 "xvcvuxddp $XT, $XB", IIC_VecFP, 622 [(set v2f64:$XT, (uint_to_fp v2i64:$XB))]>; 623 def XVCVUXDSP : XX2Form<60, 424, 624 (outs vsrc:$XT), (ins vsrc:$XB), 625 "xvcvuxdsp $XT, $XB", IIC_VecFP, []>; 626 def XVCVUXWDP : XX2Form<60, 232, 627 (outs vsrc:$XT), (ins vsrc:$XB), 628 "xvcvuxwdp $XT, $XB", IIC_VecFP, []>; 629 def XVCVUXWSP : XX2Form<60, 168, 630 (outs vsrc:$XT), (ins vsrc:$XB), 631 "xvcvuxwsp $XT, $XB", IIC_VecFP, []>; 632 633 // Rounding Instructions 634 def XSRDPI : XX2Form<60, 73, 635 (outs vsfrc:$XT), (ins vsfrc:$XB), 636 "xsrdpi $XT, $XB", IIC_VecFP, 637 [(set f64:$XT, (frnd f64:$XB))]>; 638 def XSRDPIC : XX2Form<60, 107, 639 (outs vsfrc:$XT), (ins vsfrc:$XB), 640 "xsrdpic $XT, $XB", IIC_VecFP, 641 [(set f64:$XT, (fnearbyint f64:$XB))]>; 642 def XSRDPIM : XX2Form<60, 121, 643 (outs vsfrc:$XT), (ins vsfrc:$XB), 644 "xsrdpim $XT, $XB", IIC_VecFP, 645 [(set f64:$XT, (ffloor f64:$XB))]>; 646 def XSRDPIP : XX2Form<60, 105, 647 (outs vsfrc:$XT), (ins vsfrc:$XB), 648 "xsrdpip $XT, $XB", IIC_VecFP, 649 [(set f64:$XT, (fceil f64:$XB))]>; 650 def XSRDPIZ : XX2Form<60, 89, 651 (outs vsfrc:$XT), (ins vsfrc:$XB), 652 "xsrdpiz $XT, $XB", IIC_VecFP, 653 [(set f64:$XT, (ftrunc f64:$XB))]>; 654 655 def XVRDPI : XX2Form<60, 201, 656 (outs vsrc:$XT), (ins vsrc:$XB), 657 "xvrdpi $XT, $XB", IIC_VecFP, 658 [(set v2f64:$XT, (frnd v2f64:$XB))]>; 659 def XVRDPIC : XX2Form<60, 235, 660 (outs vsrc:$XT), (ins vsrc:$XB), 661 "xvrdpic $XT, $XB", IIC_VecFP, 662 [(set v2f64:$XT, (fnearbyint v2f64:$XB))]>; 663 def XVRDPIM : XX2Form<60, 249, 664 (outs vsrc:$XT), (ins vsrc:$XB), 665 "xvrdpim $XT, $XB", IIC_VecFP, 666 [(set v2f64:$XT, (ffloor v2f64:$XB))]>; 667 def XVRDPIP : XX2Form<60, 233, 668 (outs vsrc:$XT), (ins vsrc:$XB), 669 "xvrdpip $XT, $XB", IIC_VecFP, 670 [(set v2f64:$XT, (fceil v2f64:$XB))]>; 671 def XVRDPIZ : XX2Form<60, 217, 672 (outs vsrc:$XT), (ins vsrc:$XB), 673 "xvrdpiz $XT, $XB", IIC_VecFP, 674 [(set v2f64:$XT, (ftrunc v2f64:$XB))]>; 675 676 def XVRSPI : XX2Form<60, 137, 677 (outs vsrc:$XT), (ins vsrc:$XB), 678 "xvrspi $XT, $XB", IIC_VecFP, 679 [(set v4f32:$XT, (frnd v4f32:$XB))]>; 680 def XVRSPIC : XX2Form<60, 171, 681 (outs vsrc:$XT), (ins vsrc:$XB), 682 "xvrspic $XT, $XB", IIC_VecFP, 683 [(set v4f32:$XT, (fnearbyint v4f32:$XB))]>; 684 def XVRSPIM : XX2Form<60, 185, 685 (outs vsrc:$XT), (ins vsrc:$XB), 686 "xvrspim $XT, $XB", IIC_VecFP, 687 [(set v4f32:$XT, (ffloor v4f32:$XB))]>; 688 def XVRSPIP : XX2Form<60, 169, 689 (outs vsrc:$XT), (ins vsrc:$XB), 690 "xvrspip $XT, $XB", IIC_VecFP, 691 [(set v4f32:$XT, (fceil v4f32:$XB))]>; 692 def XVRSPIZ : XX2Form<60, 153, 693 (outs vsrc:$XT), (ins vsrc:$XB), 694 "xvrspiz $XT, $XB", IIC_VecFP, 695 [(set v4f32:$XT, (ftrunc v4f32:$XB))]>; 696 697 // Max/Min Instructions 698 let isCommutable = 1 in { 699 def XSMAXDP : XX3Form<60, 160, 700 (outs vsfrc:$XT), (ins vsfrc:$XA, vsfrc:$XB), 701 "xsmaxdp $XT, $XA, $XB", IIC_VecFP, 702 [(set vsfrc:$XT, 703 (int_ppc_vsx_xsmaxdp vsfrc:$XA, vsfrc:$XB))]>; 704 def XSMINDP : XX3Form<60, 168, 705 (outs vsfrc:$XT), (ins vsfrc:$XA, vsfrc:$XB), 706 "xsmindp $XT, $XA, $XB", IIC_VecFP, 707 [(set vsfrc:$XT, 708 (int_ppc_vsx_xsmindp vsfrc:$XA, vsfrc:$XB))]>; 709 710 def XVMAXDP : XX3Form<60, 224, 711 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB), 712 "xvmaxdp $XT, $XA, $XB", IIC_VecFP, 713 [(set vsrc:$XT, 714 (int_ppc_vsx_xvmaxdp vsrc:$XA, vsrc:$XB))]>; 715 def XVMINDP : XX3Form<60, 232, 716 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB), 717 "xvmindp $XT, $XA, $XB", IIC_VecFP, 718 [(set vsrc:$XT, 719 (int_ppc_vsx_xvmindp vsrc:$XA, vsrc:$XB))]>; 720 721 def XVMAXSP : XX3Form<60, 192, 722 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB), 723 "xvmaxsp $XT, $XA, $XB", IIC_VecFP, 724 [(set vsrc:$XT, 725 (int_ppc_vsx_xvmaxsp vsrc:$XA, vsrc:$XB))]>; 726 def XVMINSP : XX3Form<60, 200, 727 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB), 728 "xvminsp $XT, $XA, $XB", IIC_VecFP, 729 [(set vsrc:$XT, 730 (int_ppc_vsx_xvminsp vsrc:$XA, vsrc:$XB))]>; 731 } // isCommutable 732} // Uses = [RM] 733 734 // Logical Instructions 735 let isCommutable = 1 in 736 def XXLAND : XX3Form<60, 130, 737 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB), 738 "xxland $XT, $XA, $XB", IIC_VecGeneral, 739 [(set v4i32:$XT, (and v4i32:$XA, v4i32:$XB))]>; 740 def XXLANDC : XX3Form<60, 138, 741 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB), 742 "xxlandc $XT, $XA, $XB", IIC_VecGeneral, 743 [(set v4i32:$XT, (and v4i32:$XA, 744 (vnot_ppc v4i32:$XB)))]>; 745 let isCommutable = 1 in { 746 def XXLNOR : XX3Form<60, 162, 747 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB), 748 "xxlnor $XT, $XA, $XB", IIC_VecGeneral, 749 [(set v4i32:$XT, (vnot_ppc (or v4i32:$XA, 750 v4i32:$XB)))]>; 751 def XXLOR : XX3Form<60, 146, 752 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB), 753 "xxlor $XT, $XA, $XB", IIC_VecGeneral, 754 [(set v4i32:$XT, (or v4i32:$XA, v4i32:$XB))]>; 755 let isCodeGenOnly = 1 in 756 def XXLORf: XX3Form<60, 146, 757 (outs vsfrc:$XT), (ins vsfrc:$XA, vsfrc:$XB), 758 "xxlor $XT, $XA, $XB", IIC_VecGeneral, []>; 759 def XXLXOR : XX3Form<60, 154, 760 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB), 761 "xxlxor $XT, $XA, $XB", IIC_VecGeneral, 762 [(set v4i32:$XT, (xor v4i32:$XA, v4i32:$XB))]>; 763 } // isCommutable 764 765 // Permutation Instructions 766 def XXMRGHW : XX3Form<60, 18, 767 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB), 768 "xxmrghw $XT, $XA, $XB", IIC_VecPerm, []>; 769 def XXMRGLW : XX3Form<60, 50, 770 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB), 771 "xxmrglw $XT, $XA, $XB", IIC_VecPerm, []>; 772 773 def XXPERMDI : XX3Form_2<60, 10, 774 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB, u2imm:$DM), 775 "xxpermdi $XT, $XA, $XB, $DM", IIC_VecPerm, []>; 776 def XXSEL : XX4Form<60, 3, 777 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB, vsrc:$XC), 778 "xxsel $XT, $XA, $XB, $XC", IIC_VecPerm, []>; 779 780 def XXSLDWI : XX3Form_2<60, 2, 781 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB, u2imm:$SHW), 782 "xxsldwi $XT, $XA, $XB, $SHW", IIC_VecPerm, 783 [(set v4i32:$XT, (PPCvecshl v4i32:$XA, v4i32:$XB, 784 imm32SExt16:$SHW))]>; 785 def XXSPLTW : XX2Form_2<60, 164, 786 (outs vsrc:$XT), (ins vsrc:$XB, u2imm:$UIM), 787 "xxspltw $XT, $XB, $UIM", IIC_VecPerm, 788 [(set v4i32:$XT, 789 (PPCxxsplt v4i32:$XB, imm32SExt16:$UIM))]>; 790} // hasSideEffects 791 792// SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded after 793// instruction selection into a branch sequence. 794let usesCustomInserter = 1, // Expanded after instruction selection. 795 PPC970_Single = 1 in { 796 797 def SELECT_CC_VSRC: Pseudo<(outs vsrc:$dst), 798 (ins crrc:$cond, vsrc:$T, vsrc:$F, i32imm:$BROPC), 799 "#SELECT_CC_VSRC", 800 []>; 801 def SELECT_VSRC: Pseudo<(outs vsrc:$dst), 802 (ins crbitrc:$cond, vsrc:$T, vsrc:$F), 803 "#SELECT_VSRC", 804 [(set v2f64:$dst, 805 (select i1:$cond, v2f64:$T, v2f64:$F))]>; 806 def SELECT_CC_VSFRC: Pseudo<(outs f8rc:$dst), 807 (ins crrc:$cond, f8rc:$T, f8rc:$F, 808 i32imm:$BROPC), "#SELECT_CC_VSFRC", 809 []>; 810 def SELECT_VSFRC: Pseudo<(outs f8rc:$dst), 811 (ins crbitrc:$cond, f8rc:$T, f8rc:$F), 812 "#SELECT_VSFRC", 813 [(set f64:$dst, 814 (select i1:$cond, f64:$T, f64:$F))]>; 815 def SELECT_CC_VSSRC: Pseudo<(outs f4rc:$dst), 816 (ins crrc:$cond, f4rc:$T, f4rc:$F, 817 i32imm:$BROPC), "#SELECT_CC_VSSRC", 818 []>; 819 def SELECT_VSSRC: Pseudo<(outs f4rc:$dst), 820 (ins crbitrc:$cond, f4rc:$T, f4rc:$F), 821 "#SELECT_VSSRC", 822 [(set f32:$dst, 823 (select i1:$cond, f32:$T, f32:$F))]>; 824} // usesCustomInserter 825} // AddedComplexity 826 827def : InstAlias<"xvmovdp $XT, $XB", 828 (XVCPSGNDP vsrc:$XT, vsrc:$XB, vsrc:$XB)>; 829def : InstAlias<"xvmovsp $XT, $XB", 830 (XVCPSGNSP vsrc:$XT, vsrc:$XB, vsrc:$XB)>; 831 832def : InstAlias<"xxspltd $XT, $XB, 0", 833 (XXPERMDI vsrc:$XT, vsrc:$XB, vsrc:$XB, 0)>; 834def : InstAlias<"xxspltd $XT, $XB, 1", 835 (XXPERMDI vsrc:$XT, vsrc:$XB, vsrc:$XB, 3)>; 836def : InstAlias<"xxmrghd $XT, $XA, $XB", 837 (XXPERMDI vsrc:$XT, vsrc:$XA, vsrc:$XB, 0)>; 838def : InstAlias<"xxmrgld $XT, $XA, $XB", 839 (XXPERMDI vsrc:$XT, vsrc:$XA, vsrc:$XB, 3)>; 840def : InstAlias<"xxswapd $XT, $XB", 841 (XXPERMDI vsrc:$XT, vsrc:$XB, vsrc:$XB, 2)>; 842 843let AddedComplexity = 400 in { // Prefer VSX patterns over non-VSX patterns. 844 845let Predicates = [IsBigEndian] in { 846def : Pat<(v2f64 (scalar_to_vector f64:$A)), 847 (v2f64 (SUBREG_TO_REG (i64 1), $A, sub_64))>; 848 849def : Pat<(f64 (extractelt v2f64:$S, 0)), 850 (f64 (EXTRACT_SUBREG $S, sub_64))>; 851def : Pat<(f64 (extractelt v2f64:$S, 1)), 852 (f64 (EXTRACT_SUBREG (XXPERMDI $S, $S, 2), sub_64))>; 853} 854 855let Predicates = [IsLittleEndian] in { 856def : Pat<(v2f64 (scalar_to_vector f64:$A)), 857 (v2f64 (XXPERMDI (SUBREG_TO_REG (i64 1), $A, sub_64), 858 (SUBREG_TO_REG (i64 1), $A, sub_64), 0))>; 859 860def : Pat<(f64 (extractelt v2f64:$S, 0)), 861 (f64 (EXTRACT_SUBREG (XXPERMDI $S, $S, 2), sub_64))>; 862def : Pat<(f64 (extractelt v2f64:$S, 1)), 863 (f64 (EXTRACT_SUBREG $S, sub_64))>; 864} 865 866// Additional fnmsub patterns: -a*c + b == -(a*c - b) 867def : Pat<(fma (fneg f64:$A), f64:$C, f64:$B), 868 (XSNMSUBADP $B, $C, $A)>; 869def : Pat<(fma f64:$A, (fneg f64:$C), f64:$B), 870 (XSNMSUBADP $B, $C, $A)>; 871 872def : Pat<(fma (fneg v2f64:$A), v2f64:$C, v2f64:$B), 873 (XVNMSUBADP $B, $C, $A)>; 874def : Pat<(fma v2f64:$A, (fneg v2f64:$C), v2f64:$B), 875 (XVNMSUBADP $B, $C, $A)>; 876 877def : Pat<(fma (fneg v4f32:$A), v4f32:$C, v4f32:$B), 878 (XVNMSUBASP $B, $C, $A)>; 879def : Pat<(fma v4f32:$A, (fneg v4f32:$C), v4f32:$B), 880 (XVNMSUBASP $B, $C, $A)>; 881 882def : Pat<(v2f64 (bitconvert v4f32:$A)), 883 (COPY_TO_REGCLASS $A, VSRC)>; 884def : Pat<(v2f64 (bitconvert v4i32:$A)), 885 (COPY_TO_REGCLASS $A, VSRC)>; 886def : Pat<(v2f64 (bitconvert v8i16:$A)), 887 (COPY_TO_REGCLASS $A, VSRC)>; 888def : Pat<(v2f64 (bitconvert v16i8:$A)), 889 (COPY_TO_REGCLASS $A, VSRC)>; 890 891def : Pat<(v4f32 (bitconvert v2f64:$A)), 892 (COPY_TO_REGCLASS $A, VRRC)>; 893def : Pat<(v4i32 (bitconvert v2f64:$A)), 894 (COPY_TO_REGCLASS $A, VRRC)>; 895def : Pat<(v8i16 (bitconvert v2f64:$A)), 896 (COPY_TO_REGCLASS $A, VRRC)>; 897def : Pat<(v16i8 (bitconvert v2f64:$A)), 898 (COPY_TO_REGCLASS $A, VRRC)>; 899 900def : Pat<(v2i64 (bitconvert v4f32:$A)), 901 (COPY_TO_REGCLASS $A, VSRC)>; 902def : Pat<(v2i64 (bitconvert v4i32:$A)), 903 (COPY_TO_REGCLASS $A, VSRC)>; 904def : Pat<(v2i64 (bitconvert v8i16:$A)), 905 (COPY_TO_REGCLASS $A, VSRC)>; 906def : Pat<(v2i64 (bitconvert v16i8:$A)), 907 (COPY_TO_REGCLASS $A, VSRC)>; 908 909def : Pat<(v4f32 (bitconvert v2i64:$A)), 910 (COPY_TO_REGCLASS $A, VRRC)>; 911def : Pat<(v4i32 (bitconvert v2i64:$A)), 912 (COPY_TO_REGCLASS $A, VRRC)>; 913def : Pat<(v8i16 (bitconvert v2i64:$A)), 914 (COPY_TO_REGCLASS $A, VRRC)>; 915def : Pat<(v16i8 (bitconvert v2i64:$A)), 916 (COPY_TO_REGCLASS $A, VRRC)>; 917 918def : Pat<(v2f64 (bitconvert v2i64:$A)), 919 (COPY_TO_REGCLASS $A, VRRC)>; 920def : Pat<(v2i64 (bitconvert v2f64:$A)), 921 (COPY_TO_REGCLASS $A, VRRC)>; 922 923def : Pat<(v2f64 (bitconvert v1i128:$A)), 924 (COPY_TO_REGCLASS $A, VRRC)>; 925def : Pat<(v1i128 (bitconvert v2f64:$A)), 926 (COPY_TO_REGCLASS $A, VRRC)>; 927 928// sign extension patterns 929// To extend "in place" from v2i32 to v2i64, we have input data like: 930// | undef | i32 | undef | i32 | 931// but xvcvsxwdp expects the input in big-Endian format: 932// | i32 | undef | i32 | undef | 933// so we need to shift everything to the left by one i32 (word) before 934// the conversion. 935def : Pat<(sext_inreg v2i64:$C, v2i32), 936 (XVCVDPSXDS (XVCVSXWDP (XXSLDWI $C, $C, 1)))>; 937def : Pat<(v2f64 (sint_to_fp (sext_inreg v2i64:$C, v2i32))), 938 (XVCVSXWDP (XXSLDWI $C, $C, 1))>; 939 940def : Pat<(v2f64 (PPCsvec2fp v4i32:$C, 0)), 941 (v2f64 (XVCVSXWDP (v2i64 (XXMRGHW $C, $C))))>; 942def : Pat<(v2f64 (PPCsvec2fp v4i32:$C, 1)), 943 (v2f64 (XVCVSXWDP (v2i64 (XXMRGLW $C, $C))))>; 944 945def : Pat<(v2f64 (PPCuvec2fp v4i32:$C, 0)), 946 (v2f64 (XVCVUXWDP (v2i64 (XXMRGHW $C, $C))))>; 947def : Pat<(v2f64 (PPCuvec2fp v4i32:$C, 1)), 948 (v2f64 (XVCVUXWDP (v2i64 (XXMRGLW $C, $C))))>; 949 950// Loads. 951def : Pat<(v2f64 (load xoaddr:$src)), (LXVD2X xoaddr:$src)>; 952def : Pat<(v2i64 (load xoaddr:$src)), (LXVD2X xoaddr:$src)>; 953def : Pat<(v4i32 (load xoaddr:$src)), (LXVW4X xoaddr:$src)>; 954def : Pat<(v2f64 (PPClxvd2x xoaddr:$src)), (LXVD2X xoaddr:$src)>; 955 956// Stores. 957def : Pat<(int_ppc_vsx_stxvd2x v2f64:$rS, xoaddr:$dst), 958 (STXVD2X $rS, xoaddr:$dst)>; 959def : Pat<(store v2i64:$rS, xoaddr:$dst), (STXVD2X $rS, xoaddr:$dst)>; 960def : Pat<(int_ppc_vsx_stxvw4x v4i32:$rS, xoaddr:$dst), 961 (STXVW4X $rS, xoaddr:$dst)>; 962def : Pat<(PPCstxvd2x v2f64:$rS, xoaddr:$dst), (STXVD2X $rS, xoaddr:$dst)>; 963 964// Permutes. 965def : Pat<(v2f64 (PPCxxswapd v2f64:$src)), (XXPERMDI $src, $src, 2)>; 966def : Pat<(v2i64 (PPCxxswapd v2i64:$src)), (XXPERMDI $src, $src, 2)>; 967def : Pat<(v4f32 (PPCxxswapd v4f32:$src)), (XXPERMDI $src, $src, 2)>; 968def : Pat<(v4i32 (PPCxxswapd v4i32:$src)), (XXPERMDI $src, $src, 2)>; 969def : Pat<(v2f64 (PPCswapNoChain v2f64:$src)), (XXPERMDI $src, $src, 2)>; 970 971// Selects. 972def : Pat<(v2f64 (selectcc i1:$lhs, i1:$rhs, v2f64:$tval, v2f64:$fval, SETLT)), 973 (SELECT_VSRC (CRANDC $lhs, $rhs), $tval, $fval)>; 974def : Pat<(v2f64 (selectcc i1:$lhs, i1:$rhs, v2f64:$tval, v2f64:$fval, SETULT)), 975 (SELECT_VSRC (CRANDC $rhs, $lhs), $tval, $fval)>; 976def : Pat<(v2f64 (selectcc i1:$lhs, i1:$rhs, v2f64:$tval, v2f64:$fval, SETLE)), 977 (SELECT_VSRC (CRORC $lhs, $rhs), $tval, $fval)>; 978def : Pat<(v2f64 (selectcc i1:$lhs, i1:$rhs, v2f64:$tval, v2f64:$fval, SETULE)), 979 (SELECT_VSRC (CRORC $rhs, $lhs), $tval, $fval)>; 980def : Pat<(v2f64 (selectcc i1:$lhs, i1:$rhs, v2f64:$tval, v2f64:$fval, SETEQ)), 981 (SELECT_VSRC (CREQV $lhs, $rhs), $tval, $fval)>; 982def : Pat<(v2f64 (selectcc i1:$lhs, i1:$rhs, v2f64:$tval, v2f64:$fval, SETGE)), 983 (SELECT_VSRC (CRORC $rhs, $lhs), $tval, $fval)>; 984def : Pat<(v2f64 (selectcc i1:$lhs, i1:$rhs, v2f64:$tval, v2f64:$fval, SETUGE)), 985 (SELECT_VSRC (CRORC $lhs, $rhs), $tval, $fval)>; 986def : Pat<(v2f64 (selectcc i1:$lhs, i1:$rhs, v2f64:$tval, v2f64:$fval, SETGT)), 987 (SELECT_VSRC (CRANDC $rhs, $lhs), $tval, $fval)>; 988def : Pat<(v2f64 (selectcc i1:$lhs, i1:$rhs, v2f64:$tval, v2f64:$fval, SETUGT)), 989 (SELECT_VSRC (CRANDC $lhs, $rhs), $tval, $fval)>; 990def : Pat<(v2f64 (selectcc i1:$lhs, i1:$rhs, v2f64:$tval, v2f64:$fval, SETNE)), 991 (SELECT_VSRC (CRXOR $lhs, $rhs), $tval, $fval)>; 992 993def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETLT)), 994 (SELECT_VSFRC (CRANDC $lhs, $rhs), $tval, $fval)>; 995def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETULT)), 996 (SELECT_VSFRC (CRANDC $rhs, $lhs), $tval, $fval)>; 997def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETLE)), 998 (SELECT_VSFRC (CRORC $lhs, $rhs), $tval, $fval)>; 999def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETULE)), 1000 (SELECT_VSFRC (CRORC $rhs, $lhs), $tval, $fval)>; 1001def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETEQ)), 1002 (SELECT_VSFRC (CREQV $lhs, $rhs), $tval, $fval)>; 1003def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETGE)), 1004 (SELECT_VSFRC (CRORC $rhs, $lhs), $tval, $fval)>; 1005def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETUGE)), 1006 (SELECT_VSFRC (CRORC $lhs, $rhs), $tval, $fval)>; 1007def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETGT)), 1008 (SELECT_VSFRC (CRANDC $rhs, $lhs), $tval, $fval)>; 1009def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETUGT)), 1010 (SELECT_VSFRC (CRANDC $lhs, $rhs), $tval, $fval)>; 1011def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETNE)), 1012 (SELECT_VSFRC (CRXOR $lhs, $rhs), $tval, $fval)>; 1013 1014// Divides. 1015def : Pat<(int_ppc_vsx_xvdivsp v4f32:$A, v4f32:$B), 1016 (XVDIVSP $A, $B)>; 1017def : Pat<(int_ppc_vsx_xvdivdp v2f64:$A, v2f64:$B), 1018 (XVDIVDP $A, $B)>; 1019 1020// Reciprocal estimate 1021def : Pat<(int_ppc_vsx_xvresp v4f32:$A), 1022 (XVRESP $A)>; 1023def : Pat<(int_ppc_vsx_xvredp v2f64:$A), 1024 (XVREDP $A)>; 1025 1026// Recip. square root estimate 1027def : Pat<(int_ppc_vsx_xvrsqrtesp v4f32:$A), 1028 (XVRSQRTESP $A)>; 1029def : Pat<(int_ppc_vsx_xvrsqrtedp v2f64:$A), 1030 (XVRSQRTEDP $A)>; 1031 1032} // AddedComplexity 1033} // HasVSX 1034 1035// The following VSX instructions were introduced in Power ISA 2.07 1036/* FIXME: if the operands are v2i64, these patterns will not match. 1037 we should define new patterns or otherwise match the same patterns 1038 when the elements are larger than i32. 1039*/ 1040def HasP8Vector : Predicate<"PPCSubTarget->hasP8Vector()">; 1041def HasDirectMove : Predicate<"PPCSubTarget->hasDirectMove()">; 1042let Predicates = [HasP8Vector] in { 1043let AddedComplexity = 400 in { // Prefer VSX patterns over non-VSX patterns. 1044 let isCommutable = 1 in { 1045 def XXLEQV : XX3Form<60, 186, 1046 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB), 1047 "xxleqv $XT, $XA, $XB", IIC_VecGeneral, 1048 [(set v4i32:$XT, (vnot_ppc (xor v4i32:$XA, v4i32:$XB)))]>; 1049 def XXLNAND : XX3Form<60, 178, 1050 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB), 1051 "xxlnand $XT, $XA, $XB", IIC_VecGeneral, 1052 [(set v4i32:$XT, (vnot_ppc (and v4i32:$XA, 1053 v4i32:$XB)))]>; 1054 } // isCommutable 1055 1056 def : Pat<(int_ppc_vsx_xxleqv v4i32:$A, v4i32:$B), 1057 (XXLEQV $A, $B)>; 1058 1059 def XXLORC : XX3Form<60, 170, 1060 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB), 1061 "xxlorc $XT, $XA, $XB", IIC_VecGeneral, 1062 [(set v4i32:$XT, (or v4i32:$XA, (vnot_ppc v4i32:$XB)))]>; 1063 1064 // VSX scalar loads introduced in ISA 2.07 1065 let mayLoad = 1 in { 1066 def LXSSPX : XX1Form<31, 524, (outs vssrc:$XT), (ins memrr:$src), 1067 "lxsspx $XT, $src", IIC_LdStLFD, 1068 [(set f32:$XT, (load xoaddr:$src))]>; 1069 def LXSIWAX : XX1Form<31, 76, (outs vsfrc:$XT), (ins memrr:$src), 1070 "lxsiwax $XT, $src", IIC_LdStLFD, 1071 [(set f64:$XT, (PPClfiwax xoaddr:$src))]>; 1072 def LXSIWZX : XX1Form<31, 12, (outs vsfrc:$XT), (ins memrr:$src), 1073 "lxsiwzx $XT, $src", IIC_LdStLFD, 1074 [(set f64:$XT, (PPClfiwzx xoaddr:$src))]>; 1075 } // mayLoad 1076 1077 // VSX scalar stores introduced in ISA 2.07 1078 let mayStore = 1 in { 1079 def STXSSPX : XX1Form<31, 652, (outs), (ins vssrc:$XT, memrr:$dst), 1080 "stxsspx $XT, $dst", IIC_LdStSTFD, 1081 [(store f32:$XT, xoaddr:$dst)]>; 1082 def STXSIWX : XX1Form<31, 140, (outs), (ins vsfrc:$XT, memrr:$dst), 1083 "stxsiwx $XT, $dst", IIC_LdStSTFD, 1084 [(PPCstfiwx f64:$XT, xoaddr:$dst)]>; 1085 } // mayStore 1086 1087 def : Pat<(f64 (extloadf32 xoaddr:$src)), 1088 (COPY_TO_REGCLASS (LXSSPX xoaddr:$src), VSFRC)>; 1089 def : Pat<(f64 (fextend f32:$src)), 1090 (COPY_TO_REGCLASS $src, VSFRC)>; 1091 1092 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETLT)), 1093 (SELECT_VSSRC (CRANDC $lhs, $rhs), $tval, $fval)>; 1094 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETULT)), 1095 (SELECT_VSSRC (CRANDC $rhs, $lhs), $tval, $fval)>; 1096 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETLE)), 1097 (SELECT_VSSRC (CRORC $lhs, $rhs), $tval, $fval)>; 1098 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETULE)), 1099 (SELECT_VSSRC (CRORC $rhs, $lhs), $tval, $fval)>; 1100 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETEQ)), 1101 (SELECT_VSSRC (CREQV $lhs, $rhs), $tval, $fval)>; 1102 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETGE)), 1103 (SELECT_VSSRC (CRORC $rhs, $lhs), $tval, $fval)>; 1104 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETUGE)), 1105 (SELECT_VSSRC (CRORC $lhs, $rhs), $tval, $fval)>; 1106 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETGT)), 1107 (SELECT_VSSRC (CRANDC $rhs, $lhs), $tval, $fval)>; 1108 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETUGT)), 1109 (SELECT_VSSRC (CRANDC $lhs, $rhs), $tval, $fval)>; 1110 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETNE)), 1111 (SELECT_VSSRC (CRXOR $lhs, $rhs), $tval, $fval)>; 1112 1113 // VSX Elementary Scalar FP arithmetic (SP) 1114 let isCommutable = 1 in { 1115 def XSADDSP : XX3Form<60, 0, 1116 (outs vssrc:$XT), (ins vssrc:$XA, vssrc:$XB), 1117 "xsaddsp $XT, $XA, $XB", IIC_VecFP, 1118 [(set f32:$XT, (fadd f32:$XA, f32:$XB))]>; 1119 def XSMULSP : XX3Form<60, 16, 1120 (outs vssrc:$XT), (ins vssrc:$XA, vssrc:$XB), 1121 "xsmulsp $XT, $XA, $XB", IIC_VecFP, 1122 [(set f32:$XT, (fmul f32:$XA, f32:$XB))]>; 1123 } // isCommutable 1124 1125 def XSDIVSP : XX3Form<60, 24, 1126 (outs vssrc:$XT), (ins vssrc:$XA, vssrc:$XB), 1127 "xsdivsp $XT, $XA, $XB", IIC_FPDivS, 1128 [(set f32:$XT, (fdiv f32:$XA, f32:$XB))]>; 1129 def XSRESP : XX2Form<60, 26, 1130 (outs vssrc:$XT), (ins vssrc:$XB), 1131 "xsresp $XT, $XB", IIC_VecFP, 1132 [(set f32:$XT, (PPCfre f32:$XB))]>; 1133 def XSSQRTSP : XX2Form<60, 11, 1134 (outs vssrc:$XT), (ins vssrc:$XB), 1135 "xssqrtsp $XT, $XB", IIC_FPSqrtS, 1136 [(set f32:$XT, (fsqrt f32:$XB))]>; 1137 def XSRSQRTESP : XX2Form<60, 10, 1138 (outs vssrc:$XT), (ins vssrc:$XB), 1139 "xsrsqrtesp $XT, $XB", IIC_VecFP, 1140 [(set f32:$XT, (PPCfrsqrte f32:$XB))]>; 1141 def XSSUBSP : XX3Form<60, 8, 1142 (outs vssrc:$XT), (ins vssrc:$XA, vssrc:$XB), 1143 "xssubsp $XT, $XA, $XB", IIC_VecFP, 1144 [(set f32:$XT, (fsub f32:$XA, f32:$XB))]>; 1145 1146 // FMA Instructions 1147 let BaseName = "XSMADDASP" in { 1148 let isCommutable = 1 in 1149 def XSMADDASP : XX3Form<60, 1, 1150 (outs vssrc:$XT), 1151 (ins vssrc:$XTi, vssrc:$XA, vssrc:$XB), 1152 "xsmaddasp $XT, $XA, $XB", IIC_VecFP, 1153 [(set f32:$XT, (fma f32:$XA, f32:$XB, f32:$XTi))]>, 1154 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">, 1155 AltVSXFMARel; 1156 let IsVSXFMAAlt = 1 in 1157 def XSMADDMSP : XX3Form<60, 9, 1158 (outs vssrc:$XT), 1159 (ins vssrc:$XTi, vssrc:$XA, vssrc:$XB), 1160 "xsmaddmsp $XT, $XA, $XB", IIC_VecFP, []>, 1161 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">, 1162 AltVSXFMARel; 1163 } 1164 1165 let BaseName = "XSMSUBASP" in { 1166 let isCommutable = 1 in 1167 def XSMSUBASP : XX3Form<60, 17, 1168 (outs vssrc:$XT), 1169 (ins vssrc:$XTi, vssrc:$XA, vssrc:$XB), 1170 "xsmsubasp $XT, $XA, $XB", IIC_VecFP, 1171 [(set f32:$XT, (fma f32:$XA, f32:$XB, 1172 (fneg f32:$XTi)))]>, 1173 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">, 1174 AltVSXFMARel; 1175 let IsVSXFMAAlt = 1 in 1176 def XSMSUBMSP : XX3Form<60, 25, 1177 (outs vssrc:$XT), 1178 (ins vssrc:$XTi, vssrc:$XA, vssrc:$XB), 1179 "xsmsubmsp $XT, $XA, $XB", IIC_VecFP, []>, 1180 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">, 1181 AltVSXFMARel; 1182 } 1183 1184 let BaseName = "XSNMADDASP" in { 1185 let isCommutable = 1 in 1186 def XSNMADDASP : XX3Form<60, 129, 1187 (outs vssrc:$XT), 1188 (ins vssrc:$XTi, vssrc:$XA, vssrc:$XB), 1189 "xsnmaddasp $XT, $XA, $XB", IIC_VecFP, 1190 [(set f32:$XT, (fneg (fma f32:$XA, f32:$XB, 1191 f32:$XTi)))]>, 1192 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">, 1193 AltVSXFMARel; 1194 let IsVSXFMAAlt = 1 in 1195 def XSNMADDMSP : XX3Form<60, 137, 1196 (outs vssrc:$XT), 1197 (ins vssrc:$XTi, vssrc:$XA, vssrc:$XB), 1198 "xsnmaddmsp $XT, $XA, $XB", IIC_VecFP, []>, 1199 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">, 1200 AltVSXFMARel; 1201 } 1202 1203 let BaseName = "XSNMSUBASP" in { 1204 let isCommutable = 1 in 1205 def XSNMSUBASP : XX3Form<60, 145, 1206 (outs vssrc:$XT), 1207 (ins vssrc:$XTi, vssrc:$XA, vssrc:$XB), 1208 "xsnmsubasp $XT, $XA, $XB", IIC_VecFP, 1209 [(set f32:$XT, (fneg (fma f32:$XA, f32:$XB, 1210 (fneg f32:$XTi))))]>, 1211 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">, 1212 AltVSXFMARel; 1213 let IsVSXFMAAlt = 1 in 1214 def XSNMSUBMSP : XX3Form<60, 153, 1215 (outs vssrc:$XT), 1216 (ins vssrc:$XTi, vssrc:$XA, vssrc:$XB), 1217 "xsnmsubmsp $XT, $XA, $XB", IIC_VecFP, []>, 1218 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">, 1219 AltVSXFMARel; 1220 } 1221 1222 // Single Precision Conversions (FP <-> INT) 1223 def XSCVSXDSP : XX2Form<60, 312, 1224 (outs vssrc:$XT), (ins vsfrc:$XB), 1225 "xscvsxdsp $XT, $XB", IIC_VecFP, 1226 [(set f32:$XT, (PPCfcfids f64:$XB))]>; 1227 def XSCVUXDSP : XX2Form<60, 296, 1228 (outs vssrc:$XT), (ins vsfrc:$XB), 1229 "xscvuxdsp $XT, $XB", IIC_VecFP, 1230 [(set f32:$XT, (PPCfcfidus f64:$XB))]>; 1231 1232 // Conversions between vector and scalar single precision 1233 def XSCVDPSPN : XX2Form<60, 267, (outs vsrc:$XT), (ins vssrc:$XB), 1234 "xscvdpspn $XT, $XB", IIC_VecFP, []>; 1235 def XSCVSPDPN : XX2Form<60, 331, (outs vssrc:$XT), (ins vsrc:$XB), 1236 "xscvspdpn $XT, $XB", IIC_VecFP, []>; 1237 1238} // AddedComplexity = 400 1239} // HasP8Vector 1240 1241let Predicates = [HasDirectMove] in { 1242 // VSX direct move instructions 1243 def MFVSRD : XX1_RS6_RD5_XO<31, 51, (outs g8rc:$rA), (ins vsfrc:$XT), 1244 "mfvsrd $rA, $XT", IIC_VecGeneral, 1245 [(set i64:$rA, (PPCmfvsr f64:$XT))]>, 1246 Requires<[In64BitMode]>; 1247 def MFVSRWZ : XX1_RS6_RD5_XO<31, 115, (outs gprc:$rA), (ins vsfrc:$XT), 1248 "mfvsrwz $rA, $XT", IIC_VecGeneral, 1249 [(set i32:$rA, (PPCmfvsr f64:$XT))]>; 1250 def MTVSRD : XX1_RS6_RD5_XO<31, 179, (outs vsfrc:$XT), (ins g8rc:$rA), 1251 "mtvsrd $XT, $rA", IIC_VecGeneral, 1252 [(set f64:$XT, (PPCmtvsra i64:$rA))]>, 1253 Requires<[In64BitMode]>; 1254 def MTVSRWA : XX1_RS6_RD5_XO<31, 211, (outs vsfrc:$XT), (ins gprc:$rA), 1255 "mtvsrwa $XT, $rA", IIC_VecGeneral, 1256 [(set f64:$XT, (PPCmtvsra i32:$rA))]>; 1257 def MTVSRWZ : XX1_RS6_RD5_XO<31, 243, (outs vsfrc:$XT), (ins gprc:$rA), 1258 "mtvsrwz $XT, $rA", IIC_VecGeneral, 1259 [(set f64:$XT, (PPCmtvsrz i32:$rA))]>; 1260} // HasDirectMove 1261 1262let Predicates = [IsISA3_0, HasDirectMove] in { 1263 def MTVSRWS: XX1_RS6_RD5_XO<31, 403, (outs vsrc:$XT), (ins gprc:$rA), 1264 "mtvsrws $XT, $rA", IIC_VecGeneral, 1265 []>; 1266 1267 def MTVSRDD: XX1Form<31, 435, (outs vsrc:$XT), (ins g8rc:$rA, g8rc:$rB), 1268 "mtvsrdd $XT, $rA, $rB", IIC_VecGeneral, 1269 []>, Requires<[In64BitMode]>; 1270 1271 def MFVSRLD: XX1_RS6_RD5_XO<31, 307, (outs g8rc:$rA), (ins vsrc:$XT), 1272 "mfvsrld $rA, $XT", IIC_VecGeneral, 1273 []>, Requires<[In64BitMode]>; 1274 1275} // IsISA3_0, HasDirectMove 1276 1277/* Direct moves of various widths from GPR's into VSR's. Each move lines 1278 the value up into element 0 (both BE and LE). Namely, entities smaller than 1279 a doubleword are shifted left and moved for BE. For LE, they're moved, then 1280 swapped to go into the least significant element of the VSR. 1281*/ 1282def MovesToVSR { 1283 dag BE_BYTE_0 = 1284 (MTVSRD 1285 (RLDICR 1286 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $A, sub_32), 56, 7)); 1287 dag BE_HALF_0 = 1288 (MTVSRD 1289 (RLDICR 1290 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $A, sub_32), 48, 15)); 1291 dag BE_WORD_0 = 1292 (MTVSRD 1293 (RLDICR 1294 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $A, sub_32), 32, 31)); 1295 dag BE_DWORD_0 = (MTVSRD $A); 1296 1297 dag LE_MTVSRW = (MTVSRD (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $A, sub_32)); 1298 dag LE_WORD_1 = (v2i64 (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)), 1299 LE_MTVSRW, sub_64)); 1300 dag LE_WORD_0 = (XXPERMDI LE_WORD_1, LE_WORD_1, 2); 1301 dag LE_DWORD_1 = (v2i64 (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)), 1302 BE_DWORD_0, sub_64)); 1303 dag LE_DWORD_0 = (XXPERMDI LE_DWORD_1, LE_DWORD_1, 2); 1304} 1305 1306/* Patterns for extracting elements out of vectors. Integer elements are 1307 extracted using direct move operations. Patterns for extracting elements 1308 whose indices are not available at compile time are also provided with 1309 various _VARIABLE_ patterns. 1310 The numbering for the DAG's is for LE, but when used on BE, the correct 1311 LE element can just be used (i.e. LE_BYTE_2 == BE_BYTE_13). 1312*/ 1313def VectorExtractions { 1314 // Doubleword extraction 1315 dag LE_DWORD_0 = 1316 (MFVSRD 1317 (EXTRACT_SUBREG 1318 (XXPERMDI (COPY_TO_REGCLASS $S, VSRC), 1319 (COPY_TO_REGCLASS $S, VSRC), 2), sub_64)); 1320 dag LE_DWORD_1 = (MFVSRD 1321 (EXTRACT_SUBREG 1322 (v2i64 (COPY_TO_REGCLASS $S, VSRC)), sub_64)); 1323 1324 // Word extraction 1325 dag LE_WORD_0 = (MFVSRWZ (EXTRACT_SUBREG (XXPERMDI $S, $S, 2), sub_64)); 1326 dag LE_WORD_1 = (MFVSRWZ (EXTRACT_SUBREG (XXSLDWI $S, $S, 1), sub_64)); 1327 dag LE_WORD_2 = (MFVSRWZ (EXTRACT_SUBREG 1328 (v2i64 (COPY_TO_REGCLASS $S, VSRC)), sub_64)); 1329 dag LE_WORD_3 = (MFVSRWZ (EXTRACT_SUBREG (XXSLDWI $S, $S, 3), sub_64)); 1330 1331 // Halfword extraction 1332 dag LE_HALF_0 = (i32 (EXTRACT_SUBREG (RLDICL LE_DWORD_0, 0, 48), sub_32)); 1333 dag LE_HALF_1 = (i32 (EXTRACT_SUBREG (RLDICL LE_DWORD_0, 48, 48), sub_32)); 1334 dag LE_HALF_2 = (i32 (EXTRACT_SUBREG (RLDICL LE_DWORD_0, 32, 48), sub_32)); 1335 dag LE_HALF_3 = (i32 (EXTRACT_SUBREG (RLDICL LE_DWORD_0, 16, 48), sub_32)); 1336 dag LE_HALF_4 = (i32 (EXTRACT_SUBREG (RLDICL LE_DWORD_1, 0, 48), sub_32)); 1337 dag LE_HALF_5 = (i32 (EXTRACT_SUBREG (RLDICL LE_DWORD_1, 48, 48), sub_32)); 1338 dag LE_HALF_6 = (i32 (EXTRACT_SUBREG (RLDICL LE_DWORD_1, 32, 48), sub_32)); 1339 dag LE_HALF_7 = (i32 (EXTRACT_SUBREG (RLDICL LE_DWORD_1, 16, 48), sub_32)); 1340 1341 // Byte extraction 1342 dag LE_BYTE_0 = (i32 (EXTRACT_SUBREG (RLDICL LE_DWORD_0, 0, 56), sub_32)); 1343 dag LE_BYTE_1 = (i32 (EXTRACT_SUBREG (RLDICL LE_DWORD_0, 56, 56), sub_32)); 1344 dag LE_BYTE_2 = (i32 (EXTRACT_SUBREG (RLDICL LE_DWORD_0, 48, 56), sub_32)); 1345 dag LE_BYTE_3 = (i32 (EXTRACT_SUBREG (RLDICL LE_DWORD_0, 40, 56), sub_32)); 1346 dag LE_BYTE_4 = (i32 (EXTRACT_SUBREG (RLDICL LE_DWORD_0, 32, 56), sub_32)); 1347 dag LE_BYTE_5 = (i32 (EXTRACT_SUBREG (RLDICL LE_DWORD_0, 24, 56), sub_32)); 1348 dag LE_BYTE_6 = (i32 (EXTRACT_SUBREG (RLDICL LE_DWORD_0, 16, 56), sub_32)); 1349 dag LE_BYTE_7 = (i32 (EXTRACT_SUBREG (RLDICL LE_DWORD_0, 8, 56), sub_32)); 1350 dag LE_BYTE_8 = (i32 (EXTRACT_SUBREG (RLDICL LE_DWORD_1, 0, 56), sub_32)); 1351 dag LE_BYTE_9 = (i32 (EXTRACT_SUBREG (RLDICL LE_DWORD_1, 56, 56), sub_32)); 1352 dag LE_BYTE_10 = (i32 (EXTRACT_SUBREG (RLDICL LE_DWORD_1, 48, 56), sub_32)); 1353 dag LE_BYTE_11 = (i32 (EXTRACT_SUBREG (RLDICL LE_DWORD_1, 40, 56), sub_32)); 1354 dag LE_BYTE_12 = (i32 (EXTRACT_SUBREG (RLDICL LE_DWORD_1, 32, 56), sub_32)); 1355 dag LE_BYTE_13 = (i32 (EXTRACT_SUBREG (RLDICL LE_DWORD_1, 24, 56), sub_32)); 1356 dag LE_BYTE_14 = (i32 (EXTRACT_SUBREG (RLDICL LE_DWORD_1, 16, 56), sub_32)); 1357 dag LE_BYTE_15 = (i32 (EXTRACT_SUBREG (RLDICL LE_DWORD_1, 8, 56), sub_32)); 1358 1359 /* Variable element number (BE and LE patterns must be specified separately) 1360 This is a rather involved process. 1361 1362 Conceptually, this is how the move is accomplished: 1363 1. Identify which doubleword contains the element 1364 2. Shift in the VMX register so that the correct doubleword is correctly 1365 lined up for the MFVSRD 1366 3. Perform the move so that the element (along with some extra stuff) 1367 is in the GPR 1368 4. Right shift within the GPR so that the element is right-justified 1369 1370 Of course, the index is an element number which has a different meaning 1371 on LE/BE so the patterns have to be specified separately. 1372 1373 Note: The final result will be the element right-justified with high 1374 order bits being arbitrarily defined (namely, whatever was in the 1375 vector register to the left of the value originally). 1376 */ 1377 1378 /* LE variable byte 1379 Number 1. above: 1380 - For elements 0-7, we shift left by 8 bytes since they're on the right 1381 - For elements 8-15, we need not shift (shift left by zero bytes) 1382 This is accomplished by inverting the bits of the index and AND-ing 1383 with 0x8 (i.e. clearing all bits of the index and inverting bit 60). 1384 */ 1385 dag LE_VBYTE_PERM_VEC = (LVSL ZERO8, (ANDC8 (LI8 8), $Idx)); 1386 1387 // Number 2. above: 1388 // - Now that we set up the shift amount, we shift in the VMX register 1389 dag LE_VBYTE_PERMUTE = (VPERM $S, $S, LE_VBYTE_PERM_VEC); 1390 1391 // Number 3. above: 1392 // - The doubleword containing our element is moved to a GPR 1393 dag LE_MV_VBYTE = (MFVSRD 1394 (EXTRACT_SUBREG 1395 (v2i64 (COPY_TO_REGCLASS LE_VBYTE_PERMUTE, VSRC)), 1396 sub_64)); 1397 1398 /* Number 4. above: 1399 - Truncate the element number to the range 0-7 (8-15 are symmetrical 1400 and out of range values are truncated accordingly) 1401 - Multiply by 8 as we need to shift right by the number of bits, not bytes 1402 - Shift right in the GPR by the calculated value 1403 */ 1404 dag LE_VBYTE_SHIFT = (EXTRACT_SUBREG (RLDICR (AND8 (LI8 7), $Idx), 3, 60), 1405 sub_32); 1406 dag LE_VARIABLE_BYTE = (EXTRACT_SUBREG (SRD LE_MV_VBYTE, LE_VBYTE_SHIFT), 1407 sub_32); 1408 1409 /* LE variable halfword 1410 Number 1. above: 1411 - For elements 0-3, we shift left by 8 since they're on the right 1412 - For elements 4-7, we need not shift (shift left by zero bytes) 1413 Similarly to the byte pattern, we invert the bits of the index, but we 1414 AND with 0x4 (i.e. clear all bits of the index and invert bit 61). 1415 Of course, the shift is still by 8 bytes, so we must multiply by 2. 1416 */ 1417 dag LE_VHALF_PERM_VEC = (LVSL ZERO8, (RLDICR (ANDC8 (LI8 4), $Idx), 1, 62)); 1418 1419 // Number 2. above: 1420 // - Now that we set up the shift amount, we shift in the VMX register 1421 dag LE_VHALF_PERMUTE = (VPERM $S, $S, LE_VHALF_PERM_VEC); 1422 1423 // Number 3. above: 1424 // - The doubleword containing our element is moved to a GPR 1425 dag LE_MV_VHALF = (MFVSRD 1426 (EXTRACT_SUBREG 1427 (v2i64 (COPY_TO_REGCLASS LE_VHALF_PERMUTE, VSRC)), 1428 sub_64)); 1429 1430 /* Number 4. above: 1431 - Truncate the element number to the range 0-3 (4-7 are symmetrical 1432 and out of range values are truncated accordingly) 1433 - Multiply by 16 as we need to shift right by the number of bits 1434 - Shift right in the GPR by the calculated value 1435 */ 1436 dag LE_VHALF_SHIFT = (EXTRACT_SUBREG (RLDICR (AND8 (LI8 3), $Idx), 4, 59), 1437 sub_32); 1438 dag LE_VARIABLE_HALF = (EXTRACT_SUBREG (SRD LE_MV_VHALF, LE_VHALF_SHIFT), 1439 sub_32); 1440 1441 /* LE variable word 1442 Number 1. above: 1443 - For elements 0-1, we shift left by 8 since they're on the right 1444 - For elements 2-3, we need not shift 1445 */ 1446 dag LE_VWORD_PERM_VEC = (LVSL ZERO8, (RLDICR (ANDC8 (LI8 2), $Idx), 2, 61)); 1447 1448 // Number 2. above: 1449 // - Now that we set up the shift amount, we shift in the VMX register 1450 dag LE_VWORD_PERMUTE = (VPERM $S, $S, LE_VWORD_PERM_VEC); 1451 1452 // Number 3. above: 1453 // - The doubleword containing our element is moved to a GPR 1454 dag LE_MV_VWORD = (MFVSRD 1455 (EXTRACT_SUBREG 1456 (v2i64 (COPY_TO_REGCLASS LE_VWORD_PERMUTE, VSRC)), 1457 sub_64)); 1458 1459 /* Number 4. above: 1460 - Truncate the element number to the range 0-1 (2-3 are symmetrical 1461 and out of range values are truncated accordingly) 1462 - Multiply by 32 as we need to shift right by the number of bits 1463 - Shift right in the GPR by the calculated value 1464 */ 1465 dag LE_VWORD_SHIFT = (EXTRACT_SUBREG (RLDICR (AND8 (LI8 1), $Idx), 5, 58), 1466 sub_32); 1467 dag LE_VARIABLE_WORD = (EXTRACT_SUBREG (SRD LE_MV_VWORD, LE_VWORD_SHIFT), 1468 sub_32); 1469 1470 /* LE variable doubleword 1471 Number 1. above: 1472 - For element 0, we shift left by 8 since it's on the right 1473 - For element 1, we need not shift 1474 */ 1475 dag LE_VDWORD_PERM_VEC = (LVSL ZERO8, (RLDICR (ANDC8 (LI8 1), $Idx), 3, 60)); 1476 1477 // Number 2. above: 1478 // - Now that we set up the shift amount, we shift in the VMX register 1479 dag LE_VDWORD_PERMUTE = (VPERM $S, $S, LE_VDWORD_PERM_VEC); 1480 1481 // Number 3. above: 1482 // - The doubleword containing our element is moved to a GPR 1483 // - Number 4. is not needed for the doubleword as the value is 64-bits 1484 dag LE_VARIABLE_DWORD = 1485 (MFVSRD (EXTRACT_SUBREG 1486 (v2i64 (COPY_TO_REGCLASS LE_VDWORD_PERMUTE, VSRC)), 1487 sub_64)); 1488 1489 /* LE variable float 1490 - Shift the vector to line up the desired element to BE Word 0 1491 - Convert 32-bit float to a 64-bit single precision float 1492 */ 1493 dag LE_VFLOAT_PERM_VEC = (LVSL ZERO8, (RLDICR (XOR8 (LI8 3), $Idx), 2, 61)); 1494 dag LE_VFLOAT_PERMUTE = (VPERM $S, $S, LE_VFLOAT_PERM_VEC); 1495 dag LE_VARIABLE_FLOAT = (XSCVSPDPN LE_VFLOAT_PERMUTE); 1496 1497 /* LE variable double 1498 Same as the LE doubleword except there is no move. 1499 */ 1500 dag LE_VDOUBLE_PERMUTE = (VPERM (COPY_TO_REGCLASS $S, VRRC), 1501 (COPY_TO_REGCLASS $S, VRRC), 1502 LE_VDWORD_PERM_VEC); 1503 dag LE_VARIABLE_DOUBLE = (COPY_TO_REGCLASS LE_VDOUBLE_PERMUTE, VSRC); 1504 1505 /* BE variable byte 1506 The algorithm here is the same as the LE variable byte except: 1507 - The shift in the VMX register is by 0/8 for opposite element numbers so 1508 we simply AND the element number with 0x8 1509 - The order of elements after the move to GPR is reversed, so we invert 1510 the bits of the index prior to truncating to the range 0-7 1511 */ 1512 dag BE_VBYTE_PERM_VEC = (LVSL ZERO8, (ANDIo8 $Idx, 8)); 1513 dag BE_VBYTE_PERMUTE = (VPERM $S, $S, BE_VBYTE_PERM_VEC); 1514 dag BE_MV_VBYTE = (MFVSRD 1515 (EXTRACT_SUBREG 1516 (v2i64 (COPY_TO_REGCLASS BE_VBYTE_PERMUTE, VSRC)), 1517 sub_64)); 1518 dag BE_VBYTE_SHIFT = (EXTRACT_SUBREG (RLDICR (ANDC8 (LI8 7), $Idx), 3, 60), 1519 sub_32); 1520 dag BE_VARIABLE_BYTE = (EXTRACT_SUBREG (SRD BE_MV_VBYTE, BE_VBYTE_SHIFT), 1521 sub_32); 1522 1523 /* BE variable halfword 1524 The algorithm here is the same as the LE variable halfword except: 1525 - The shift in the VMX register is by 0/8 for opposite element numbers so 1526 we simply AND the element number with 0x4 and multiply by 2 1527 - The order of elements after the move to GPR is reversed, so we invert 1528 the bits of the index prior to truncating to the range 0-3 1529 */ 1530 dag BE_VHALF_PERM_VEC = (LVSL ZERO8, (RLDICR (ANDIo8 $Idx, 4), 1, 62)); 1531 dag BE_VHALF_PERMUTE = (VPERM $S, $S, BE_VHALF_PERM_VEC); 1532 dag BE_MV_VHALF = (MFVSRD 1533 (EXTRACT_SUBREG 1534 (v2i64 (COPY_TO_REGCLASS BE_VHALF_PERMUTE, VSRC)), 1535 sub_64)); 1536 dag BE_VHALF_SHIFT = (EXTRACT_SUBREG (RLDICR (ANDC8 (LI8 3), $Idx), 4, 59), 1537 sub_32); 1538 dag BE_VARIABLE_HALF = (EXTRACT_SUBREG (SRD BE_MV_VHALF, BE_VHALF_SHIFT), 1539 sub_32); 1540 1541 /* BE variable word 1542 The algorithm is the same as the LE variable word except: 1543 - The shift in the VMX register happens for opposite element numbers 1544 - The order of elements after the move to GPR is reversed, so we invert 1545 the bits of the index prior to truncating to the range 0-1 1546 */ 1547 dag BE_VWORD_PERM_VEC = (LVSL ZERO8, (RLDICR (ANDIo8 $Idx, 2), 2, 61)); 1548 dag BE_VWORD_PERMUTE = (VPERM $S, $S, BE_VWORD_PERM_VEC); 1549 dag BE_MV_VWORD = (MFVSRD 1550 (EXTRACT_SUBREG 1551 (v2i64 (COPY_TO_REGCLASS BE_VWORD_PERMUTE, VSRC)), 1552 sub_64)); 1553 dag BE_VWORD_SHIFT = (EXTRACT_SUBREG (RLDICR (ANDC8 (LI8 1), $Idx), 5, 58), 1554 sub_32); 1555 dag BE_VARIABLE_WORD = (EXTRACT_SUBREG (SRD BE_MV_VWORD, BE_VWORD_SHIFT), 1556 sub_32); 1557 1558 /* BE variable doubleword 1559 Same as the LE doubleword except we shift in the VMX register for opposite 1560 element indices. 1561 */ 1562 dag BE_VDWORD_PERM_VEC = (LVSL ZERO8, (RLDICR (ANDIo8 $Idx, 1), 3, 60)); 1563 dag BE_VDWORD_PERMUTE = (VPERM $S, $S, BE_VDWORD_PERM_VEC); 1564 dag BE_VARIABLE_DWORD = 1565 (MFVSRD (EXTRACT_SUBREG 1566 (v2i64 (COPY_TO_REGCLASS BE_VDWORD_PERMUTE, VSRC)), 1567 sub_64)); 1568 1569 /* BE variable float 1570 - Shift the vector to line up the desired element to BE Word 0 1571 - Convert 32-bit float to a 64-bit single precision float 1572 */ 1573 dag BE_VFLOAT_PERM_VEC = (LVSL ZERO8, (RLDICR $Idx, 2, 61)); 1574 dag BE_VFLOAT_PERMUTE = (VPERM $S, $S, BE_VFLOAT_PERM_VEC); 1575 dag BE_VARIABLE_FLOAT = (XSCVSPDPN BE_VFLOAT_PERMUTE); 1576 1577 /* BE variable double 1578 Same as the BE doubleword except there is no move. 1579 */ 1580 dag BE_VDOUBLE_PERMUTE = (VPERM (COPY_TO_REGCLASS $S, VRRC), 1581 (COPY_TO_REGCLASS $S, VRRC), 1582 BE_VDWORD_PERM_VEC); 1583 dag BE_VARIABLE_DOUBLE = (COPY_TO_REGCLASS BE_VDOUBLE_PERMUTE, VSRC); 1584} 1585 1586// v4f32 scalar <-> vector conversions (BE) 1587let Predicates = [IsBigEndian, HasP8Vector] in { 1588 def : Pat<(v4f32 (scalar_to_vector f32:$A)), 1589 (v4f32 (XSCVDPSPN $A))>; 1590 def : Pat<(f32 (vector_extract v4f32:$S, 0)), 1591 (f32 (XSCVSPDPN $S))>; 1592 def : Pat<(f32 (vector_extract v4f32:$S, 1)), 1593 (f32 (XSCVSPDPN (XXSLDWI $S, $S, 1)))>; 1594 def : Pat<(f32 (vector_extract v4f32:$S, 2)), 1595 (f32 (XSCVSPDPN (XXPERMDI $S, $S, 2)))>; 1596 def : Pat<(f32 (vector_extract v4f32:$S, 3)), 1597 (f32 (XSCVSPDPN (XXSLDWI $S, $S, 3)))>; 1598 def : Pat<(f32 (vector_extract v4f32:$S, i64:$Idx)), 1599 (f32 VectorExtractions.BE_VARIABLE_FLOAT)>; 1600} // IsBigEndian, HasP8Vector 1601 1602// Variable index vector_extract for v2f64 does not require P8Vector 1603let Predicates = [IsBigEndian, HasVSX] in 1604 def : Pat<(f64 (vector_extract v2f64:$S, i64:$Idx)), 1605 (f64 VectorExtractions.BE_VARIABLE_DOUBLE)>; 1606 1607let Predicates = [IsBigEndian, HasDirectMove] in { 1608 // v16i8 scalar <-> vector conversions (BE) 1609 def : Pat<(v16i8 (scalar_to_vector i32:$A)), 1610 (v16i8 (SUBREG_TO_REG (i64 1), MovesToVSR.BE_BYTE_0, sub_64))>; 1611 def : Pat<(v8i16 (scalar_to_vector i32:$A)), 1612 (v8i16 (SUBREG_TO_REG (i64 1), MovesToVSR.BE_HALF_0, sub_64))>; 1613 def : Pat<(v4i32 (scalar_to_vector i32:$A)), 1614 (v4i32 (SUBREG_TO_REG (i64 1), MovesToVSR.BE_WORD_0, sub_64))>; 1615 def : Pat<(v2i64 (scalar_to_vector i64:$A)), 1616 (v2i64 (SUBREG_TO_REG (i64 1), MovesToVSR.BE_DWORD_0, sub_64))>; 1617 def : Pat<(i32 (vector_extract v16i8:$S, 0)), 1618 (i32 VectorExtractions.LE_BYTE_15)>; 1619 def : Pat<(i32 (vector_extract v16i8:$S, 1)), 1620 (i32 VectorExtractions.LE_BYTE_14)>; 1621 def : Pat<(i32 (vector_extract v16i8:$S, 2)), 1622 (i32 VectorExtractions.LE_BYTE_13)>; 1623 def : Pat<(i32 (vector_extract v16i8:$S, 3)), 1624 (i32 VectorExtractions.LE_BYTE_12)>; 1625 def : Pat<(i32 (vector_extract v16i8:$S, 4)), 1626 (i32 VectorExtractions.LE_BYTE_11)>; 1627 def : Pat<(i32 (vector_extract v16i8:$S, 5)), 1628 (i32 VectorExtractions.LE_BYTE_10)>; 1629 def : Pat<(i32 (vector_extract v16i8:$S, 6)), 1630 (i32 VectorExtractions.LE_BYTE_9)>; 1631 def : Pat<(i32 (vector_extract v16i8:$S, 7)), 1632 (i32 VectorExtractions.LE_BYTE_8)>; 1633 def : Pat<(i32 (vector_extract v16i8:$S, 8)), 1634 (i32 VectorExtractions.LE_BYTE_7)>; 1635 def : Pat<(i32 (vector_extract v16i8:$S, 9)), 1636 (i32 VectorExtractions.LE_BYTE_6)>; 1637 def : Pat<(i32 (vector_extract v16i8:$S, 10)), 1638 (i32 VectorExtractions.LE_BYTE_5)>; 1639 def : Pat<(i32 (vector_extract v16i8:$S, 11)), 1640 (i32 VectorExtractions.LE_BYTE_4)>; 1641 def : Pat<(i32 (vector_extract v16i8:$S, 12)), 1642 (i32 VectorExtractions.LE_BYTE_3)>; 1643 def : Pat<(i32 (vector_extract v16i8:$S, 13)), 1644 (i32 VectorExtractions.LE_BYTE_2)>; 1645 def : Pat<(i32 (vector_extract v16i8:$S, 14)), 1646 (i32 VectorExtractions.LE_BYTE_1)>; 1647 def : Pat<(i32 (vector_extract v16i8:$S, 15)), 1648 (i32 VectorExtractions.LE_BYTE_0)>; 1649 def : Pat<(i32 (vector_extract v16i8:$S, i64:$Idx)), 1650 (i32 VectorExtractions.BE_VARIABLE_BYTE)>; 1651 1652 // v8i16 scalar <-> vector conversions (BE) 1653 def : Pat<(i32 (vector_extract v8i16:$S, 0)), 1654 (i32 VectorExtractions.LE_HALF_7)>; 1655 def : Pat<(i32 (vector_extract v8i16:$S, 1)), 1656 (i32 VectorExtractions.LE_HALF_6)>; 1657 def : Pat<(i32 (vector_extract v8i16:$S, 2)), 1658 (i32 VectorExtractions.LE_HALF_5)>; 1659 def : Pat<(i32 (vector_extract v8i16:$S, 3)), 1660 (i32 VectorExtractions.LE_HALF_4)>; 1661 def : Pat<(i32 (vector_extract v8i16:$S, 4)), 1662 (i32 VectorExtractions.LE_HALF_3)>; 1663 def : Pat<(i32 (vector_extract v8i16:$S, 5)), 1664 (i32 VectorExtractions.LE_HALF_2)>; 1665 def : Pat<(i32 (vector_extract v8i16:$S, 6)), 1666 (i32 VectorExtractions.LE_HALF_1)>; 1667 def : Pat<(i32 (vector_extract v8i16:$S, 7)), 1668 (i32 VectorExtractions.LE_HALF_0)>; 1669 def : Pat<(i32 (vector_extract v8i16:$S, i64:$Idx)), 1670 (i32 VectorExtractions.BE_VARIABLE_HALF)>; 1671 1672 // v4i32 scalar <-> vector conversions (BE) 1673 def : Pat<(i32 (vector_extract v4i32:$S, 0)), 1674 (i32 VectorExtractions.LE_WORD_3)>; 1675 def : Pat<(i32 (vector_extract v4i32:$S, 1)), 1676 (i32 VectorExtractions.LE_WORD_2)>; 1677 def : Pat<(i32 (vector_extract v4i32:$S, 2)), 1678 (i32 VectorExtractions.LE_WORD_1)>; 1679 def : Pat<(i32 (vector_extract v4i32:$S, 3)), 1680 (i32 VectorExtractions.LE_WORD_0)>; 1681 def : Pat<(i32 (vector_extract v4i32:$S, i64:$Idx)), 1682 (i32 VectorExtractions.BE_VARIABLE_WORD)>; 1683 1684 // v2i64 scalar <-> vector conversions (BE) 1685 def : Pat<(i64 (vector_extract v2i64:$S, 0)), 1686 (i64 VectorExtractions.LE_DWORD_1)>; 1687 def : Pat<(i64 (vector_extract v2i64:$S, 1)), 1688 (i64 VectorExtractions.LE_DWORD_0)>; 1689 def : Pat<(i64 (vector_extract v2i64:$S, i64:$Idx)), 1690 (i64 VectorExtractions.BE_VARIABLE_DWORD)>; 1691} // IsBigEndian, HasDirectMove 1692 1693// v4f32 scalar <-> vector conversions (LE) 1694let Predicates = [IsLittleEndian, HasP8Vector] in { 1695 def : Pat<(v4f32 (scalar_to_vector f32:$A)), 1696 (v4f32 (XXSLDWI (XSCVDPSPN $A), (XSCVDPSPN $A), 1))>; 1697 def : Pat<(f32 (vector_extract v4f32:$S, 0)), 1698 (f32 (XSCVSPDPN (XXSLDWI $S, $S, 3)))>; 1699 def : Pat<(f32 (vector_extract v4f32:$S, 1)), 1700 (f32 (XSCVSPDPN (XXPERMDI $S, $S, 2)))>; 1701 def : Pat<(f32 (vector_extract v4f32:$S, 2)), 1702 (f32 (XSCVSPDPN (XXSLDWI $S, $S, 1)))>; 1703 def : Pat<(f32 (vector_extract v4f32:$S, 3)), 1704 (f32 (XSCVSPDPN $S))>; 1705 def : Pat<(f32 (vector_extract v4f32:$S, i64:$Idx)), 1706 (f32 VectorExtractions.LE_VARIABLE_FLOAT)>; 1707} // IsLittleEndian, HasP8Vector 1708 1709// Variable index vector_extract for v2f64 does not require P8Vector 1710let Predicates = [IsLittleEndian, HasVSX] in 1711 def : Pat<(f64 (vector_extract v2f64:$S, i64:$Idx)), 1712 (f64 VectorExtractions.LE_VARIABLE_DOUBLE)>; 1713 1714let Predicates = [IsLittleEndian, HasDirectMove] in { 1715 // v16i8 scalar <-> vector conversions (LE) 1716 def : Pat<(v16i8 (scalar_to_vector i32:$A)), 1717 (v16i8 (COPY_TO_REGCLASS MovesToVSR.LE_WORD_0, VSRC))>; 1718 def : Pat<(v8i16 (scalar_to_vector i32:$A)), 1719 (v8i16 (COPY_TO_REGCLASS MovesToVSR.LE_WORD_0, VSRC))>; 1720 def : Pat<(v4i32 (scalar_to_vector i32:$A)), 1721 (v4i32 MovesToVSR.LE_WORD_0)>; 1722 def : Pat<(v2i64 (scalar_to_vector i64:$A)), 1723 (v2i64 MovesToVSR.LE_DWORD_0)>; 1724 def : Pat<(i32 (vector_extract v16i8:$S, 0)), 1725 (i32 VectorExtractions.LE_BYTE_0)>; 1726 def : Pat<(i32 (vector_extract v16i8:$S, 1)), 1727 (i32 VectorExtractions.LE_BYTE_1)>; 1728 def : Pat<(i32 (vector_extract v16i8:$S, 2)), 1729 (i32 VectorExtractions.LE_BYTE_2)>; 1730 def : Pat<(i32 (vector_extract v16i8:$S, 3)), 1731 (i32 VectorExtractions.LE_BYTE_3)>; 1732 def : Pat<(i32 (vector_extract v16i8:$S, 4)), 1733 (i32 VectorExtractions.LE_BYTE_4)>; 1734 def : Pat<(i32 (vector_extract v16i8:$S, 5)), 1735 (i32 VectorExtractions.LE_BYTE_5)>; 1736 def : Pat<(i32 (vector_extract v16i8:$S, 6)), 1737 (i32 VectorExtractions.LE_BYTE_6)>; 1738 def : Pat<(i32 (vector_extract v16i8:$S, 7)), 1739 (i32 VectorExtractions.LE_BYTE_7)>; 1740 def : Pat<(i32 (vector_extract v16i8:$S, 8)), 1741 (i32 VectorExtractions.LE_BYTE_8)>; 1742 def : Pat<(i32 (vector_extract v16i8:$S, 9)), 1743 (i32 VectorExtractions.LE_BYTE_9)>; 1744 def : Pat<(i32 (vector_extract v16i8:$S, 10)), 1745 (i32 VectorExtractions.LE_BYTE_10)>; 1746 def : Pat<(i32 (vector_extract v16i8:$S, 11)), 1747 (i32 VectorExtractions.LE_BYTE_11)>; 1748 def : Pat<(i32 (vector_extract v16i8:$S, 12)), 1749 (i32 VectorExtractions.LE_BYTE_12)>; 1750 def : Pat<(i32 (vector_extract v16i8:$S, 13)), 1751 (i32 VectorExtractions.LE_BYTE_13)>; 1752 def : Pat<(i32 (vector_extract v16i8:$S, 14)), 1753 (i32 VectorExtractions.LE_BYTE_14)>; 1754 def : Pat<(i32 (vector_extract v16i8:$S, 15)), 1755 (i32 VectorExtractions.LE_BYTE_15)>; 1756 def : Pat<(i32 (vector_extract v16i8:$S, i64:$Idx)), 1757 (i32 VectorExtractions.LE_VARIABLE_BYTE)>; 1758 1759 // v8i16 scalar <-> vector conversions (LE) 1760 def : Pat<(i32 (vector_extract v8i16:$S, 0)), 1761 (i32 VectorExtractions.LE_HALF_0)>; 1762 def : Pat<(i32 (vector_extract v8i16:$S, 1)), 1763 (i32 VectorExtractions.LE_HALF_1)>; 1764 def : Pat<(i32 (vector_extract v8i16:$S, 2)), 1765 (i32 VectorExtractions.LE_HALF_2)>; 1766 def : Pat<(i32 (vector_extract v8i16:$S, 3)), 1767 (i32 VectorExtractions.LE_HALF_3)>; 1768 def : Pat<(i32 (vector_extract v8i16:$S, 4)), 1769 (i32 VectorExtractions.LE_HALF_4)>; 1770 def : Pat<(i32 (vector_extract v8i16:$S, 5)), 1771 (i32 VectorExtractions.LE_HALF_5)>; 1772 def : Pat<(i32 (vector_extract v8i16:$S, 6)), 1773 (i32 VectorExtractions.LE_HALF_6)>; 1774 def : Pat<(i32 (vector_extract v8i16:$S, 7)), 1775 (i32 VectorExtractions.LE_HALF_7)>; 1776 def : Pat<(i32 (vector_extract v8i16:$S, i64:$Idx)), 1777 (i32 VectorExtractions.LE_VARIABLE_HALF)>; 1778 1779 // v4i32 scalar <-> vector conversions (LE) 1780 def : Pat<(i32 (vector_extract v4i32:$S, 0)), 1781 (i32 VectorExtractions.LE_WORD_0)>; 1782 def : Pat<(i32 (vector_extract v4i32:$S, 1)), 1783 (i32 VectorExtractions.LE_WORD_1)>; 1784 def : Pat<(i32 (vector_extract v4i32:$S, 2)), 1785 (i32 VectorExtractions.LE_WORD_2)>; 1786 def : Pat<(i32 (vector_extract v4i32:$S, 3)), 1787 (i32 VectorExtractions.LE_WORD_3)>; 1788 def : Pat<(i32 (vector_extract v4i32:$S, i64:$Idx)), 1789 (i32 VectorExtractions.LE_VARIABLE_WORD)>; 1790 1791 // v2i64 scalar <-> vector conversions (LE) 1792 def : Pat<(i64 (vector_extract v2i64:$S, 0)), 1793 (i64 VectorExtractions.LE_DWORD_0)>; 1794 def : Pat<(i64 (vector_extract v2i64:$S, 1)), 1795 (i64 VectorExtractions.LE_DWORD_1)>; 1796 def : Pat<(i64 (vector_extract v2i64:$S, i64:$Idx)), 1797 (i64 VectorExtractions.LE_VARIABLE_DWORD)>; 1798} // IsLittleEndian, HasDirectMove 1799 1800let Predicates = [HasDirectMove, HasVSX] in { 1801// bitconvert f32 -> i32 1802// (convert to 32-bit fp single, shift right 1 word, move to GPR) 1803def : Pat<(i32 (bitconvert f32:$S)), 1804 (i32 (MFVSRWZ (EXTRACT_SUBREG 1805 (XXSLDWI (XSCVDPSPN $S),(XSCVDPSPN $S), 3), 1806 sub_64)))>; 1807// bitconvert i32 -> f32 1808// (move to FPR, shift left 1 word, convert to 64-bit fp single) 1809def : Pat<(f32 (bitconvert i32:$A)), 1810 (f32 (XSCVSPDPN 1811 (XXSLDWI MovesToVSR.LE_WORD_1, MovesToVSR.LE_WORD_1, 1)))>; 1812 1813// bitconvert f64 -> i64 1814// (move to GPR, nothing else needed) 1815def : Pat<(i64 (bitconvert f64:$S)), 1816 (i64 (MFVSRD $S))>; 1817 1818// bitconvert i64 -> f64 1819// (move to FPR, nothing else needed) 1820def : Pat<(f64 (bitconvert i64:$S)), 1821 (f64 (MTVSRD $S))>; 1822} 1823 1824def AlignValues { 1825 dag F32_TO_BE_WORD1 = (v4f32 (XXSLDWI (XSCVDPSPN $B), (XSCVDPSPN $B), 3)); 1826 dag I32_TO_BE_WORD1 = (COPY_TO_REGCLASS (MTVSRWZ $B), VSRC); 1827} 1828 1829// The following VSX instructions were introduced in Power ISA 3.0 1830def HasP9Vector : Predicate<"PPCSubTarget->hasP9Vector()">; 1831let AddedComplexity = 400, Predicates = [HasP9Vector] in { 1832 1833 // [PO VRT XO VRB XO /] 1834 class X_VT5_XO5_VB5<bits<6> opcode, bits<5> xo2, bits<10> xo, string opc, 1835 list<dag> pattern> 1836 : X_RD5_XO5_RS5<opcode, xo2, xo, (outs vrrc:$vT), (ins vrrc:$vB), 1837 !strconcat(opc, " $vT, $vB"), IIC_VecFP, pattern>; 1838 1839 // [PO VRT XO VRB XO RO], Round to Odd version of [PO VRT XO VRB XO /] 1840 class X_VT5_XO5_VB5_Ro<bits<6> opcode, bits<5> xo2, bits<10> xo, string opc, 1841 list<dag> pattern> 1842 : X_VT5_XO5_VB5<opcode, xo2, xo, opc, pattern>, isDOT; 1843 1844 // [PO VRT XO VRB XO /], but the VRB is only used the left 64 bits (or less), 1845 // So we use different operand class for VRB 1846 class X_VT5_XO5_VB5_TyVB<bits<6> opcode, bits<5> xo2, bits<10> xo, string opc, 1847 RegisterOperand vbtype, list<dag> pattern> 1848 : X_RD5_XO5_RS5<opcode, xo2, xo, (outs vrrc:$vT), (ins vbtype:$vB), 1849 !strconcat(opc, " $vT, $vB"), IIC_VecFP, pattern>; 1850 1851 // [PO T XO B XO BX /] 1852 class XX2_RT5_XO5_XB6<bits<6> opcode, bits<5> xo2, bits<9> xo, string opc, 1853 list<dag> pattern> 1854 : XX2_RD5_XO5_RS6<opcode, xo2, xo, (outs g8rc:$rT), (ins vsfrc:$XB), 1855 !strconcat(opc, " $rT, $XB"), IIC_VecFP, pattern>; 1856 1857 // [PO T XO B XO BX TX] 1858 class XX2_XT6_XO5_XB6<bits<6> opcode, bits<5> xo2, bits<9> xo, string opc, 1859 RegisterOperand vtype, list<dag> pattern> 1860 : XX2_RD6_XO5_RS6<opcode, xo2, xo, (outs vtype:$XT), (ins vtype:$XB), 1861 !strconcat(opc, " $XT, $XB"), IIC_VecFP, pattern>; 1862 1863 // [PO T A B XO AX BX TX], src and dest register use different operand class 1864 class XX3_XT5_XA5_XB5<bits<6> opcode, bits<8> xo, string opc, 1865 RegisterOperand xty, RegisterOperand aty, RegisterOperand bty, 1866 InstrItinClass itin, list<dag> pattern> 1867 : XX3Form<opcode, xo, (outs xty:$XT), (ins aty:$XA, bty:$XB), 1868 !strconcat(opc, " $XT, $XA, $XB"), itin, pattern>; 1869 1870 // [PO VRT VRA VRB XO /] 1871 class X_VT5_VA5_VB5<bits<6> opcode, bits<10> xo, string opc, 1872 list<dag> pattern> 1873 : XForm_1<opcode, xo, (outs vrrc:$vT), (ins vrrc:$vA, vrrc:$vB), 1874 !strconcat(opc, " $vT, $vA, $vB"), IIC_VecFP, pattern>; 1875 1876 // [PO VRT VRA VRB XO RO], Round to Odd version of [PO VRT VRA VRB XO /] 1877 class X_VT5_VA5_VB5_Ro<bits<6> opcode, bits<10> xo, string opc, 1878 list<dag> pattern> 1879 : X_VT5_VA5_VB5<opcode, xo, opc, pattern>, isDOT; 1880 1881 //===--------------------------------------------------------------------===// 1882 // Quad-Precision Scalar Move Instructions: 1883 1884 // Copy Sign 1885 def XSCPSGNQP : X_VT5_VA5_VB5<63, 100, "xscpsgnqp", []>; 1886 1887 // Absolute/Negative-Absolute/Negate 1888 def XSABSQP : X_VT5_XO5_VB5<63, 0, 804, "xsabsqp" , []>; 1889 def XSNABSQP : X_VT5_XO5_VB5<63, 8, 804, "xsnabsqp", []>; 1890 def XSNEGQP : X_VT5_XO5_VB5<63, 16, 804, "xsnegqp" , []>; 1891 1892 //===--------------------------------------------------------------------===// 1893 // Quad-Precision Scalar Floating-Point Arithmetic Instructions: 1894 1895 // Add/Divide/Multiply/Subtract 1896 def XSADDQP : X_VT5_VA5_VB5 <63, 4, "xsaddqp" , []>; 1897 def XSADDQPO : X_VT5_VA5_VB5_Ro<63, 4, "xsaddqpo", []>; 1898 def XSDIVQP : X_VT5_VA5_VB5 <63, 548, "xsdivqp" , []>; 1899 def XSDIVQPO : X_VT5_VA5_VB5_Ro<63, 548, "xsdivqpo", []>; 1900 def XSMULQP : X_VT5_VA5_VB5 <63, 36, "xsmulqp" , []>; 1901 def XSMULQPO : X_VT5_VA5_VB5_Ro<63, 36, "xsmulqpo", []>; 1902 def XSSUBQP : X_VT5_VA5_VB5 <63, 516, "xssubqp" , []>; 1903 def XSSUBQPO : X_VT5_VA5_VB5_Ro<63, 516, "xssubqpo", []>; 1904 1905 // Square-Root 1906 def XSSQRTQP : X_VT5_XO5_VB5 <63, 27, 804, "xssqrtqp" , []>; 1907 def XSSQRTQPO : X_VT5_XO5_VB5_Ro<63, 27, 804, "xssqrtqpo", []>; 1908 1909 // (Negative) Multiply-{Add/Subtract} 1910 def XSMADDQP : X_VT5_VA5_VB5 <63, 388, "xsmaddqp" , []>; 1911 def XSMADDQPO : X_VT5_VA5_VB5_Ro<63, 388, "xsmaddqpo" , []>; 1912 def XSMSUBQP : X_VT5_VA5_VB5 <63, 420, "xsmsubqp" , []>; 1913 def XSMSUBQPO : X_VT5_VA5_VB5_Ro<63, 420, "xsmsubqpo" , []>; 1914 def XSNMADDQP : X_VT5_VA5_VB5 <63, 452, "xsnmaddqp" , []>; 1915 def XSNMADDQPO: X_VT5_VA5_VB5_Ro<63, 452, "xsnmaddqpo", []>; 1916 def XSNMSUBQP : X_VT5_VA5_VB5 <63, 484, "xsnmsubqp" , []>; 1917 def XSNMSUBQPO: X_VT5_VA5_VB5_Ro<63, 484, "xsnmsubqpo", []>; 1918 1919 //===--------------------------------------------------------------------===// 1920 // Quad/Double-Precision Compare Instructions: 1921 1922 // [PO BF // VRA VRB XO /] 1923 class X_BF3_VA5_VB5<bits<6> opcode, bits<10> xo, string opc, 1924 list<dag> pattern> 1925 : XForm_17<opcode, xo, (outs crrc:$crD), (ins vrrc:$VA, vrrc:$VB), 1926 !strconcat(opc, " $crD, $VA, $VB"), IIC_FPCompare> { 1927 let Pattern = pattern; 1928 } 1929 1930 // QP Compare Ordered/Unordered 1931 def XSCMPOQP : X_BF3_VA5_VB5<63, 132, "xscmpoqp", []>; 1932 def XSCMPUQP : X_BF3_VA5_VB5<63, 644, "xscmpuqp", []>; 1933 1934 // DP/QP Compare Exponents 1935 def XSCMPEXPDP : XX3Form_1<60, 59, 1936 (outs crrc:$crD), (ins vsfrc:$XA, vsfrc:$XB), 1937 "xscmpexpdp $crD, $XA, $XB", IIC_FPCompare, []>; 1938 def XSCMPEXPQP : X_BF3_VA5_VB5<63, 164, "xscmpexpqp", []>; 1939 1940 // DP Compare ==, >=, >, != 1941 // Use vsrc for XT, because the entire register of XT is set. 1942 // XT.dword[1] = 0x0000_0000_0000_0000 1943 def XSCMPEQDP : XX3_XT5_XA5_XB5<60, 3, "xscmpeqdp", vsrc, vsfrc, vsfrc, 1944 IIC_FPCompare, []>; 1945 def XSCMPGEDP : XX3_XT5_XA5_XB5<60, 19, "xscmpgedp", vsrc, vsfrc, vsfrc, 1946 IIC_FPCompare, []>; 1947 def XSCMPGTDP : XX3_XT5_XA5_XB5<60, 11, "xscmpgtdp", vsrc, vsfrc, vsfrc, 1948 IIC_FPCompare, []>; 1949 def XSCMPNEDP : XX3_XT5_XA5_XB5<60, 27, "xscmpnedp", vsrc, vsfrc, vsfrc, 1950 IIC_FPCompare, []>; 1951 // Vector Compare Not Equal 1952 def XVCMPNEDP : XX3Form_Rc<60, 123, 1953 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB), 1954 "xvcmpnedp $XT, $XA, $XB", IIC_VecFPCompare, []>; 1955 let Defs = [CR6] in 1956 def XVCMPNEDPo : XX3Form_Rc<60, 123, 1957 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB), 1958 "xvcmpnedp. $XT, $XA, $XB", IIC_VecFPCompare, []>, 1959 isDOT; 1960 def XVCMPNESP : XX3Form_Rc<60, 91, 1961 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB), 1962 "xvcmpnesp $XT, $XA, $XB", IIC_VecFPCompare, []>; 1963 let Defs = [CR6] in 1964 def XVCMPNESPo : XX3Form_Rc<60, 91, 1965 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB), 1966 "xvcmpnesp. $XT, $XA, $XB", IIC_VecFPCompare, []>, 1967 isDOT; 1968 1969 //===--------------------------------------------------------------------===// 1970 // Quad-Precision Floating-Point Conversion Instructions: 1971 1972 // Convert DP -> QP 1973 def XSCVDPQP : X_VT5_XO5_VB5_TyVB<63, 22, 836, "xscvdpqp", vsfrc, []>; 1974 1975 // Round & Convert QP -> DP (dword[1] is set to zero) 1976 def XSCVQPDP : X_VT5_XO5_VB5 <63, 20, 836, "xscvqpdp" , []>; 1977 def XSCVQPDPO : X_VT5_XO5_VB5_Ro<63, 20, 836, "xscvqpdpo", []>; 1978 1979 // Truncate & Convert QP -> (Un)Signed (D)Word (dword[1] is set to zero) 1980 def XSCVQPSDZ : X_VT5_XO5_VB5<63, 25, 836, "xscvqpsdz", []>; 1981 def XSCVQPSWZ : X_VT5_XO5_VB5<63, 9, 836, "xscvqpswz", []>; 1982 def XSCVQPUDZ : X_VT5_XO5_VB5<63, 17, 836, "xscvqpudz", []>; 1983 def XSCVQPUWZ : X_VT5_XO5_VB5<63, 1, 836, "xscvqpuwz", []>; 1984 1985 // Convert (Un)Signed DWord -> QP 1986 def XSCVSDQP : X_VT5_XO5_VB5_TyVB<63, 10, 836, "xscvsdqp", vsfrc, []>; 1987 def XSCVUDQP : X_VT5_XO5_VB5_TyVB<63, 2, 836, "xscvudqp", vsfrc, []>; 1988 1989 //===--------------------------------------------------------------------===// 1990 // Round to Floating-Point Integer Instructions 1991 1992 // (Round &) Convert DP <-> HP 1993 // Note! xscvdphp's src and dest register both use the left 64 bits, so we use 1994 // vsfrc for src and dest register. xscvhpdp's src only use the left 16 bits, 1995 // but we still use vsfrc for it. 1996 def XSCVDPHP : XX2_XT6_XO5_XB6<60, 17, 347, "xscvdphp", vsfrc, []>; 1997 def XSCVHPDP : XX2_XT6_XO5_XB6<60, 16, 347, "xscvhpdp", vsfrc, []>; 1998 1999 // Vector HP -> SP 2000 def XVCVHPSP : XX2_XT6_XO5_XB6<60, 24, 475, "xvcvhpsp", vsrc, []>; 2001 def XVCVSPHP : XX2_XT6_XO5_XB6<60, 25, 475, "xvcvsphp", vsrc, []>; 2002 2003 class Z23_VT5_R1_VB5_RMC2_EX1<bits<6> opcode, bits<8> xo, bit ex, string opc, 2004 list<dag> pattern> 2005 : Z23Form_1<opcode, xo, 2006 (outs vrrc:$vT), (ins u1imm:$r, vrrc:$vB, u2imm:$rmc), 2007 !strconcat(opc, " $r, $vT, $vB, $rmc"), IIC_VecFP, pattern> { 2008 let RC = ex; 2009 } 2010 2011 // Round to Quad-Precision Integer [with Inexact] 2012 def XSRQPI : Z23_VT5_R1_VB5_RMC2_EX1<63, 5, 0, "xsrqpi" , []>; 2013 def XSRQPIX : Z23_VT5_R1_VB5_RMC2_EX1<63, 5, 1, "xsrqpix", []>; 2014 2015 // Round Quad-Precision to Double-Extended Precision (fp80) 2016 def XSRQPXP : Z23_VT5_R1_VB5_RMC2_EX1<63, 37, 0, "xsrqpxp", []>; 2017 2018 //===--------------------------------------------------------------------===// 2019 // Insert/Extract Instructions 2020 2021 // Insert Exponent DP/QP 2022 // XT NOTE: XT.dword[1] = 0xUUUU_UUUU_UUUU_UUUU 2023 def XSIEXPDP : XX1Form <60, 918, (outs vsrc:$XT), (ins g8rc:$rA, g8rc:$rB), 2024 "xsiexpdp $XT, $rA, $rB", IIC_VecFP, []>; 2025 // vB NOTE: only vB.dword[0] is used, that's why we don't use 2026 // X_VT5_VA5_VB5 form 2027 def XSIEXPQP : XForm_18<63, 868, (outs vrrc:$vT), (ins vrrc:$vA, vsfrc:$vB), 2028 "xsiexpqp $vT, $vA, $vB", IIC_VecFP, []>; 2029 2030 // Extract Exponent/Significand DP/QP 2031 def XSXEXPDP : XX2_RT5_XO5_XB6<60, 0, 347, "xsxexpdp", []>; 2032 def XSXSIGDP : XX2_RT5_XO5_XB6<60, 1, 347, "xsxsigdp", []>; 2033 def XSXEXPQP : X_VT5_XO5_VB5 <63, 2, 804, "xsxexpqp", []>; 2034 def XSXSIGQP : X_VT5_XO5_VB5 <63, 18, 804, "xsxsigqp", []>; 2035 2036 // Vector Insert Word 2037 // XB NOTE: Only XB.dword[1] is used, but we use vsrc on XB. 2038 def XXINSERTW : 2039 XX2_RD6_UIM5_RS6<60, 181, (outs vsrc:$XT), 2040 (ins vsrc:$XTi, vsrc:$XB, u4imm:$UIM), 2041 "xxinsertw $XT, $XB, $UIM", IIC_VecFP, 2042 [(set v4i32:$XT, (PPCxxinsert v4i32:$XTi, v4i32:$XB, 2043 imm32SExt16:$UIM))]>, 2044 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">; 2045 2046 // Vector Extract Unsigned Word 2047 def XXEXTRACTUW : XX2_RD6_UIM5_RS6<60, 165, 2048 (outs vsfrc:$XT), (ins vsrc:$XB, u4imm:$UIMM), 2049 "xxextractuw $XT, $XB, $UIMM", IIC_VecFP, []>; 2050 2051 // Vector Insert Exponent DP/SP 2052 def XVIEXPDP : XX3_XT5_XA5_XB5<60, 248, "xviexpdp", vsrc, vsrc, vsrc, 2053 IIC_VecFP, []>; 2054 def XVIEXPSP : XX3_XT5_XA5_XB5<60, 216, "xviexpsp", vsrc, vsrc, vsrc, 2055 IIC_VecFP, []>; 2056 2057 // Vector Extract Exponent/Significand DP/SP 2058 def XVXEXPDP : XX2_XT6_XO5_XB6<60, 0, 475, "xvxexpdp", vsrc, []>; 2059 def XVXEXPSP : XX2_XT6_XO5_XB6<60, 8, 475, "xvxexpsp", vsrc, []>; 2060 def XVXSIGDP : XX2_XT6_XO5_XB6<60, 1, 475, "xvxsigdp", vsrc, []>; 2061 def XVXSIGSP : XX2_XT6_XO5_XB6<60, 9, 475, "xvxsigsp", vsrc, []>; 2062 2063 //===--------------------------------------------------------------------===// 2064 2065 // Test Data Class SP/DP/QP 2066 def XSTSTDCSP : XX2_BF3_DCMX7_RS6<60, 298, 2067 (outs crrc:$BF), (ins u7imm:$DCMX, vsfrc:$XB), 2068 "xststdcsp $BF, $XB, $DCMX", IIC_VecFP, []>; 2069 def XSTSTDCDP : XX2_BF3_DCMX7_RS6<60, 362, 2070 (outs crrc:$BF), (ins u7imm:$DCMX, vsfrc:$XB), 2071 "xststdcdp $BF, $XB, $DCMX", IIC_VecFP, []>; 2072 def XSTSTDCQP : X_BF3_DCMX7_RS5 <63, 708, 2073 (outs crrc:$BF), (ins u7imm:$DCMX, vrrc:$vB), 2074 "xststdcqp $BF, $vB, $DCMX", IIC_VecFP, []>; 2075 2076 // Vector Test Data Class SP/DP 2077 def XVTSTDCSP : XX2_RD6_DCMX7_RS6<60, 13, 5, 2078 (outs vsrc:$XT), (ins u7imm:$DCMX, vsrc:$XB), 2079 "xvtstdcsp $XT, $XB, $DCMX", IIC_VecFP, []>; 2080 def XVTSTDCDP : XX2_RD6_DCMX7_RS6<60, 15, 5, 2081 (outs vsrc:$XT), (ins u7imm:$DCMX, vsrc:$XB), 2082 "xvtstdcdp $XT, $XB, $DCMX", IIC_VecFP, []>; 2083 2084 //===--------------------------------------------------------------------===// 2085 2086 // Maximum/Minimum Type-C/Type-J DP 2087 // XT.dword[1] = 0xUUUU_UUUU_UUUU_UUUU, so we use vsrc for XT 2088 def XSMAXCDP : XX3_XT5_XA5_XB5<60, 128, "xsmaxcdp", vsrc, vsfrc, vsfrc, 2089 IIC_VecFP, []>; 2090 def XSMAXJDP : XX3_XT5_XA5_XB5<60, 144, "xsmaxjdp", vsrc, vsfrc, vsfrc, 2091 IIC_VecFP, []>; 2092 def XSMINCDP : XX3_XT5_XA5_XB5<60, 136, "xsmincdp", vsrc, vsfrc, vsfrc, 2093 IIC_VecFP, []>; 2094 def XSMINJDP : XX3_XT5_XA5_XB5<60, 152, "xsminjdp", vsrc, vsfrc, vsfrc, 2095 IIC_VecFP, []>; 2096 2097 //===--------------------------------------------------------------------===// 2098 2099 // Vector Byte-Reverse H/W/D/Q Word 2100 def XXBRH : XX2_XT6_XO5_XB6<60, 7, 475, "xxbrh", vsrc, []>; 2101 def XXBRW : XX2_XT6_XO5_XB6<60, 15, 475, "xxbrw", vsrc, []>; 2102 def XXBRD : XX2_XT6_XO5_XB6<60, 23, 475, "xxbrd", vsrc, []>; 2103 def XXBRQ : XX2_XT6_XO5_XB6<60, 31, 475, "xxbrq", vsrc, []>; 2104 2105 // Vector Permute 2106 def XXPERM : XX3_XT5_XA5_XB5<60, 26, "xxperm" , vsrc, vsrc, vsrc, 2107 IIC_VecPerm, []>; 2108 def XXPERMR : XX3_XT5_XA5_XB5<60, 58, "xxpermr", vsrc, vsrc, vsrc, 2109 IIC_VecPerm, []>; 2110 2111 // Vector Splat Immediate Byte 2112 def XXSPLTIB : X_RD6_IMM8<60, 360, (outs vsrc:$XT), (ins u8imm:$IMM8), 2113 "xxspltib $XT, $IMM8", IIC_VecPerm, []>; 2114 2115 //===--------------------------------------------------------------------===// 2116 // Vector/Scalar Load/Store Instructions 2117 2118 let mayLoad = 1 in { 2119 // Load Vector 2120 def LXV : DQ_RD6_RS5_DQ12<61, 1, (outs vsrc:$XT), (ins memrix16:$src), 2121 "lxv $XT, $src", IIC_LdStLFD, []>; 2122 // Load DWord 2123 def LXSD : DSForm_1<57, 2, (outs vrrc:$vD), (ins memrix:$src), 2124 "lxsd $vD, $src", IIC_LdStLFD, []>; 2125 // Load SP from src, convert it to DP, and place in dword[0] 2126 def LXSSP : DSForm_1<57, 3, (outs vrrc:$vD), (ins memrix:$src), 2127 "lxssp $vD, $src", IIC_LdStLFD, []>; 2128 2129 // [PO T RA RB XO TX] almost equal to [PO S RA RB XO SX], but has different 2130 // "out" and "in" dag 2131 class X_XT6_RA5_RB5<bits<6> opcode, bits<10> xo, string opc, 2132 RegisterOperand vtype, list<dag> pattern> 2133 : XX1Form<opcode, xo, (outs vtype:$XT), (ins memrr:$src), 2134 !strconcat(opc, " $XT, $src"), IIC_LdStLFD, pattern>; 2135 2136 // Load as Integer Byte/Halfword & Zero Indexed 2137 def LXSIBZX : X_XT6_RA5_RB5<31, 781, "lxsibzx", vsfrc, []>; 2138 def LXSIHZX : X_XT6_RA5_RB5<31, 813, "lxsihzx", vsfrc, []>; 2139 2140 // Load Vector Halfword*8/Byte*16 Indexed 2141 def LXVH8X : X_XT6_RA5_RB5<31, 812, "lxvh8x" , vsrc, []>; 2142 def LXVB16X : X_XT6_RA5_RB5<31, 876, "lxvb16x", vsrc, []>; 2143 2144 // Load Vector Indexed 2145 def LXVX : X_XT6_RA5_RB5<31, 268, "lxvx" , vsrc, []>; 2146 2147 // Load Vector (Left-justified) with Length 2148 def LXVL : X_XT6_RA5_RB5<31, 269, "lxvl" , vsrc, []>; 2149 def LXVLL : X_XT6_RA5_RB5<31, 301, "lxvll" , vsrc, []>; 2150 2151 // Load Vector Word & Splat Indexed 2152 def LXVWSX : X_XT6_RA5_RB5<31, 364, "lxvwsx" , vsrc, []>; 2153 } // end mayLoad 2154 2155 let mayStore = 1 in { 2156 // Store Vector 2157 def STXV : DQ_RD6_RS5_DQ12<61, 5, (outs), (ins vsrc:$XT, memrix16:$dst), 2158 "stxv $XT, $dst", IIC_LdStSTFD, []>; 2159 // Store DWord 2160 def STXSD : DSForm_1<61, 2, (outs), (ins vrrc:$vS, memrix:$dst), 2161 "stxsd $vS, $dst", IIC_LdStSTFD, []>; 2162 // Convert DP of dword[0] to SP, and Store to dst 2163 def STXSSP : DSForm_1<61, 3, (outs), (ins vrrc:$vS, memrix:$dst), 2164 "stxssp $vS, $dst", IIC_LdStSTFD, []>; 2165 2166 // [PO S RA RB XO SX] 2167 class X_XS6_RA5_RB5<bits<6> opcode, bits<10> xo, string opc, 2168 RegisterOperand vtype, list<dag> pattern> 2169 : XX1Form<opcode, xo, (outs), (ins vtype:$XT, memrr:$dst), 2170 !strconcat(opc, " $XT, $dst"), IIC_LdStSTFD, pattern>; 2171 2172 // Store as Integer Byte/Halfword Indexed 2173 def STXSIBX : X_XS6_RA5_RB5<31, 909, "stxsibx" , vsfrc, []>; 2174 def STXSIHX : X_XS6_RA5_RB5<31, 941, "stxsihx" , vsfrc, []>; 2175 2176 // Store Vector Halfword*8/Byte*16 Indexed 2177 def STXVH8X : X_XS6_RA5_RB5<31, 940, "stxvh8x" , vsrc, []>; 2178 def STXVB16X : X_XS6_RA5_RB5<31, 1004, "stxvb16x", vsrc, []>; 2179 2180 // Store Vector Indexed 2181 def STXVX : X_XS6_RA5_RB5<31, 396, "stxvx" , vsrc, []>; 2182 2183 // Store Vector (Left-justified) with Length 2184 def STXVL : X_XS6_RA5_RB5<31, 397, "stxvl" , vsrc, []>; 2185 def STXVLL : X_XS6_RA5_RB5<31, 429, "stxvll" , vsrc, []>; 2186 } // end mayStore 2187 2188 // Patterns for which instructions from ISA 3.0 are a better match 2189 let Predicates = [IsLittleEndian, HasP9Vector] in { 2190 def : Pat<(f32 (PPCfcfidus (PPCmtvsrz (i32 (extractelt v4i32:$A, 0))))), 2191 (f32 (XSCVUXDSP (XXEXTRACTUW $A, 12)))>; 2192 def : Pat<(f32 (PPCfcfidus (PPCmtvsrz (i32 (extractelt v4i32:$A, 1))))), 2193 (f32 (XSCVUXDSP (XXEXTRACTUW $A, 8)))>; 2194 def : Pat<(f32 (PPCfcfidus (PPCmtvsrz (i32 (extractelt v4i32:$A, 2))))), 2195 (f32 (XSCVUXDSP (XXEXTRACTUW $A, 4)))>; 2196 def : Pat<(f32 (PPCfcfidus (PPCmtvsrz (i32 (extractelt v4i32:$A, 3))))), 2197 (f32 (XSCVUXDSP (XXEXTRACTUW $A, 0)))>; 2198 def : Pat<(v4i32 (insertelt v4i32:$A, i32:$B, 0)), 2199 (v4i32 (XXINSERTW v4i32:$A, AlignValues.I32_TO_BE_WORD1, 12))>; 2200 def : Pat<(v4i32 (insertelt v4i32:$A, i32:$B, 1)), 2201 (v4i32 (XXINSERTW v4i32:$A, AlignValues.I32_TO_BE_WORD1, 8))>; 2202 def : Pat<(v4i32 (insertelt v4i32:$A, i32:$B, 2)), 2203 (v4i32 (XXINSERTW v4i32:$A, AlignValues.I32_TO_BE_WORD1, 4))>; 2204 def : Pat<(v4i32 (insertelt v4i32:$A, i32:$B, 3)), 2205 (v4i32 (XXINSERTW v4i32:$A, AlignValues.I32_TO_BE_WORD1, 0))>; 2206 def : Pat<(v4f32 (insertelt v4f32:$A, f32:$B, 0)), 2207 (v4f32 (XXINSERTW v4f32:$A, AlignValues.F32_TO_BE_WORD1, 12))>; 2208 def : Pat<(v4f32 (insertelt v4f32:$A, f32:$B, 1)), 2209 (v4f32 (XXINSERTW v4f32:$A, AlignValues.F32_TO_BE_WORD1, 8))>; 2210 def : Pat<(v4f32 (insertelt v4f32:$A, f32:$B, 2)), 2211 (v4f32 (XXINSERTW v4f32:$A, AlignValues.F32_TO_BE_WORD1, 4))>; 2212 def : Pat<(v4f32 (insertelt v4f32:$A, f32:$B, 3)), 2213 (v4f32 (XXINSERTW v4f32:$A, AlignValues.F32_TO_BE_WORD1, 0))>; 2214 } // IsLittleEndian, HasP9Vector 2215 2216 let Predicates = [IsBigEndian, HasP9Vector] in { 2217 def : Pat<(f32 (PPCfcfidus (PPCmtvsrz (i32 (extractelt v4i32:$A, 0))))), 2218 (f32 (XSCVUXDSP (XXEXTRACTUW $A, 0)))>; 2219 def : Pat<(f32 (PPCfcfidus (PPCmtvsrz (i32 (extractelt v4i32:$A, 1))))), 2220 (f32 (XSCVUXDSP (XXEXTRACTUW $A, 4)))>; 2221 def : Pat<(f32 (PPCfcfidus (PPCmtvsrz (i32 (extractelt v4i32:$A, 2))))), 2222 (f32 (XSCVUXDSP (XXEXTRACTUW $A, 8)))>; 2223 def : Pat<(f32 (PPCfcfidus (PPCmtvsrz (i32 (extractelt v4i32:$A, 3))))), 2224 (f32 (XSCVUXDSP (XXEXTRACTUW $A, 12)))>; 2225 def : Pat<(v4i32 (insertelt v4i32:$A, i32:$B, 0)), 2226 (v4i32 (XXINSERTW v4i32:$A, AlignValues.I32_TO_BE_WORD1, 0))>; 2227 def : Pat<(v4i32 (insertelt v4i32:$A, i32:$B, 1)), 2228 (v4i32 (XXINSERTW v4i32:$A, AlignValues.I32_TO_BE_WORD1, 4))>; 2229 def : Pat<(v4i32 (insertelt v4i32:$A, i32:$B, 2)), 2230 (v4i32 (XXINSERTW v4i32:$A, AlignValues.I32_TO_BE_WORD1, 8))>; 2231 def : Pat<(v4i32 (insertelt v4i32:$A, i32:$B, 3)), 2232 (v4i32 (XXINSERTW v4i32:$A, AlignValues.I32_TO_BE_WORD1, 12))>; 2233 def : Pat<(v4f32 (insertelt v4f32:$A, f32:$B, 0)), 2234 (v4f32 (XXINSERTW v4f32:$A, AlignValues.F32_TO_BE_WORD1, 0))>; 2235 def : Pat<(v4f32 (insertelt v4f32:$A, f32:$B, 1)), 2236 (v4f32 (XXINSERTW v4f32:$A, AlignValues.F32_TO_BE_WORD1, 4))>; 2237 def : Pat<(v4f32 (insertelt v4f32:$A, f32:$B, 2)), 2238 (v4f32 (XXINSERTW v4f32:$A, AlignValues.F32_TO_BE_WORD1, 8))>; 2239 def : Pat<(v4f32 (insertelt v4f32:$A, f32:$B, 3)), 2240 (v4f32 (XXINSERTW v4f32:$A, AlignValues.F32_TO_BE_WORD1, 12))>; 2241 } // IsLittleEndian, HasP9Vector 2242} // end HasP9Vector, AddedComplexity 2243