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Searched refs:rcl (Results 1 – 25 of 28) sorted by relevance

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/external/mesa3d/src/gallium/drivers/v3d/
Dv3dx_rcl.c460 cl_emit(&job->rcl, START_ADDRESS_OF_GENERIC_TILE_LIST, branch) { in v3d_rcl_emit_generic_per_tile_list()
486 cl_emit(&job->rcl, TILE_RENDERING_MODE_CFG_Z_STENCIL, zs) { in v3d_emit_z_stencil_config()
523 cl_emit(&job->rcl, MULTICORE_RENDERING_TILE_LIST_SET_BASE, list) { in emit_render_layer()
527 cl_emit(&job->rcl, MULTICORE_RENDERING_SUPERTILE_CFG, config) { in emit_render_layer()
560 cl_emit(&job->rcl, TILE_COORDINATES, coords) { in emit_render_layer()
579 cl_emit(&job->rcl, STORE_TILE_BUFFER_GENERAL, store) { in emit_render_layer()
585 cl_emit(&job->rcl, TILE_COORDINATES, coords); in emit_render_layer()
586 cl_emit(&job->rcl, END_OF_LOADS, end); in emit_render_layer()
587 cl_emit(&job->rcl, STORE_TILE_BUFFER_GENERAL, store) { in emit_render_layer()
591 cl_emit(&job->rcl, CLEAR_TILE_BUFFERS, clear) { in emit_render_layer()
[all …]
Dv3d_job.c80 v3d_destroy_cl(&job->rcl); in v3d_job_free()
96 v3d_init_cl(job, &job->rcl); in v3d_job_create()
521 job->submit.rcl_end = job->rcl.bo->offset + cl_offset(&job->rcl); in v3d_job_submit()
Dv3d_context.h316 struct v3d_cl rcl; member
/external/mesa3d/src/gallium/drivers/vc4/kernel/
Dvc4_render_cl.c45 struct drm_gem_cma_object *rcl; member
51 *(u8 *)(setup->rcl->vaddr + setup->next_offset) = val; in rcl_u8()
57 *(u16 *)(setup->rcl->vaddr + setup->next_offset) = val; in rcl_u16()
63 *(u32 *)(setup->rcl->vaddr + setup->next_offset) = val; in rcl_u32()
325 setup->rcl = drm_gem_cma_create(dev, size); in vc4_create_rcl_bo()
326 if (!setup->rcl) in vc4_create_rcl_bo()
328 list_addtail(&to_vc4_bo(&setup->rcl->base)->unref_head, in vc4_create_rcl_bo()
371 exec->ct1ca = setup->rcl->paddr; in vc4_create_rcl_bo()
372 exec->ct1ea = setup->rcl->paddr + setup->next_offset; in vc4_create_rcl_bo()
/external/mesa3d/src/broadcom/vulkan/
Dv3dv_queue.c574 assert(list_length(&job->rcl.bo_list) == 1); in handle_cl_job()
580 submit.rcl_start = job->rcl.bo->offset; in handle_cl_job()
581 submit.rcl_end = job->rcl.bo->offset + v3dv_cl_offset(&job->rcl); in handle_cl_job()
760 struct v3dv_cl *rcl = &job->rcl; in emit_noop_render() local
761 v3dv_cl_ensure_space_with_branch(rcl, 200 + 1 * 256 * in emit_noop_render()
764 cl_emit(rcl, TILE_RENDERING_MODE_CFG_COMMON, config) { in emit_noop_render()
773 cl_emit(rcl, TILE_RENDERING_MODE_CFG_COLOR, rt) { in emit_noop_render()
779 cl_emit(rcl, TILE_RENDERING_MODE_CFG_ZS_CLEAR_VALUES, clear) { in emit_noop_render()
784 cl_emit(rcl, TILE_LIST_INITIAL_BLOCK_SIZE, init) { in emit_noop_render()
790 cl_emit(rcl, MULTICORE_RENDERING_TILE_LIST_SET_BASE, list) { in emit_noop_render()
[all …]
Dv3dv_meta_clear.c1295 cl_emit(&job->rcl, START_ADDRESS_OF_GENERIC_TILE_LIST, branch) { in emit_tlb_clear_per_tile_rcl()
1311 struct v3dv_cl *rcl = &job->rcl; in emit_tlb_clear_layer_rcl() local
1317 cl_emit(rcl, MULTICORE_RENDERING_TILE_LIST_SET_BASE, list) { in emit_tlb_clear_layer_rcl()
1321 cl_emit(rcl, MULTICORE_RENDERING_SUPERTILE_CFG, config) { in emit_tlb_clear_layer_rcl()
1337 cl_emit(rcl, TILE_COORDINATES, coords); in emit_tlb_clear_layer_rcl()
1338 cl_emit(rcl, END_OF_LOADS, end); in emit_tlb_clear_layer_rcl()
1339 cl_emit(rcl, STORE_TILE_BUFFER_GENERAL, store) { in emit_tlb_clear_layer_rcl()
1343 cl_emit(rcl, CLEAR_TILE_BUFFERS, clear) { in emit_tlb_clear_layer_rcl()
1348 cl_emit(rcl, END_OF_TILE_MARKER, end); in emit_tlb_clear_layer_rcl()
1351 cl_emit(rcl, FLUSH_VCD_CACHE, flush); in emit_tlb_clear_layer_rcl()
[all …]
Dv3dv_meta_copy.c267 struct v3dv_cl *rcl = &job->rcl; in emit_rcl_prologue() local
268 v3dv_cl_ensure_space_with_branch(rcl, 200 + in emit_rcl_prologue()
274 cl_emit(rcl, TILE_RENDERING_MODE_CFG_COMMON, config) { in emit_rcl_prologue()
305 cl_emit(rcl, TILE_RENDERING_MODE_CFG_CLEAR_COLORS_PART1, clear) { in emit_rcl_prologue()
312 cl_emit(rcl, TILE_RENDERING_MODE_CFG_CLEAR_COLORS_PART2, clear) { in emit_rcl_prologue()
322 cl_emit(rcl, TILE_RENDERING_MODE_CFG_CLEAR_COLORS_PART3, clear) { in emit_rcl_prologue()
330 cl_emit(rcl, TILE_RENDERING_MODE_CFG_COLOR, rt) { in emit_rcl_prologue()
336 cl_emit(rcl, TILE_RENDERING_MODE_CFG_ZS_CLEAR_VALUES, clear) { in emit_rcl_prologue()
341 cl_emit(rcl, TILE_LIST_INITIAL_BLOCK_SIZE, init) { in emit_rcl_prologue()
347 return rcl; in emit_rcl_prologue()
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Dv3dv_cmd_buffer.c164 v3dv_cl_destroy(&job->rcl); in job_destroy_gpu_cl_resources()
187 list_for_each_entry_safe(struct v3dv_bo, bo, &job->rcl.bo_list, list_link) { in job_destroy_cloned_gpu_cl_resources()
617 if (v3dv_cl_offset(&cmd_buffer->state.job->rcl) == 0) in cmd_buffer_end_render_pass_frame()
699 assert(v3dv_cl_offset(&job->rcl) != 0 || cmd_buffer->state.pass); in v3dv_cmd_buffer_finish_job()
811 v3dv_cl_init(job, &job->rcl); in v3dv_job_init()
1846 cl_emit(&job->rcl, START_ADDRESS_OF_GENERIC_TILE_LIST, branch) { in cmd_buffer_render_pass_emit_per_tile_rcl()
1859 struct v3dv_cl *rcl = &job->rcl; in cmd_buffer_emit_render_pass_layer_rcl() local
1867 cl_emit(rcl, MULTICORE_RENDERING_TILE_LIST_SET_BASE, list) { in cmd_buffer_emit_render_pass_layer_rcl()
1871 cl_emit(rcl, MULTICORE_RENDERING_SUPERTILE_CFG, config) { in cmd_buffer_emit_render_pass_layer_rcl()
1886 cl_emit(rcl, TILE_COORDINATES, coords) { in cmd_buffer_emit_render_pass_layer_rcl()
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Dv3dv_private.h835 struct v3dv_cl rcl; member
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86InstrShiftRotate.td333 "rcl{b}\t{%cl, $dst|$dst, cl}", []>;
335 "rcl{w}\t{%cl, $dst|$dst, cl}", []>, OpSize16;
337 "rcl{l}\t{%cl, $dst|$dst, cl}", []>, OpSize32;
339 "rcl{q}\t{%cl, $dst|$dst, cl}", []>;
344 "rcl{b}\t$dst", []>;
346 "rcl{b}\t{$cnt, $dst|$dst, $cnt}", []>;
348 "rcl{w}\t$dst", []>, OpSize16;
350 "rcl{w}\t{$cnt, $dst|$dst, $cnt}", []>, OpSize16;
352 "rcl{l}\t$dst", []>, OpSize32;
354 "rcl{l}\t{$cnt, $dst|$dst, $cnt}", []>, OpSize32;
[all …]
/external/llvm/lib/Target/X86/
DX86InstrShiftRotate.td344 "rcl{b}\t$dst", [], IIC_SR>;
346 "rcl{b}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>;
349 "rcl{b}\t{%cl, $dst|$dst, cl}", [], IIC_SR>;
352 "rcl{w}\t$dst", [], IIC_SR>, OpSize16;
354 "rcl{w}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>, OpSize16;
357 "rcl{w}\t{%cl, $dst|$dst, cl}", [], IIC_SR>, OpSize16;
360 "rcl{l}\t$dst", [], IIC_SR>, OpSize32;
362 "rcl{l}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>, OpSize32;
365 "rcl{l}\t{%cl, $dst|$dst, cl}", [], IIC_SR>, OpSize32;
369 "rcl{q}\t$dst", [], IIC_SR>;
[all …]
DX86InstrInfo.td3041 defm : ShiftRotateByOneAlias<"rcl", "RCL">;
/external/llvm-project/llvm/lib/Target/X86/
DX86InstrShiftRotate.td333 "rcl{b}\t{%cl, $dst|$dst, cl}", []>;
335 "rcl{w}\t{%cl, $dst|$dst, cl}", []>, OpSize16;
337 "rcl{l}\t{%cl, $dst|$dst, cl}", []>, OpSize32;
339 "rcl{q}\t{%cl, $dst|$dst, cl}", []>;
344 "rcl{b}\t$dst", []>;
346 "rcl{b}\t{$cnt, $dst|$dst, $cnt}", []>;
348 "rcl{w}\t$dst", []>, OpSize16;
350 "rcl{w}\t{$cnt, $dst|$dst, $cnt}", []>, OpSize16;
352 "rcl{l}\t$dst", []>, OpSize32;
354 "rcl{l}\t{$cnt, $dst|$dst, $cnt}", []>, OpSize32;
[all …]
/external/capstone/arch/X86/
DX86MappingInsnOp_reduce.inc4012 { /* X86_RCL16m1, X86_INS_RCL: rcl{w} $dst, 1 */
4016 { /* X86_RCL16mCL, X86_INS_RCL: rcl{w} $dst, cl */
4020 { /* X86_RCL16mi, X86_INS_RCL: rcl{w} $dst, $cnt */
4024 { /* X86_RCL16r1, X86_INS_RCL: rcl{w} $dst, 1 */
4028 { /* X86_RCL16rCL, X86_INS_RCL: rcl{w} $dst, cl */
4032 { /* X86_RCL16ri, X86_INS_RCL: rcl{w} $dst, $cnt */
4036 { /* X86_RCL32m1, X86_INS_RCL: rcl{l} $dst, 1 */
4040 { /* X86_RCL32mCL, X86_INS_RCL: rcl{l} $dst, cl */
4044 { /* X86_RCL32mi, X86_INS_RCL: rcl{l} $dst, $cnt */
4048 { /* X86_RCL32r1, X86_INS_RCL: rcl{l} $dst, 1 */
[all …]
DX86MappingInsnOp.inc8420 { /* X86_RCL16m1, X86_INS_RCL: rcl{w} $dst, 1 */
8424 { /* X86_RCL16mCL, X86_INS_RCL: rcl{w} $dst, cl */
8428 { /* X86_RCL16mi, X86_INS_RCL: rcl{w} $dst, $cnt */
8432 { /* X86_RCL16r1, X86_INS_RCL: rcl{w} $dst, 1 */
8436 { /* X86_RCL16rCL, X86_INS_RCL: rcl{w} $dst, cl */
8440 { /* X86_RCL16ri, X86_INS_RCL: rcl{w} $dst, $cnt */
8444 { /* X86_RCL32m1, X86_INS_RCL: rcl{l} $dst, 1 */
8448 { /* X86_RCL32mCL, X86_INS_RCL: rcl{l} $dst, cl */
8452 { /* X86_RCL32mi, X86_INS_RCL: rcl{l} $dst, $cnt */
8456 { /* X86_RCL32r1, X86_INS_RCL: rcl{l} $dst, 1 */
[all …]
/external/llvm-project/llvm/lib/Target/ARM/
DARMSchedule.td195 list<int> rcl, SchedWriteRes wr> :
198 let ResourceCycles = !listconcat(wr.ResourceCycles, rcl);
/external/perfetto/protos/perfetto/trace/track_event/
Dchrome_compositor_scheduler_state.proto32 // https://cs.chromium.org/chromium/src/cc/scheduler/scheduler.cc?l=870&rcl=5e15eabc9c0eec8daf94fdf…
/external/openscreen/infra/config/global/
Dcr-buildbucket.cfg98 …# https://cs.chromium.org/chromium/build/scripts/slave/recipes/openscreen.py?rcl=671f9f1c5f5bef8…
/external/llvm/test/MC/X86/
Dx86-64.s356 rcl %bl label
/external/elfutils/libcpu/defs/
Di386483 1101000{w},{mod}010{r_m}:rcl{w} {mod}{r_m}{w}
484 1101001{w},{mod}010{r_m}:rcl{w} %cl,{mod}{r_m}{w}
485 1100000{w},{mod}010{r_m},{imm8}:rcl{w} {imm8},{mod}{r_m}{w}
/external/mesa3d/src/mesa/x86/
Dassyntax.h582 #define RCL_L(a, b) CHOICE(rcll ARG2(a,b), rcll ARG2(a,b), _LTOG rcl ARG2(b,a))
583 #define RCL_W(a, b) CHOICE(rclw ARG2(a,b), rclw ARG2(a,b), _WTOG rcl ARG2(b,a))
1294 #define RCL_L(a, b) rcl L_(b), L_(a)
1295 #define RCL_W(a, b) rcl W_(b), W_(a)
1296 #define RCL_B(a, b) rcl B_(b), B_(a)
/external/llvm-project/llvm/test/MC/X86/
Dx86-64.s352 rcl %bl label
/external/elfutils/tests/
Dtestfile44.expect.bz21testfile44.o: elf32-elf_i386 2 3Disassembly of section .text: 4 5 0 ...
Dtestfile45.expect.bz21testfile45.o: elf64-elf_x86_64 2 3Disassembly of section .text: 4 5 0 ...
/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/X86/
DX86GenAsmMatcher.inc7744 "\003rcl\004rclb\004rcll\004rclq\004rclw\005rcpps\005rcpss\003rcr\004rcr"
24558 { 6607 /* rcl */, X86::RCL16r1, Convert__Reg1_0__Tie0_1_1, AMFBS_None, { MCK_GR16 }, },
24559 { 6607 /* rcl */, X86::RCL32r1, Convert__Reg1_0__Tie0_1_1, AMFBS_None, { MCK_GR32 }, },
24560 { 6607 /* rcl */, X86::RCL64r1, Convert__Reg1_0__Tie0_1_1, AMFBS_None, { MCK_GR64 }, },
24561 { 6607 /* rcl */, X86::RCL8r1, Convert__Reg1_0__Tie0_1_1, AMFBS_None, { MCK_GR8 }, },
24562 { 6607 /* rcl */, X86::RCL16m1, Convert__Mem165_0, AMFBS_None, { MCK_Mem16 }, },
24563 { 6607 /* rcl */, X86::RCL32m1, Convert__Mem325_0, AMFBS_None, { MCK_Mem32 }, },
24564 { 6607 /* rcl */, X86::RCL64m1, Convert__Mem645_0, AMFBS_In64BitMode, { MCK_Mem64 }, },
24565 { 6607 /* rcl */, X86::RCL8m1, Convert__Mem85_0, AMFBS_None, { MCK_Mem8 }, },
24566 { 6607 /* rcl */, X86::RCL16rCL, Convert__Reg1_0__Tie0_1_1, AMFBS_None, { MCK_GR16, MCK_CL }, },
[all …]

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