1 /*
2 * Copyright © 2017 Broadcom
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "util/format/u_format.h"
25 #include "v3d_context.h"
26 #include "v3d_tiling.h"
27 #include "broadcom/common/v3d_macros.h"
28 #include "broadcom/cle/v3dx_pack.h"
29
30 #define PIPE_CLEAR_COLOR_BUFFERS (PIPE_CLEAR_COLOR0 | \
31 PIPE_CLEAR_COLOR1 | \
32 PIPE_CLEAR_COLOR2 | \
33 PIPE_CLEAR_COLOR3) \
34
35 #define PIPE_FIRST_COLOR_BUFFER_BIT (ffs(PIPE_CLEAR_COLOR0) - 1)
36
37 /* The HW queues up the load until the tile coordinates show up, but can only
38 * track one at a time. If we need to do more than one load, then we need to
39 * flush out the previous load by emitting the tile coordinates and doing a
40 * dummy store.
41 */
42 static void
flush_last_load(struct v3d_cl * cl)43 flush_last_load(struct v3d_cl *cl)
44 {
45 if (V3D_VERSION >= 40)
46 return;
47
48 cl_emit(cl, TILE_COORDINATES_IMPLICIT, coords);
49 cl_emit(cl, STORE_TILE_BUFFER_GENERAL, store) {
50 store.buffer_to_store = NONE;
51 }
52 }
53
54 static void
load_general(struct v3d_cl * cl,struct pipe_surface * psurf,int buffer,int layer,uint32_t pipe_bit,uint32_t * loads_pending)55 load_general(struct v3d_cl *cl, struct pipe_surface *psurf, int buffer,
56 int layer, uint32_t pipe_bit, uint32_t *loads_pending)
57 {
58 struct v3d_surface *surf = v3d_surface(psurf);
59 bool separate_stencil = surf->separate_stencil && buffer == STENCIL;
60 if (separate_stencil) {
61 psurf = surf->separate_stencil;
62 surf = v3d_surface(psurf);
63 }
64
65 struct v3d_resource *rsc = v3d_resource(psurf->texture);
66
67 uint32_t layer_offset =
68 v3d_layer_offset(&rsc->base, psurf->u.tex.level,
69 psurf->u.tex.first_layer + layer);
70 cl_emit(cl, LOAD_TILE_BUFFER_GENERAL, load) {
71 load.buffer_to_load = buffer;
72 load.address = cl_address(rsc->bo, layer_offset);
73
74 #if V3D_VERSION >= 40
75 load.memory_format = surf->tiling;
76 if (separate_stencil)
77 load.input_image_format = V3D_OUTPUT_IMAGE_FORMAT_S8;
78 else
79 load.input_image_format = surf->format;
80 load.r_b_swap = surf->swap_rb;
81
82 if (surf->tiling == VC5_TILING_UIF_NO_XOR ||
83 surf->tiling == VC5_TILING_UIF_XOR) {
84 load.height_in_ub_or_stride =
85 surf->padded_height_of_output_image_in_uif_blocks;
86 } else if (surf->tiling == VC5_TILING_RASTER) {
87 struct v3d_resource_slice *slice =
88 &rsc->slices[psurf->u.tex.level];
89 load.height_in_ub_or_stride = slice->stride;
90 }
91
92 if (psurf->texture->nr_samples > 1)
93 load.decimate_mode = V3D_DECIMATE_MODE_ALL_SAMPLES;
94 else
95 load.decimate_mode = V3D_DECIMATE_MODE_SAMPLE_0;
96
97 #else /* V3D_VERSION < 40 */
98 /* Can't do raw ZSTENCIL loads -- need to load/store them to
99 * separate buffers for Z and stencil.
100 */
101 assert(buffer != ZSTENCIL);
102 load.raw_mode = true;
103 load.padded_height_of_output_image_in_uif_blocks =
104 surf->padded_height_of_output_image_in_uif_blocks;
105 #endif /* V3D_VERSION < 40 */
106 }
107
108 *loads_pending &= ~pipe_bit;
109 if (*loads_pending)
110 flush_last_load(cl);
111 }
112
113 static void
store_general(struct v3d_job * job,struct v3d_cl * cl,struct pipe_surface * psurf,int layer,int buffer,int pipe_bit,uint32_t * stores_pending,bool general_color_clear)114 store_general(struct v3d_job *job,
115 struct v3d_cl *cl, struct pipe_surface *psurf,
116 int layer, int buffer, int pipe_bit,
117 uint32_t *stores_pending, bool general_color_clear)
118 {
119 struct v3d_surface *surf = v3d_surface(psurf);
120 bool separate_stencil = surf->separate_stencil && buffer == STENCIL;
121 if (separate_stencil) {
122 psurf = surf->separate_stencil;
123 surf = v3d_surface(psurf);
124 }
125
126 *stores_pending &= ~pipe_bit;
127 bool last_store = !(*stores_pending);
128
129 struct v3d_resource *rsc = v3d_resource(psurf->texture);
130
131 rsc->writes++;
132
133 uint32_t layer_offset =
134 v3d_layer_offset(&rsc->base, psurf->u.tex.level,
135 psurf->u.tex.first_layer + layer);
136 cl_emit(cl, STORE_TILE_BUFFER_GENERAL, store) {
137 store.buffer_to_store = buffer;
138 store.address = cl_address(rsc->bo, layer_offset);
139
140 #if V3D_VERSION >= 40
141 store.clear_buffer_being_stored = false;
142
143 if (separate_stencil)
144 store.output_image_format = V3D_OUTPUT_IMAGE_FORMAT_S8;
145 else
146 store.output_image_format = surf->format;
147
148 store.r_b_swap = surf->swap_rb;
149 store.memory_format = surf->tiling;
150
151 if (surf->tiling == VC5_TILING_UIF_NO_XOR ||
152 surf->tiling == VC5_TILING_UIF_XOR) {
153 store.height_in_ub_or_stride =
154 surf->padded_height_of_output_image_in_uif_blocks;
155 } else if (surf->tiling == VC5_TILING_RASTER) {
156 struct v3d_resource_slice *slice =
157 &rsc->slices[psurf->u.tex.level];
158 store.height_in_ub_or_stride = slice->stride;
159 }
160
161 if (psurf->texture->nr_samples > 1)
162 store.decimate_mode = V3D_DECIMATE_MODE_ALL_SAMPLES;
163 else
164 store.decimate_mode = V3D_DECIMATE_MODE_SAMPLE_0;
165
166 #else /* V3D_VERSION < 40 */
167 /* Can't do raw ZSTENCIL stores -- need to load/store them to
168 * separate buffers for Z and stencil.
169 */
170 assert(buffer != ZSTENCIL);
171 store.raw_mode = true;
172 if (!last_store) {
173 store.disable_color_buffers_clear_on_write = true;
174 store.disable_z_buffer_clear_on_write = true;
175 store.disable_stencil_buffer_clear_on_write = true;
176 } else {
177 store.disable_color_buffers_clear_on_write =
178 !(((pipe_bit & PIPE_CLEAR_COLOR_BUFFERS) &&
179 general_color_clear &&
180 (job->clear & pipe_bit)));
181 store.disable_z_buffer_clear_on_write =
182 !(job->clear & PIPE_CLEAR_DEPTH);
183 store.disable_stencil_buffer_clear_on_write =
184 !(job->clear & PIPE_CLEAR_STENCIL);
185 }
186 store.padded_height_of_output_image_in_uif_blocks =
187 surf->padded_height_of_output_image_in_uif_blocks;
188 #endif /* V3D_VERSION < 40 */
189 }
190
191 /* There must be a TILE_COORDINATES_IMPLICIT between each store. */
192 if (V3D_VERSION < 40 && !last_store) {
193 cl_emit(cl, TILE_COORDINATES_IMPLICIT, coords);
194 }
195 }
196
197 static int
zs_buffer_from_pipe_bits(int pipe_clear_bits)198 zs_buffer_from_pipe_bits(int pipe_clear_bits)
199 {
200 switch (pipe_clear_bits & PIPE_CLEAR_DEPTHSTENCIL) {
201 case PIPE_CLEAR_DEPTHSTENCIL:
202 return ZSTENCIL;
203 case PIPE_CLEAR_DEPTH:
204 return Z;
205 case PIPE_CLEAR_STENCIL:
206 return STENCIL;
207 default:
208 return NONE;
209 }
210 }
211
212 static void
v3d_rcl_emit_loads(struct v3d_job * job,struct v3d_cl * cl,int layer)213 v3d_rcl_emit_loads(struct v3d_job *job, struct v3d_cl *cl, int layer)
214 {
215 uint32_t loads_pending = job->load;
216
217 for (int i = 0; i < V3D_MAX_DRAW_BUFFERS; i++) {
218 uint32_t bit = PIPE_CLEAR_COLOR0 << i;
219 if (!(loads_pending & bit))
220 continue;
221
222 struct pipe_surface *psurf = job->cbufs[i];
223 if (!psurf || (V3D_VERSION < 40 &&
224 psurf->texture->nr_samples <= 1)) {
225 continue;
226 }
227
228 load_general(cl, psurf, RENDER_TARGET_0 + i, layer,
229 bit, &loads_pending);
230 }
231
232 if ((loads_pending & PIPE_CLEAR_DEPTHSTENCIL) &&
233 (V3D_VERSION >= 40 ||
234 (job->zsbuf && job->zsbuf->texture->nr_samples > 1))) {
235 struct v3d_resource *rsc = v3d_resource(job->zsbuf->texture);
236
237 if (rsc->separate_stencil &&
238 (loads_pending & PIPE_CLEAR_STENCIL)) {
239 load_general(cl, job->zsbuf,
240 STENCIL, layer,
241 PIPE_CLEAR_STENCIL,
242 &loads_pending);
243 }
244
245 if (loads_pending & PIPE_CLEAR_DEPTHSTENCIL) {
246 load_general(cl, job->zsbuf,
247 zs_buffer_from_pipe_bits(loads_pending),
248 layer,
249 loads_pending & PIPE_CLEAR_DEPTHSTENCIL,
250 &loads_pending);
251 }
252 }
253
254 #if V3D_VERSION < 40
255 /* The initial reload will be queued until we get the
256 * tile coordinates.
257 */
258 if (loads_pending) {
259 cl_emit(cl, RELOAD_TILE_COLOR_BUFFER, load) {
260 load.disable_color_buffer_load =
261 (~loads_pending &
262 PIPE_CLEAR_COLOR_BUFFERS) >>
263 PIPE_FIRST_COLOR_BUFFER_BIT;
264 load.enable_z_load =
265 loads_pending & PIPE_CLEAR_DEPTH;
266 load.enable_stencil_load =
267 loads_pending & PIPE_CLEAR_STENCIL;
268 }
269 }
270 #else /* V3D_VERSION >= 40 */
271 assert(!loads_pending);
272 cl_emit(cl, END_OF_LOADS, end);
273 #endif
274 }
275
276 static void
v3d_rcl_emit_stores(struct v3d_job * job,struct v3d_cl * cl,int layer)277 v3d_rcl_emit_stores(struct v3d_job *job, struct v3d_cl *cl, int layer)
278 {
279 #if V3D_VERSION < 40
280 UNUSED bool needs_color_clear = job->clear & PIPE_CLEAR_COLOR_BUFFERS;
281 UNUSED bool needs_z_clear = job->clear & PIPE_CLEAR_DEPTH;
282 UNUSED bool needs_s_clear = job->clear & PIPE_CLEAR_STENCIL;
283
284 /* For clearing color in a TLB general on V3D 3.3:
285 *
286 * - NONE buffer store clears all TLB color buffers.
287 * - color buffer store clears just the TLB color buffer being stored.
288 * - Z/S buffers store may not clear the TLB color buffer.
289 *
290 * And on V3D 4.1, we only have one flag for "clear the buffer being
291 * stored" in the general packet, and a separate packet to clear all
292 * color TLB buffers.
293 *
294 * As a result, we only bother flagging TLB color clears in a general
295 * packet when we don't have to emit a separate packet to clear all
296 * TLB color buffers.
297 */
298 bool general_color_clear = (needs_color_clear &&
299 (job->clear & PIPE_CLEAR_COLOR_BUFFERS) ==
300 (job->store & PIPE_CLEAR_COLOR_BUFFERS));
301 #else
302 bool general_color_clear = false;
303 #endif
304
305 uint32_t stores_pending = job->store;
306
307 /* For V3D 4.1, use general stores for all TLB stores.
308 *
309 * For V3D 3.3, we only use general stores to do raw stores for any
310 * MSAA surfaces. These output UIF tiled images where each 4x MSAA
311 * pixel is a 2x2 quad, and the format will be that of the
312 * internal_type/internal_bpp, rather than the format from GL's
313 * perspective. Non-MSAA surfaces will use
314 * STORE_MULTI_SAMPLE_RESOLVED_TILE_COLOR_BUFFER_EXTENDED.
315 */
316 for (int i = 0; i < V3D_MAX_DRAW_BUFFERS; i++) {
317 uint32_t bit = PIPE_CLEAR_COLOR0 << i;
318 if (!(job->store & bit))
319 continue;
320
321 struct pipe_surface *psurf = job->cbufs[i];
322 if (!psurf ||
323 (V3D_VERSION < 40 && psurf->texture->nr_samples <= 1)) {
324 continue;
325 }
326
327 store_general(job, cl, psurf, layer, RENDER_TARGET_0 + i, bit,
328 &stores_pending, general_color_clear);
329 }
330
331 if (job->store & PIPE_CLEAR_DEPTHSTENCIL && job->zsbuf &&
332 !(V3D_VERSION < 40 && job->zsbuf->texture->nr_samples <= 1)) {
333 struct v3d_resource *rsc = v3d_resource(job->zsbuf->texture);
334 if (rsc->separate_stencil) {
335 if (job->store & PIPE_CLEAR_DEPTH) {
336 store_general(job, cl, job->zsbuf, layer,
337 Z, PIPE_CLEAR_DEPTH,
338 &stores_pending,
339 general_color_clear);
340 }
341
342 if (job->store & PIPE_CLEAR_STENCIL) {
343 store_general(job, cl, job->zsbuf, layer,
344 STENCIL, PIPE_CLEAR_STENCIL,
345 &stores_pending,
346 general_color_clear);
347 }
348 } else {
349 store_general(job, cl, job->zsbuf, layer,
350 zs_buffer_from_pipe_bits(job->store),
351 job->store & PIPE_CLEAR_DEPTHSTENCIL,
352 &stores_pending, general_color_clear);
353 }
354 }
355
356 #if V3D_VERSION < 40
357 if (stores_pending) {
358 cl_emit(cl, STORE_MULTI_SAMPLE_RESOLVED_TILE_COLOR_BUFFER_EXTENDED, store) {
359
360 store.disable_color_buffer_write =
361 (~stores_pending >>
362 PIPE_FIRST_COLOR_BUFFER_BIT) & 0xf;
363 store.enable_z_write = stores_pending & PIPE_CLEAR_DEPTH;
364 store.enable_stencil_write = stores_pending & PIPE_CLEAR_STENCIL;
365
366 /* Note that when set this will clear all of the color
367 * buffers.
368 */
369 store.disable_color_buffers_clear_on_write =
370 !needs_color_clear;
371 store.disable_z_buffer_clear_on_write =
372 !needs_z_clear;
373 store.disable_stencil_buffer_clear_on_write =
374 !needs_s_clear;
375 };
376 } else if (needs_color_clear && !general_color_clear) {
377 /* If we didn't do our color clears in the general packet,
378 * then emit a packet to clear all the TLB color buffers now.
379 */
380 cl_emit(cl, STORE_TILE_BUFFER_GENERAL, store) {
381 store.buffer_to_store = NONE;
382 }
383 }
384 #else /* V3D_VERSION >= 40 */
385 /* If we're emitting an RCL with GL_ARB_framebuffer_no_attachments,
386 * we still need to emit some sort of store.
387 */
388 if (!job->store) {
389 cl_emit(cl, STORE_TILE_BUFFER_GENERAL, store) {
390 store.buffer_to_store = NONE;
391 }
392 }
393
394 assert(!stores_pending);
395
396 /* GFXH-1461/GFXH-1689: The per-buffer store command's clear
397 * buffer bit is broken for depth/stencil. In addition, the
398 * clear packet's Z/S bit is broken, but the RTs bit ends up
399 * clearing Z/S.
400 */
401 if (job->clear) {
402 cl_emit(cl, CLEAR_TILE_BUFFERS, clear) {
403 clear.clear_z_stencil_buffer = true;
404 clear.clear_all_render_targets = true;
405 }
406 }
407 #endif /* V3D_VERSION >= 40 */
408 }
409
410 static void
v3d_rcl_emit_generic_per_tile_list(struct v3d_job * job,int layer)411 v3d_rcl_emit_generic_per_tile_list(struct v3d_job *job, int layer)
412 {
413 /* Emit the generic list in our indirect state -- the rcl will just
414 * have pointers into it.
415 */
416 struct v3d_cl *cl = &job->indirect;
417 v3d_cl_ensure_space(cl, 200, 1);
418 struct v3d_cl_reloc tile_list_start = cl_get_address(cl);
419
420 if (V3D_VERSION >= 40) {
421 /* V3D 4.x only requires a single tile coordinates, and
422 * END_OF_LOADS switches us between loading and rendering.
423 */
424 cl_emit(cl, TILE_COORDINATES_IMPLICIT, coords);
425 }
426
427 v3d_rcl_emit_loads(job, cl, layer);
428
429 if (V3D_VERSION < 40) {
430 /* Tile Coordinates triggers the last reload and sets where
431 * the stores go. There must be one per store packet.
432 */
433 cl_emit(cl, TILE_COORDINATES_IMPLICIT, coords);
434 }
435
436 /* The binner starts out writing tiles assuming that the initial mode
437 * is triangles, so make sure that's the case.
438 */
439 cl_emit(cl, PRIM_LIST_FORMAT, fmt) {
440 fmt.primitive_type = LIST_TRIANGLES;
441 }
442
443 #if V3D_VERSION >= 41
444 /* PTB assumes that value to be 0, but hw will not set it. */
445 cl_emit(cl, SET_INSTANCEID, set) {
446 set.instance_id = 0;
447 }
448 #endif
449
450 cl_emit(cl, BRANCH_TO_IMPLICIT_TILE_LIST, branch);
451
452 v3d_rcl_emit_stores(job, cl, layer);
453
454 #if V3D_VERSION >= 40
455 cl_emit(cl, END_OF_TILE_MARKER, end);
456 #endif
457
458 cl_emit(cl, RETURN_FROM_SUB_LIST, ret);
459
460 cl_emit(&job->rcl, START_ADDRESS_OF_GENERIC_TILE_LIST, branch) {
461 branch.start = tile_list_start;
462 branch.end = cl_get_address(cl);
463 }
464 }
465
466 #if V3D_VERSION >= 40
467 static void
v3d_setup_render_target(struct v3d_job * job,int cbuf,uint32_t * rt_bpp,uint32_t * rt_type,uint32_t * rt_clamp)468 v3d_setup_render_target(struct v3d_job *job, int cbuf,
469 uint32_t *rt_bpp, uint32_t *rt_type, uint32_t *rt_clamp)
470 {
471 if (!job->cbufs[cbuf])
472 return;
473
474 struct v3d_surface *surf = v3d_surface(job->cbufs[cbuf]);
475 *rt_bpp = surf->internal_bpp;
476 *rt_type = surf->internal_type;
477 *rt_clamp = V3D_RENDER_TARGET_CLAMP_NONE;
478 }
479
480 #else /* V3D_VERSION < 40 */
481
482 static void
v3d_emit_z_stencil_config(struct v3d_job * job,struct v3d_surface * surf,struct v3d_resource * rsc,bool is_separate_stencil)483 v3d_emit_z_stencil_config(struct v3d_job *job, struct v3d_surface *surf,
484 struct v3d_resource *rsc, bool is_separate_stencil)
485 {
486 cl_emit(&job->rcl, TILE_RENDERING_MODE_CFG_Z_STENCIL, zs) {
487 zs.address = cl_address(rsc->bo, surf->offset);
488
489 if (!is_separate_stencil) {
490 zs.internal_type = surf->internal_type;
491 zs.output_image_format = surf->format;
492 } else {
493 zs.z_stencil_id = 1; /* Separate stencil */
494 }
495
496 zs.padded_height_of_output_image_in_uif_blocks =
497 surf->padded_height_of_output_image_in_uif_blocks;
498
499 assert(surf->tiling != VC5_TILING_RASTER);
500 zs.memory_format = surf->tiling;
501 }
502
503 if (job->store & (is_separate_stencil ?
504 PIPE_CLEAR_STENCIL :
505 PIPE_CLEAR_DEPTHSTENCIL)) {
506 rsc->writes++;
507 }
508 }
509 #endif /* V3D_VERSION < 40 */
510
511 #define div_round_up(a, b) (((a) + (b) - 1) / b)
512
513 static void
emit_render_layer(struct v3d_job * job,uint32_t layer)514 emit_render_layer(struct v3d_job *job, uint32_t layer)
515 {
516 uint32_t supertile_w = 1, supertile_h = 1;
517
518 /* If doing multicore binning, we would need to initialize each
519 * core's tile list here.
520 */
521 uint32_t tile_alloc_offset =
522 layer * job->draw_tiles_x * job->draw_tiles_y * 64;
523 cl_emit(&job->rcl, MULTICORE_RENDERING_TILE_LIST_SET_BASE, list) {
524 list.address = cl_address(job->tile_alloc, tile_alloc_offset);
525 }
526
527 cl_emit(&job->rcl, MULTICORE_RENDERING_SUPERTILE_CFG, config) {
528 uint32_t frame_w_in_supertiles, frame_h_in_supertiles;
529 const uint32_t max_supertiles = 256;
530
531 /* Size up our supertiles until we get under the limit. */
532 for (;;) {
533 frame_w_in_supertiles = div_round_up(job->draw_tiles_x,
534 supertile_w);
535 frame_h_in_supertiles = div_round_up(job->draw_tiles_y,
536 supertile_h);
537 if (frame_w_in_supertiles *
538 frame_h_in_supertiles < max_supertiles) {
539 break;
540 }
541
542 if (supertile_w < supertile_h)
543 supertile_w++;
544 else
545 supertile_h++;
546 }
547
548 config.number_of_bin_tile_lists = 1;
549 config.total_frame_width_in_tiles = job->draw_tiles_x;
550 config.total_frame_height_in_tiles = job->draw_tiles_y;
551
552 config.supertile_width_in_tiles = supertile_w;
553 config.supertile_height_in_tiles = supertile_h;
554
555 config.total_frame_width_in_supertiles = frame_w_in_supertiles;
556 config.total_frame_height_in_supertiles = frame_h_in_supertiles;
557 }
558
559 /* Start by clearing the tile buffer. */
560 cl_emit(&job->rcl, TILE_COORDINATES, coords) {
561 coords.tile_column_number = 0;
562 coords.tile_row_number = 0;
563 }
564
565 /* Emit an initial clear of the tile buffers. This is necessary
566 * for any buffers that should be cleared (since clearing
567 * normally happens at the *end* of the generic tile list), but
568 * it's also nice to clear everything so the first tile doesn't
569 * inherit any contents from some previous frame.
570 *
571 * Also, implement the GFXH-1742 workaround. There's a race in
572 * the HW between the RCL updating the TLB's internal type/size
573 * and thespawning of the QPU instances using the TLB's current
574 * internal type/size. To make sure the QPUs get the right
575 * state, we need 1 dummy store in between internal type/size
576 * changes on V3D 3.x, and 2 dummy stores on 4.x.
577 */
578 #if V3D_VERSION < 40
579 cl_emit(&job->rcl, STORE_TILE_BUFFER_GENERAL, store) {
580 store.buffer_to_store = NONE;
581 }
582 #else
583 for (int i = 0; i < 2; i++) {
584 if (i > 0)
585 cl_emit(&job->rcl, TILE_COORDINATES, coords);
586 cl_emit(&job->rcl, END_OF_LOADS, end);
587 cl_emit(&job->rcl, STORE_TILE_BUFFER_GENERAL, store) {
588 store.buffer_to_store = NONE;
589 }
590 if (i == 0) {
591 cl_emit(&job->rcl, CLEAR_TILE_BUFFERS, clear) {
592 clear.clear_z_stencil_buffer = true;
593 clear.clear_all_render_targets = true;
594 }
595 }
596 cl_emit(&job->rcl, END_OF_TILE_MARKER, end);
597 }
598 #endif
599
600 cl_emit(&job->rcl, FLUSH_VCD_CACHE, flush);
601
602 v3d_rcl_emit_generic_per_tile_list(job, layer);
603
604 /* XXX perf: We should expose GL_MESA_tile_raster_order to
605 * improve X11 performance, but we should use Morton order
606 * otherwise to improve cache locality.
607 */
608 uint32_t supertile_w_in_pixels = job->tile_width * supertile_w;
609 uint32_t supertile_h_in_pixels = job->tile_height * supertile_h;
610 uint32_t min_x_supertile = job->draw_min_x / supertile_w_in_pixels;
611 uint32_t min_y_supertile = job->draw_min_y / supertile_h_in_pixels;
612
613 uint32_t max_x_supertile = 0;
614 uint32_t max_y_supertile = 0;
615 if (job->draw_max_x != 0 && job->draw_max_y != 0) {
616 max_x_supertile = (job->draw_max_x - 1) / supertile_w_in_pixels;
617 max_y_supertile = (job->draw_max_y - 1) / supertile_h_in_pixels;
618 }
619
620 for (int y = min_y_supertile; y <= max_y_supertile; y++) {
621 for (int x = min_x_supertile; x <= max_x_supertile; x++) {
622 cl_emit(&job->rcl, SUPERTILE_COORDINATES, coords) {
623 coords.column_number_in_supertiles = x;
624 coords.row_number_in_supertiles = y;
625 }
626 }
627 }
628 }
629
630 void
v3dX(emit_rcl)631 v3dX(emit_rcl)(struct v3d_job *job)
632 {
633 /* The RCL list should be empty. */
634 assert(!job->rcl.bo);
635
636 v3d_cl_ensure_space_with_branch(&job->rcl, 200 +
637 MAX2(job->num_layers, 1) * 256 *
638 cl_packet_length(SUPERTILE_COORDINATES));
639 job->submit.rcl_start = job->rcl.bo->offset;
640 v3d_job_add_bo(job, job->rcl.bo);
641
642 int nr_cbufs = 0;
643 for (int i = 0; i < V3D_MAX_DRAW_BUFFERS; i++) {
644 if (job->cbufs[i])
645 nr_cbufs = i + 1;
646 }
647
648 /* Comon config must be the first TILE_RENDERING_MODE_CFG
649 * and Z_STENCIL_CLEAR_VALUES must be last. The ones in between are
650 * optional updates to the previous HW state.
651 */
652 cl_emit(&job->rcl, TILE_RENDERING_MODE_CFG_COMMON, config) {
653 #if V3D_VERSION < 40
654 config.enable_z_store = job->store & PIPE_CLEAR_DEPTH;
655 config.enable_stencil_store = job->store & PIPE_CLEAR_STENCIL;
656 #else /* V3D_VERSION >= 40 */
657 if (job->zsbuf) {
658 struct v3d_surface *surf = v3d_surface(job->zsbuf);
659 config.internal_depth_type = surf->internal_type;
660 }
661 #endif /* V3D_VERSION >= 40 */
662
663 /* XXX: Early D/S clear */
664
665 switch (job->first_ez_state) {
666 case VC5_EZ_UNDECIDED:
667 case VC5_EZ_LT_LE:
668 config.early_z_disable = false;
669 config.early_z_test_and_update_direction =
670 EARLY_Z_DIRECTION_LT_LE;
671 break;
672 case VC5_EZ_GT_GE:
673 config.early_z_disable = false;
674 config.early_z_test_and_update_direction =
675 EARLY_Z_DIRECTION_GT_GE;
676 break;
677 case VC5_EZ_DISABLED:
678 config.early_z_disable = true;
679 }
680
681 config.image_width_pixels = job->draw_width;
682 config.image_height_pixels = job->draw_height;
683
684 config.number_of_render_targets = MAX2(nr_cbufs, 1);
685
686 config.multisample_mode_4x = job->msaa;
687
688 config.maximum_bpp_of_all_render_targets = job->internal_bpp;
689 }
690
691 for (int i = 0; i < nr_cbufs; i++) {
692 struct pipe_surface *psurf = job->cbufs[i];
693 if (!psurf)
694 continue;
695 struct v3d_surface *surf = v3d_surface(psurf);
696 struct v3d_resource *rsc = v3d_resource(psurf->texture);
697
698 UNUSED uint32_t config_pad = 0;
699 uint32_t clear_pad = 0;
700
701 /* XXX: Set the pad for raster. */
702 if (surf->tiling == VC5_TILING_UIF_NO_XOR ||
703 surf->tiling == VC5_TILING_UIF_XOR) {
704 int uif_block_height = v3d_utile_height(rsc->cpp) * 2;
705 uint32_t implicit_padded_height = (align(job->draw_height, uif_block_height) /
706 uif_block_height);
707 if (surf->padded_height_of_output_image_in_uif_blocks -
708 implicit_padded_height < 15) {
709 config_pad = (surf->padded_height_of_output_image_in_uif_blocks -
710 implicit_padded_height);
711 } else {
712 config_pad = 15;
713 clear_pad = surf->padded_height_of_output_image_in_uif_blocks;
714 }
715 }
716
717 #if V3D_VERSION < 40
718 cl_emit(&job->rcl, TILE_RENDERING_MODE_CFG_COLOR, rt) {
719 rt.address = cl_address(rsc->bo, surf->offset);
720 rt.internal_type = surf->internal_type;
721 rt.output_image_format = surf->format;
722 rt.memory_format = surf->tiling;
723 rt.internal_bpp = surf->internal_bpp;
724 rt.render_target_number = i;
725 rt.pad = config_pad;
726
727 if (job->store & PIPE_CLEAR_COLOR0 << i)
728 rsc->writes++;
729 }
730 #endif /* V3D_VERSION < 40 */
731
732 cl_emit(&job->rcl, TILE_RENDERING_MODE_CFG_CLEAR_COLORS_PART1,
733 clear) {
734 clear.clear_color_low_32_bits = job->clear_color[i][0];
735 clear.clear_color_next_24_bits = job->clear_color[i][1] & 0xffffff;
736 clear.render_target_number = i;
737 };
738
739 if (surf->internal_bpp >= V3D_INTERNAL_BPP_64) {
740 cl_emit(&job->rcl, TILE_RENDERING_MODE_CFG_CLEAR_COLORS_PART2,
741 clear) {
742 clear.clear_color_mid_low_32_bits =
743 ((job->clear_color[i][1] >> 24) |
744 (job->clear_color[i][2] << 8));
745 clear.clear_color_mid_high_24_bits =
746 ((job->clear_color[i][2] >> 24) |
747 ((job->clear_color[i][3] & 0xffff) << 8));
748 clear.render_target_number = i;
749 };
750 }
751
752 if (surf->internal_bpp >= V3D_INTERNAL_BPP_128 || clear_pad) {
753 cl_emit(&job->rcl, TILE_RENDERING_MODE_CFG_CLEAR_COLORS_PART3,
754 clear) {
755 clear.uif_padded_height_in_uif_blocks = clear_pad;
756 clear.clear_color_high_16_bits = job->clear_color[i][3] >> 16;
757 clear.render_target_number = i;
758 };
759 }
760 }
761
762 #if V3D_VERSION >= 40
763 cl_emit(&job->rcl, TILE_RENDERING_MODE_CFG_COLOR, rt) {
764 v3d_setup_render_target(job, 0,
765 &rt.render_target_0_internal_bpp,
766 &rt.render_target_0_internal_type,
767 &rt.render_target_0_clamp);
768 v3d_setup_render_target(job, 1,
769 &rt.render_target_1_internal_bpp,
770 &rt.render_target_1_internal_type,
771 &rt.render_target_1_clamp);
772 v3d_setup_render_target(job, 2,
773 &rt.render_target_2_internal_bpp,
774 &rt.render_target_2_internal_type,
775 &rt.render_target_2_clamp);
776 v3d_setup_render_target(job, 3,
777 &rt.render_target_3_internal_bpp,
778 &rt.render_target_3_internal_type,
779 &rt.render_target_3_clamp);
780 }
781 #endif
782
783 #if V3D_VERSION < 40
784 /* TODO: Don't bother emitting if we don't load/clear Z/S. */
785 if (job->zsbuf) {
786 struct pipe_surface *psurf = job->zsbuf;
787 struct v3d_surface *surf = v3d_surface(psurf);
788 struct v3d_resource *rsc = v3d_resource(psurf->texture);
789
790 v3d_emit_z_stencil_config(job, surf, rsc, false);
791
792 /* Emit the separate stencil packet if we have a resource for
793 * it. The HW will only load/store this buffer if the
794 * Z/Stencil config doesn't have stencil in its format.
795 */
796 if (surf->separate_stencil) {
797 v3d_emit_z_stencil_config(job,
798 v3d_surface(surf->separate_stencil),
799 rsc->separate_stencil, true);
800 }
801 }
802 #endif /* V3D_VERSION < 40 */
803
804 /* Ends rendering mode config. */
805 cl_emit(&job->rcl, TILE_RENDERING_MODE_CFG_ZS_CLEAR_VALUES,
806 clear) {
807 clear.z_clear_value = job->clear_z;
808 clear.stencil_clear_value = job->clear_s;
809 };
810
811 /* Always set initial block size before the first branch, which needs
812 * to match the value from binning mode config.
813 */
814 cl_emit(&job->rcl, TILE_LIST_INITIAL_BLOCK_SIZE, init) {
815 init.use_auto_chained_tile_lists = true;
816 init.size_of_first_block_in_chained_tile_lists =
817 TILE_ALLOCATION_BLOCK_SIZE_64B;
818 }
819
820 /* ARB_framebuffer_no_attachments allows rendering to happen even when
821 * the framebuffer has no attachments, the idea being that fragment
822 * shaders can still do image load/store, ssbo, etc without having to
823 * write to actual attachments, so always run at least one iteration
824 * of the loop.
825 */
826 assert(job->num_layers > 0 || (job->load == 0 && job->store == 0));
827 for (int layer = 0; layer < MAX2(1, job->num_layers); layer++)
828 emit_render_layer(job, layer);
829
830 cl_emit(&job->rcl, END_OF_RENDERING, end);
831 }
832