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Searched refs:rdvl (Results 1 – 25 of 26) sorted by relevance

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/external/llvm-project/llvm/test/MC/AArch64/SVE/
Drdvl.s10 rdvl x0, #0 label
16 rdvl xzr, #-1 label
22 rdvl x23, #31 label
28 rdvl x21, #-32 label
Drdvl-diagnostics.s4 rdvl x9, #32 label
10 rdvl x9, x10 label
/external/llvm-project/llvm/test/CodeGen/AArch64/
Dsve-vscale.ll13 ; CHECK: rdvl x0, #1
22 ; CHECK: rdvl x0, #1
31 ; CHECK: rdvl x0, #1
40 ; CHECK: rdvl x0, #1
49 ; CHECK: rdvl x0, #1
57 ; CHECK: rdvl [[TMP:x[0-9]+]], #1
66 ; CHECK: rdvl [[TMP:x[0-9]+]], #-1
75 ; CHECK: rdvl [[VL_B:x[0-9]+]], #1
88 ; CHECK: rdvl x0, #-32
97 ; CHECK: rdvl x0, #31
Dsve-vscale-combine.ll36 ; CHECK-NEXT: rdvl x0, #2
46 ; CHECK-NEXT: rdvl x0, #3
57 ; CHECK-NEXT: rdvl x8, #-1
69 ; CHECK-NEXT: rdvl x8, #-1
86 ; CHECK-NEXT: rdvl x0, #1
96 ; CHECK-NEXT: rdvl x0, #1
Dsve-gep.ll11 ; CHECK-NEXT: rdvl x8, #4
21 ; CHECK-NEXT: rdvl x8, #1
41 ; CHECK-NEXT: rdvl x8, #1
53 ; CHECK-NEXT: rdvl x8, #1
107 ; CHECK-NEXT: rdvl x8, #1
120 ; CHECK-NEXT: rdvl x8, #1
133 ; CHECK-NEXT: rdvl x8, #1
Dsve-split-extract-elt.ll30 ; CHECK-NEXT: rdvl x10, #2
55 ; CHECK-NEXT: rdvl x10, #1
152 ; CHECK-NEXT: rdvl x10, #1
177 ; CHECK-NEXT: rdvl x10, #1
Dsve-intrinsics-ldN-reg+imm-addr-mode.ll46 ; CHECK: rdvl x[[OFFSET:[0-9]]], #3
57 ; CHECK: rdvl x[[OFFSET:[0-9]]], #-18
68 ; CHECK: rdvl x[[OFFSET:[0-9]]], #16
183 ; CHECK: rdvl x[[OFFSET:[0-9]]], #4
194 ; CHECK: rdvl x[[OFFSET:[0-9]]], #5
205 ; CHECK: rdvl x[[OFFSET:[0-9]]], #-27
216 ; CHECK: rdvl x[[OFFSET:[0-9]]], #24
331 ; CHECK: rdvl x[[OFFSET:[0-9]]], #5
342 ; CHECK: rdvl x[[OFFSET:[0-9]]], #6
353 ; CHECK: rdvl x[[OFFSET:[0-9]]], #7
[all …]
Dsve-intrinsics-stN-reg-imm-addr-mode.ll31 ; CHECK: rdvl x[[N:[0-9]+]], #3
44 ; CHECK: rdvl x[[N:[0-9]+]], #-18
57 ; CHECK: rdvl x[[N:[0-9]+]], #16
195 ; CHECK: rdvl x[[N:[0-9]+]], #4
209 ; CHECK: rdvl x[[N:[0-9]+]], #5
223 ; CHECK: rdvl x[[N:[0-9]+]], #-27
237 ; CHECK: rdvl x[[N:[0-9]+]], #24
385 ; CHECK: rdvl x[[N:[0-9]+]], #5
400 ; CHECK: rdvl x[[N:[0-9]+]], #6
415 ; CHECK: rdvl x[[N:[0-9]+]], #7
[all …]
Dsve-ld1-addressing-mode-reg-imm.ll46 ; CHECK-NEXT: rdvl x8, #8
59 ; CHECK-NEXT: rdvl x8, #-9
Dsve-st1-addressing-mode-reg-imm.ll46 ; CHECK-NEXT: rdvl x8, #8
59 ; CHECK-NEXT: rdvl x8, #-9
Dsve-insert-vector.ll144 ; CHECK-NEXT: rdvl x8, #1
165 ; CHECK-NEXT: rdvl x8, #1
Dsve-split-insert-elt.ll30 ; CHECK-NEXT: rdvl x8, #2
142 ; CHECK-NEXT: rdvl x10, #2
Dsve-forward-st-to-ld.ll56 ; CHECK-NEXT: rdvl x8, #1
Dsve-pred-non-temporal-ldst-addressing-mode-reg-imm.ll14 ; CHECK-NEXT: rdvl x8, #8
17 ; CHECK-NEXT: rdvl x8, #-9
Dsve-intrinsics-st1-addressing-mode-reg-imm.ll46 ; CHECK: rdvl x[[OFFSET:[0-9]+]], #8
58 ; CHECK: rdvl x[[OFFSET:[0-9]+]], #-9
Dsve-extract-vector.ll120 ; CHECK-NEXT: rdvl x8, #1
Dsve-intrinsics-ld1-addressing-mode-reg-imm.ll70 ; CHECK: rdvl x[[OFFSET:[0-9]+]], #8
82 ; CHECK: rdvl x[[OFFSET:[0-9]+]], #-9
Dsve-intrinsics-loads-nf.ll21 ; CHECK: rdvl x[[OFFSET:[0-9]+]], #-9
67 ; CHECK: rdvl x[[OFFSET:[0-9]+]], #8
Dsve-pred-contiguous-ldst-addressing-mode-reg-imm.ll14 ; CHECK-NEXT: rdvl x8, #8
17 ; CHECK-NEXT: rdvl x8, #-9
/external/vixl/src/aarch64/
Dmacro-assembler-sve-aarch64.cc269 rdvl(xd, static_cast<int>(multiplier)); in Addvl()
293 rdvl(b, 1); in Addvl()
Dassembler-aarch64.h5168 void rdvl(const Register& xd, int imm6);
Dassembler-sve-aarch64.cc6307 void Assembler::rdvl(const Register& xd, int imm6) { in rdvl() function in vixl::aarch64::Assembler
/external/vixl/test/aarch64/
Dtest-disasm-sve-aarch64.cc6240 COMPARE_PREFIX(rdvl(x26, 0), "rdvl x26, #0"); in TEST()
6241 COMPARE_PREFIX(rdvl(x27, 31), "rdvl x27, #31"); in TEST()
6242 COMPARE_PREFIX(rdvl(x28, -32), "rdvl x28, #-32"); in TEST()
6243 COMPARE_PREFIX(rdvl(xzr, 9), "rdvl xzr, #9"); in TEST()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64SVEInstrInfo.td839 def RDVLI_XI : sve_int_read_vl_a<0b0, 0b11111, "rdvl">;
/external/llvm-project/llvm/lib/Target/AArch64/
DAArch64SVEInstrInfo.td1285 def RDVLI_XI : sve_int_read_vl_a<0b0, 0b11111, "rdvl">;

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