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Searched refs:read_reg (Results 1 – 22 of 22) sorted by relevance

/external/igt-gpu-tools/tools/
Dintel_display_poller.c77 static uint32_t read_reg(uint32_t reg) in read_reg() function
104 if ((read_reg(DSPACNTR) & DISPPLANE_SEL_PIPE_MASK) == DISPPLANE_SEL_PIPE_A) in pipe_to_plane()
106 if ((read_reg(DSPBCNTR) & DISPPLANE_SEL_PIPE_MASK) == DISPPLANE_SEL_PIPE_A) in pipe_to_plane()
112 if ((read_reg(DSPACNTR) & DISPPLANE_SEL_PIPE_MASK) == DISPPLANE_SEL_PIPE_B) in pipe_to_plane()
114 if ((read_reg(DSPBCNTR) & DISPPLANE_SEL_PIPE_MASK) == DISPPLANE_SEL_PIPE_B) in pipe_to_plane()
136 use_tileoff = read_reg(PIPE_REG(plane, DSPACNTR)) & DISPLAY_PLANE_TILED; in dspoffset_reg()
163 iir_mask = read_reg(iir) & 0x7fff0000; in poll_pixel_pipestat()
168 pix1 = read_reg(pix); in poll_pixel_pipestat()
169 iir1 = read_reg(iir); in poll_pixel_pipestat()
170 iir2 = read_reg(iir); in poll_pixel_pipestat()
[all …]
Dintel_watermark.c39 static uint32_t read_reg(uint32_t addr) in read_reg() function
257 wm_linetime[pipe] = read_reg(0x45270 + pipe * 0x4); in skl_wm_dump()
262 plane_ctl[pipe][plane] = read_reg(addr + 0x80); in skl_wm_dump()
263 wm_trans[pipe][plane] = read_reg(addr + 0x00168); in skl_wm_dump()
264 buf_cfg[pipe][plane] = read_reg(addr + 0x0017C); in skl_wm_dump()
266 nv12_buf_cfg[pipe][plane] = read_reg(addr + 0x00178); in skl_wm_dump()
271 wm[level][pipe][plane] = read_reg(wm_offset); in skl_wm_dump()
475 dspcntr[i] = read_reg(0x70180 + i * 0x1000); in ilk_wm_dump()
477 spcntr[i] = read_reg(0x70280 + i * 0x1000); in ilk_wm_dump()
479 spcntr[i] = read_reg(0x72180 + i * 0x1000); in ilk_wm_dump()
[all …]
/external/arm-trusted-firmware/plat/mediatek/common/drivers/pmic_wrap/
Dpmic_wrap_init.c22 uint32_t *read_reg) in wait_for_state_idle() argument
62 if (read_reg) in wait_for_state_idle()
63 *read_reg = reg_rdata; in wait_for_state_idle()
69 uint32_t *read_reg) in wait_for_state_ready() argument
92 if (read_reg) in wait_for_state_ready()
93 *read_reg = reg_rdata; in wait_for_state_ready()
/external/arm-trusted-firmware/drivers/imx/uart/
Dimx_uart.c60 static uint32_t read_reg(uintptr_t base, uint32_t offset) in read_reg() function
74 val = read_reg(base_addr, IMX_UART_CR2_OFFSET); in console_imx_uart_core_init()
144 val = read_reg(base_addr, IMX_UART_STAT2_OFFSET); in console_imx_uart_core_putc()
162 val = read_reg(base_addr, IMX_UART_TS_OFFSET); in console_imx_uart_core_getc()
166 val = read_reg(base_addr, IMX_UART_RXD_OFFSET); in console_imx_uart_core_getc()
/external/libiio/src/tests/
Diio_reg.c58 static int read_reg(const char *name, unsigned long addr) in read_reg() function
106 return read_reg(argv[1], addr); in main()
/external/crosvm/devices/src/irqchip/
Dioapic.rs516 fn read_reg(ioapic: &mut Ioapic, selector: u8) -> u32 { in read_reg() function
533 read_reg(ioapic, encode_selector_from_irq(irq, false)).into(), in read_entry()
538 read_reg(ioapic, encode_selector_from_irq(irq, true)).into(), in read_entry()
589 let before = read_reg(&mut ioapic, IOAPIC_REG_VERSION); in write_read_ioaic_reg_version()
593 assert_eq!(read_reg(&mut ioapic, IOAPIC_REG_VERSION), before); in write_read_ioaic_reg_version()
602 assert_eq!(read_reg(&mut ioapic, IOAPIC_REG_ID), 0x0f000000); in write_read_ioapic_reg_id()
618 read_reg(&mut ioapic, IOAPIC_REG_ARBITRATION_ID), in write_read_ioapic_arbitration_id()
625 read_reg(&mut ioapic, IOAPIC_REG_ARBITRATION_ID), in write_read_ioapic_arbitration_id()
/external/mesa3d/src/mesa/state_tracker/tests/
Dst_tests_common.cpp151 read_reg(s); in FakeCodeline()
154 read_reg(d); in FakeCodeline()
159 void FakeCodeline::read_reg(const st_reg& s) in read_reg() function in FakeCodeline
165 read_reg(*s.reladdr); in read_reg()
167 read_reg(*s.reladdr2); in read_reg()
Dst_tests_common.h90 void read_reg(const st_reg& s);
/external/crosvm/devices/src/pci/
Dpci_configuration.rs335 pub fn read_reg(&self, reg_idx: usize) -> u32 { in read_reg() method
707 let cap_ptr = cfg.read_reg(CAPABILITY_LIST_HEAD_OFFSET / 4) & 0xFF; in add_capability()
711 let cap1_data = cfg.read_reg(cap1_offset / 4); in add_capability()
717 let cap2_data = cfg.read_reg(cap2_offset / 4); in add_capability()
749 let class_reg = cfg.read_reg(2); in class_code()
775 assert_eq!(cfg.read_reg(0), 0x56781234); in read_only_bits()
Dpci_device.rs257 self.config_regs.read_reg(reg_idx) in read_config_register()
Dpci_root.rs41 self.config.read_reg(reg_idx) in read_config_register()
Dac97.rs356 self.config_regs.read_reg(reg_idx) in read_config_register()
/external/mesa3d/src/broadcom/simulator/
Dv3d_simulator_wrapper.cpp66 return hw->read_reg(reg); in v3d_hw_read_reg()
/external/arm-trusted-firmware/drivers/mtd/nand/
Dspi_nand.c30 static int spi_nand_reg(bool read_reg, uint8_t reg, uint8_t *val, in spi_nand_reg() argument
36 if (read_reg) { in spi_nand_reg()
/external/tensorflow/tensorflow/lite/micro/examples/magic_wand/sparkfun_edge/
Daccelerometer_handler.cc121 dev_ctx.read_reg = lis2dh12_read_platform_apollo3; // read bytes function in SetupAccelerometer()
/external/tensorflow/tensorflow/lite/micro/examples/person_detection/arduino/
Dimage_provider.cc89 test = myCAM.read_reg(ARDUCHIP_TEST1); in InitCamera()
/external/crosvm/devices/src/usb/xhci/
Dxhci_controller.rs253 self.config_regs.read_reg(reg_idx) in read_config_register()
/external/cpuinfo/test/dmesg/
Dgalaxy-c9-pro.log1066 [ 5.813665] [4: mdss_fb0: 509] [MDSS] samsung_nv_read : mdss DSI0 read_reg : DA[1] : 41 .
1071 [ 5.821376] [4: mdss_fb0: 509] [MDSS] samsung_nv_read : mdss DSI0 read_reg : DB[1] : 00 .
1072 [ 5.827730] [4: mdss_fb0: 509] [MDSS] samsung_nv_read : mdss DSI0 read_reg : DC[1] : 11 .
1079 [ 5.836192] [4: mdss_fb0: 509] [MDSS] samsung_nv_read : mdss DSI0 read_reg : C8[4] : 61 …
1089 [ 5.844305] [4: mdss_fb0: 509] [MDSS] samsung_nv_read : mdss DSI0 read_reg : D6[5] : 51 …
1095 [ 5.851758] [4: mdss_fb0: 509] [MDSS] samsung_nv_read : mdss DSI0 read_reg : C8[7] : 61 …
1098 [ 5.857919] [4: mdss_fb0: 509] [MDSS] samsung_nv_read : mdss DSI0 read_reg : D6[5] : 00 …
1103 [ 5.864727] [4: mdss_fb0: 509] [MDSS] samsung_nv_read : mdss DSI0 read_reg : B4[4] : 6f …
1105 [ 5.877910] [4: mdss_fb0: 509] [MDSS] samsung_nv_read : mdss DSI0 read_reg : B4[29] : 7b…
1109 [ 5.883446] [4: mdss_fb0: 509] [MDSS] samsung_nv_read : mdss DSI0 read_reg : B6[2] : 11 …
[all …]
Dgalaxy-s5-us.log2260 <6>[ 6.759540] read_reg : C8[2] : 35 13 .
2264 <6>[ 6.776153] read_reg : D6[5] : 42 15 16 a0 ce .
2273 <6>[ 6.792376] read_reg : C8[7] : 01 18 01 17 01 1e 07 .
2287 <6>[ 6.829928] read_reg : C8[15] : 81 7f 81 7c 7d 7c 7a .7b 7a 7f 7e 7f 7f 7f .7f .
2294 <6>[ 6.851426] read_reg : B6[1] : 13 .
2298 <6>[ 6.870260] read_reg : FD[1] : bc .
2302 <6>[ 6.887055] read_reg : A1[4] : 0b a7 0c 5f .
2313 <6>[ 6.929965] read_reg : C8[33] : 00 25 00 11 00 5e 5f .61 5e 5b 5d 5a 4d 4e .4b 53 56 51 62 64…
2425 <6>[ 7.195949] read_reg : A[1] : 9c .
Dgalaxy-s7-us.log3475 [ 6.289587] [2: mdss_fb0: 763] [MDSS] samsung_nv_read : mdss DSI0 read_reg : 4[3] : 00 4…
3496 [ 6.300832] [0: mdss_fb0: 763] [MDSS] samsung_nv_read : mdss DSI0 read_reg : C8[4] : 5a …
3499 [ 6.303653] [1: mdss_fb0: 763] [MDSS] samsung_nv_read : mdss DSI0 read_reg : D6[5] : c0 …
3504 [ 6.305799] [0: mdss_fb0: 763] [MDSS] samsung_nv_read : mdss DSI0 read_reg : C8[7] : 5a …
3507 [ 6.307898] [0: mdss_fb0: 763] [MDSS] samsung_nv_read : mdss DSI0 read_reg : B5[2] : 10 …
3509 [ 6.313213] [1: mdss_fb0: 763] [MDSS] samsung_nv_read : mdss DSI0 read_reg : B3[33] : 6f…
3510 [ 6.314984] [1: mdss_fb0: 763] [MDSS] samsung_nv_read : mdss DSI0 read_reg : A1[4] : 0b …
3517 [ 6.320865] [0: mdss_fb0: 763] [MDSS] samsung_nv_read : mdss DSI0 read_reg : C8[35] : 00…
3527 [ 6.327152] [1: mdss_fb0: 763] [MDSS] samsung_nv_read : mdss DSI0 read_reg : C8[35] : 00…
Dgalaxy-s8-us.log3319 [ 6.395266] [1: mdss_fb0: 672] [MDSS] samsung_nv_read : mdss DSI0 read_reg : 4[3] : d1 4…
3324 [ 6.396347] [1: mdss_fb0: 672] [MDSS] samsung_nv_read : mdss DSI0 read_reg : A1[4] : 64 …
3326 [ 6.397277] [1: mdss_fb0: 672] [MDSS] samsung_nv_read : mdss DSI0 read_reg : D6[5] : f2 …
3328 [ 6.398314] [1: mdss_fb0: 672] [MDSS] samsung_nv_read : mdss DSI0 read_reg : C9[20] : 30…
3330 [ 6.399161] [1: mdss_fb0: 672] [MDSS] samsung_nv_read : mdss DSI0 read_reg : B5[2] : 12 …
3331 [ 6.400485] [1: mdss_fb0: 672] [MDSS] samsung_nv_read : mdss DSI0 read_reg : B3[33] : 07…
3332 [ 6.401124] [1: mdss_fb0: 672] [MDSS] samsung_nv_read : mdss DSI0 read_reg : A1[4] : 0b …
3337 [ 6.402160] [1: mdss_fb0: 672] [MDSS] samsung_nv_read : mdss DSI0 read_reg : A1[7] : 64 …
3339 [ 6.403672] [3: mdss_fb0: 672] [MDSS] samsung_nv_read : mdss DSI0 read_reg : C8[35] : 00…
3347 [ 6.406239] [2: mdss_fb0: 672] [MDSS] samsung_nv_read : mdss DSI0 read_reg : C8[35] : 00…
[all …]
/external/crosvm/devices/src/virtio/
Dvirtio_pci_device.rs545 let mut data: u32 = self.config_regs.read_reg(reg_idx); in read_config_register()