| /external/libvpx/libvpx/vpx_dsp/mips/ |
| D | idct32x32_msa.c | 45 v8i16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in idct32x8_row_even_process_store() local
49 LD_SH8(tmp_buf, 32, reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7); in idct32x8_row_even_process_store()
59 DOTP_CONST_PAIR(reg0, reg4, cospi_16_64, cospi_16_64, reg0, reg4); in idct32x8_row_even_process_store()
61 BUTTERFLY_4(reg4, reg0, reg2, reg6, vec1, vec3, vec2, vec0); in idct32x8_row_even_process_store()
66 LD_SH8((tmp_buf + 16), 32, reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7); in idct32x8_row_even_process_store()
68 DOTP_CONST_PAIR(reg4, reg3, cospi_14_64, cospi_18_64, reg4, reg3); in idct32x8_row_even_process_store()
72 vec0 = reg0 + reg4; in idct32x8_row_even_process_store()
73 reg0 = reg0 - reg4; in idct32x8_row_even_process_store()
74 reg4 = reg6 + reg2; in idct32x8_row_even_process_store()
83 reg2 = reg3 + reg4; in idct32x8_row_even_process_store()
[all …]
|
| D | idct16x16_msa.c | 16 v8i16 reg0, reg2, reg4, reg6, reg8, reg10, reg12, reg14; in vpx_idct16_1d_rows_msa() local
20 LD_SH8(input, 16, reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7); in vpx_idct16_1d_rows_msa()
24 TRANSPOSE8x8_SH_SH(reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7, reg0, reg1, in vpx_idct16_1d_rows_msa()
25 reg2, reg3, reg4, reg5, reg6, reg7); in vpx_idct16_1d_rows_msa()
33 DOTP_CONST_PAIR(reg4, reg12, cospi_24_64, cospi_8_64, reg4, reg12); in vpx_idct16_1d_rows_msa()
34 BUTTERFLY_4(reg8, reg0, reg4, reg12, reg2, reg6, reg10, reg14); in vpx_idct16_1d_rows_msa()
35 SUB4(reg2, loc1, reg14, loc0, reg6, loc3, reg10, loc2, reg0, reg12, reg4, in vpx_idct16_1d_rows_msa()
76 loc1 = reg4 + loc0; in vpx_idct16_1d_rows_msa()
77 loc2 = reg4 - loc0; in vpx_idct16_1d_rows_msa()
81 BUTTERFLY_4(reg8, reg10, reg11, reg5, loc0, reg4, reg9, loc1); in vpx_idct16_1d_rows_msa()
[all …]
|
| /external/vixl/src/aarch64/ |
| D | registers-aarch64.cc | 176 const CPURegister& reg4, in AreAliased() argument
189 const CPURegister regs[] = {reg1, reg2, reg3, reg4, reg5, reg6, reg7, reg8}; in AreAliased()
227 const CPURegister& reg4, in AreSameSizeAndType() argument
236 match &= !reg4.IsValid() || reg4.IsSameSizeAndType(reg1); in AreSameSizeAndType()
247 const CPURegister& reg4, in AreEven() argument
256 even &= !reg4.IsValid() || ((reg4.GetCode() % 2) == 0); in AreEven()
267 const CPURegister& reg4) { in AreConsecutive() argument
284 if (!reg4.IsValid()) { in AreConsecutive()
286 } else if (reg4.GetCode() != in AreConsecutive()
297 const CPURegister& reg4) { in AreSameFormat() argument
[all …]
|
| D | registers-aarch64.h | 840 const CPURegister& reg4 = NoReg,
853 const CPURegister& reg4 = NoCPUReg,
865 const CPURegister& reg4 = NoReg,
878 const CPURegister& reg4 = NoCPUReg);
886 const CPURegister& reg4 = NoCPUReg);
896 const CPURegister& reg4 = NoCPUReg);
|
| D | macro-assembler-aarch64.cc | 2952 const Register& reg4) { in Include() argument
2955 reg1.GetBit() | reg2.GetBit() | reg3.GetBit() | reg4.GetBit(); in Include()
2966 const VRegister& reg4) { in Include() argument
2968 reg1.GetBit() | reg2.GetBit() | reg3.GetBit() | reg4.GetBit(); in Include()
2976 const CPURegister& reg4) { in Include() argument
2981 const CPURegister regs[] = {reg1, reg2, reg3, reg4}; in Include()
3016 const Register& reg4) { in Exclude() argument
3018 reg1.GetBit() | reg2.GetBit() | reg3.GetBit() | reg4.GetBit(); in Exclude()
3026 const VRegister& reg4) { in Exclude() argument
3028 reg1.GetBit() | reg2.GetBit() | reg3.GetBit() | reg4.GetBit(); in Exclude()
[all …]
|
| /external/elfutils/tests/ |
| D | run-varlocs.sh | 59 [400500,400504) {reg4}
67 [400510,40051c) {reg4}
69 [40052a,400531) {GNU_entry_value(1) {reg4}, stack_value}
82 [400400,400403) {reg4}
83 [400403,40040b) {GNU_entry_value(1) {reg4}, stack_value}
110 [400400,400408) {reg4}
111 [400408,400423) {GNU_entry_value(1) {reg4}, stack_value}
147 [401050,401066) {reg4}
148 [401066,401067) {entry_value(1) {reg4}, stack_value}
159 [401150,401160) {reg4}
[all …]
|
| D | run-dwarfcfi.sh | 42 reg4: location expression: call_frame_cfa stack_value
59 reg4: undefined
76 reg4: undefined
93 reg4: undefined
110 reg4: same_value
127 reg4: undefined
|
| D | run-readelf-loc.sh | 297 [ 0] reg4
302 [ 0] reg4
453 [ 0] reg4
458 [ 0] reg4
659 [ 0] reg4
664 [ 0] reg4
817 [ 0] reg4
822 [ 0] reg4
1114 [ 0] reg4
1119 [ 0] reg4
[all …]
|
| D | run-readelf-zdebug-rel.sh | 87 [ 0] reg4
192 [ 0] reg4
|
| /external/libyuv/files/source/ |
| D | rotate_msa.cc | 85 v16u8 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in TransposeWx16_MSA() local
109 ILVRL_H(vec0, vec2, vec1, vec3, reg4, reg5, reg6, reg7); in TransposeWx16_MSA()
110 ILVRL_W(reg0, reg4, reg1, reg5, res0, res1, res2, res3); in TransposeWx16_MSA()
131 ILVRL_H(vec0, vec2, vec1, vec3, reg4, reg5, reg6, reg7); in TransposeWx16_MSA()
132 res8 = (v16u8)__msa_ilvr_w((v4i32)reg4, (v4i32)reg0); in TransposeWx16_MSA()
133 res9 = (v16u8)__msa_ilvl_w((v4i32)reg4, (v4i32)reg0); in TransposeWx16_MSA()
166 v16u8 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in TransposeUVWx16_MSA() local
190 ILVRL_H(vec0, vec2, vec1, vec3, reg4, reg5, reg6, reg7); in TransposeUVWx16_MSA()
191 ILVRL_W(reg0, reg4, reg1, reg5, res0, res1, res2, res3); in TransposeUVWx16_MSA()
212 ILVRL_H(vec0, vec2, vec1, vec3, reg4, reg5, reg6, reg7); in TransposeUVWx16_MSA()
[all …]
|
| D | scale_msa.cc | 141 v8u16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in ScaleARGBRowDownEvenBox_MSA() local
169 reg4 = (v8u16)__msa_pckev_d((v2i64)reg2, (v2i64)reg0); in ScaleARGBRowDownEvenBox_MSA()
173 reg4 += reg6; in ScaleARGBRowDownEvenBox_MSA()
175 reg4 = (v8u16)__msa_srari_h((v8i16)reg4, 2); in ScaleARGBRowDownEvenBox_MSA()
177 dst0 = (v16u8)__msa_pckev_b((v16i8)reg5, (v16i8)reg4); in ScaleARGBRowDownEvenBox_MSA()
669 v16u8 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in ScaleARGBFilterCols_MSA() local
705 reg4 = (v16u8)__msa_ilvr_b((v16i8)src2, (v16i8)src0); in ScaleARGBFilterCols_MSA()
709 tmp0 = __msa_dotp_u_h(reg4, mult0); in ScaleARGBFilterCols_MSA()
766 v8i16 reg0, reg1, reg2, reg3, reg4, reg5; in ScaleRowDown34_0_Box_MSA() local
806 reg4 = (v8i16)__msa_dotp_u_h(vec4, const1); in ScaleRowDown34_0_Box_MSA()
[all …]
|
| D | row_msa.cc | 774 v8u16 reg0, reg1, reg2, reg3, reg4, reg5; in ARGBToYRow_MSA() local
794 reg4 = (v8u16)__msa_ilvod_b(zero, (v16i8)vec0); in ARGBToYRow_MSA()
800 reg4 *= const_0x42; in ARGBToYRow_MSA()
804 reg0 += reg4; in ARGBToYRow_MSA()
826 v8u16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7, reg8, reg9; in ARGBToUVRow_MSA() local
862 reg4 = __msa_hadd_u_h(vec0, vec0); in ARGBToUVRow_MSA()
890 reg4 += __msa_hadd_u_h(vec0, vec0); in ARGBToUVRow_MSA()
896 reg4 = (v8u16)__msa_srai_h((v8i16)reg4, 2); in ARGBToUVRow_MSA()
904 reg8 += reg4 * const_0x26; in ARGBToUVRow_MSA()
910 reg4 *= const_0x70; in ARGBToUVRow_MSA()
[all …]
|
| /external/libvpx/libvpx/third_party/libyuv/source/ |
| D | rotate_msa.cc | 85 v16u8 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in TransposeWx16_MSA() local
109 ILVRL_H(vec0, vec2, vec1, vec3, reg4, reg5, reg6, reg7); in TransposeWx16_MSA()
110 ILVRL_W(reg0, reg4, reg1, reg5, res0, res1, res2, res3); in TransposeWx16_MSA()
131 ILVRL_H(vec0, vec2, vec1, vec3, reg4, reg5, reg6, reg7); in TransposeWx16_MSA()
132 res8 = (v16u8)__msa_ilvr_w((v4i32)reg4, (v4i32)reg0); in TransposeWx16_MSA()
133 res9 = (v16u8)__msa_ilvl_w((v4i32)reg4, (v4i32)reg0); in TransposeWx16_MSA()
166 v16u8 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in TransposeUVWx16_MSA() local
190 ILVRL_H(vec0, vec2, vec1, vec3, reg4, reg5, reg6, reg7); in TransposeUVWx16_MSA()
191 ILVRL_W(reg0, reg4, reg1, reg5, res0, res1, res2, res3); in TransposeUVWx16_MSA()
212 ILVRL_H(vec0, vec2, vec1, vec3, reg4, reg5, reg6, reg7); in TransposeUVWx16_MSA()
[all …]
|
| D | scale_msa.cc | 141 v8u16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in ScaleARGBRowDownEvenBox_MSA() local
169 reg4 = (v8u16)__msa_pckev_d((v2i64)reg2, (v2i64)reg0); in ScaleARGBRowDownEvenBox_MSA()
173 reg4 += reg6; in ScaleARGBRowDownEvenBox_MSA()
175 reg4 = (v8u16)__msa_srari_h((v8i16)reg4, 2); in ScaleARGBRowDownEvenBox_MSA()
177 dst0 = (v16u8)__msa_pckev_b((v16i8)reg5, (v16i8)reg4); in ScaleARGBRowDownEvenBox_MSA()
669 v16u8 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in ScaleARGBFilterCols_MSA() local
705 reg4 = (v16u8)__msa_ilvr_b((v16i8)src2, (v16i8)src0); in ScaleARGBFilterCols_MSA()
709 tmp0 = __msa_dotp_u_h(reg4, mult0); in ScaleARGBFilterCols_MSA()
766 v8i16 reg0, reg1, reg2, reg3, reg4, reg5; in ScaleRowDown34_0_Box_MSA() local
806 reg4 = (v8i16)__msa_dotp_u_h(vec4, const1); in ScaleRowDown34_0_Box_MSA()
[all …]
|
| D | row_msa.cc | 774 v8u16 reg0, reg1, reg2, reg3, reg4, reg5; in ARGBToYRow_MSA() local
794 reg4 = (v8u16)__msa_ilvod_b(zero, (v16i8)vec0); in ARGBToYRow_MSA()
800 reg4 *= const_0x42; in ARGBToYRow_MSA()
804 reg0 += reg4; in ARGBToYRow_MSA()
826 v8u16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7, reg8, reg9; in ARGBToUVRow_MSA() local
862 reg4 = __msa_hadd_u_h(vec0, vec0); in ARGBToUVRow_MSA()
890 reg4 += __msa_hadd_u_h(vec0, vec0); in ARGBToUVRow_MSA()
896 reg4 = (v8u16)__msa_srai_h((v8i16)reg4, 2); in ARGBToUVRow_MSA()
904 reg8 += reg4 * const_0x26; in ARGBToUVRow_MSA()
910 reg4 *= const_0x70; in ARGBToUVRow_MSA()
[all …]
|
| /external/llvm/test/CodeGen/ARM/ |
| D | fast-isel-pic.ll | 45 ; THUMB-ELF: ldr r[[reg4:[0-9]+]], [r[[reg3]]]
46 ; THUMB-ELF: ldr r0, [r[[reg4]]]
48 ; ARM: ldr [[reg4:r[0-9]+]],
49 ; ARM: ldr [[reg4]], [pc, [[reg4]]]
|
| /external/llvm-project/llvm/test/CodeGen/ARM/ |
| D | fast-isel-pic.ll | 45 ; THUMB-ELF: ldr r[[reg4:[0-9]+]], [r[[reg3]]]
46 ; THUMB-ELF: ldr r0, [r[[reg4]]]
48 ; ARM: ldr [[reg4:r[0-9]+]],
49 ; ARM: ldr [[reg4]], [pc, [[reg4]]]
|
| /external/libxml2/result/HTML/ |
| D | reg4.html.err | 1 ./test/HTML/reg4.html:10: HTML parser error : Unexpected end tag : p
|
| /external/llvm/test/CodeGen/AMDGPU/ |
| D | pv.ll | 6 …eg1, <4 x float> inreg %reg2, <4 x float> inreg %reg3, <4 x float> inreg %reg4, <4 x float> inreg …
20 %12 = extractelement <4 x float> %reg4, i32 0
21 %13 = extractelement <4 x float> %reg4, i32 1
22 %14 = extractelement <4 x float> %reg4, i32 2
23 %15 = extractelement <4 x float> %reg4, i32 3
|
| /external/llvm-project/llvm/test/tools/llvm-objdump/COFF/ |
| D | eh_frame.test | 14 # CHECK: DW_CFA_def_cfa: reg4 +4
|
| /external/llvm/test/DebugInfo/ |
| D | dwarfdump-debug-frame-simple.test | 9 ; FRAMES: DW_CFA_def_cfa: reg4 +4
|
| /external/llvm-project/llvm/test/DebugInfo/ |
| D | dwarfdump-debug-frame-simple.test | 9 ; FRAMES: DW_CFA_def_cfa: {{reg4|ESP}} +4
|
| /external/llvm/test/MC/X86/ |
| D | i386-darwin-frame-register.ll | 14 ; CHECK: DW_CFA_def_cfa: reg4 +4
|
| /external/llvm-project/llvm/test/CodeGen/AMDGPU/ |
| D | pv.ll | 5 …eg1, <4 x float> inreg %reg2, <4 x float> inreg %reg3, <4 x float> inreg %reg4, <4 x float> inreg …
19 %tmp24 = extractelement <4 x float> %reg4, i32 0
20 %tmp25 = extractelement <4 x float> %reg4, i32 1
21 %tmp26 = extractelement <4 x float> %reg4, i32 2
22 %tmp27 = extractelement <4 x float> %reg4, i32 3
|
| /external/llvm-project/llvm/test/Transforms/NewGVN/ |
| D | pr33367.ll | 100 %reg4 = load i64, i64* %preg3, align 32, !tbaa !32
101 %add2c279 = add i64 %reg7, %reg4
|