Home
last modified time | relevance | path

Searched refs:reg_offset (Results 1 – 25 of 42) sorted by relevance

12

/external/arm-trusted-firmware/drivers/arm/ccn/
Dccn.c575 unsigned int reg_offset, unsigned long long val) in ccn_write_node_reg() argument
579 if (reg_offset > REGION_ID_OFFSET) { in ccn_write_node_reg()
581 reg_offset); in ccn_write_node_reg()
587 ccn_reg_write(ccn_plat_desc->periphbase, region_id, reg_offset, val); in ccn_write_node_reg()
591 + reg_offset); in ccn_write_node_reg()
601 unsigned int reg_offset) in ccn_read_node_reg() argument
606 if (reg_offset > REGION_ID_OFFSET) { in ccn_read_node_reg()
608 reg_offset); in ccn_read_node_reg()
614 val = ccn_reg_read(ccn_plat_desc->periphbase, region_id, reg_offset); in ccn_read_node_reg()
618 + reg_offset); in ccn_read_node_reg()
/external/mesa3d/src/intel/compiler/
Dbrw_ir_fs.h181 reg_offset(const fs_reg &r) in reg_offset() function
224 !(reg_offset(r) + dr <= reg_offset(s) || in regions_overlap()
225 reg_offset(s) + ds <= reg_offset(r)); in regions_overlap()
238 reg_offset(r) >= reg_offset(s) && in region_contained_in()
239 reg_offset(r) + dr <= reg_offset(s) + ds; in region_contained_in()
444 return DIV_ROUND_UP(reg_offset(inst->dst) % REG_SIZE + in regs_written()
463 return DIV_ROUND_UP(reg_offset(inst->src[i]) % reg_size + in regs_read()
Dbrw_ir_vec4.h232 reg_offset(const backend_reg &r) in reg_offset() function
264 !(reg_offset(r) + dr <= reg_offset(s) || in regions_overlap()
265 reg_offset(s) + ds <= reg_offset(r)); in regions_overlap()
420 return DIV_ROUND_UP(reg_offset(inst->dst) % REG_SIZE + inst->size_written, in regs_written()
435 return DIV_ROUND_UP(reg_offset(inst->src[i]) % reg_size + inst->size_read(i), in regs_read()
Dbrw_fs_lower_regioning.cpp114 if (reg_offset(inst->src[i]) % REG_SIZE != in required_dst_byte_offset()
115 reg_offset(inst->dst) % REG_SIZE) in required_dst_byte_offset()
119 return reg_offset(inst->dst) % REG_SIZE; in required_dst_byte_offset()
146 reg_offset(inst->src[i]) % REG_SIZE > 0 && in has_invalid_src_region()
154 const unsigned dst_byte_offset = reg_offset(inst->dst) % REG_SIZE; in has_invalid_src_region()
155 const unsigned src_byte_offset = reg_offset(inst->src[i]) % REG_SIZE; in has_invalid_src_region()
175 const unsigned dst_byte_offset = reg_offset(inst->dst) % REG_SIZE; in has_invalid_dst_region()
Dbrw_vec4_visitor.cpp1340 src_reg *reladdr, int reg_offset) in get_scratch_offset() argument
1362 brw_imm_d(reg_offset))); in get_scratch_offset()
1369 brw_imm_d(reg_offset * message_header_scale))); in get_scratch_offset()
1373 return brw_imm_d(reg_offset * message_header_scale); in get_scratch_offset()
1389 int reg_offset = base_offset + orig_src.offset / REG_SIZE; in emit_scratch_read() local
1391 reg_offset); in emit_scratch_read()
1399 index = get_scratch_offset(block, inst, orig_src.reladdr, reg_offset + 1); in emit_scratch_read()
1418 int reg_offset = base_offset + inst->dst.offset / REG_SIZE; in emit_scratch_write() local
1420 reg_offset); in emit_scratch_write()
1476 reg_offset + 1); in emit_scratch_write()
[all …]
/external/mesa3d/src/amd/common/
Dac_shadowed_regs.c2935 unsigned reg_offset = R_02835C_PA_SC_TILE_STEERING_OVERRIDE; in ac_emulate_clear_state() local
2939 gfx103_emulate_clear_state(cs, 1, &reg_offset, &reg_value, set_context_reg_seq_array); in ac_emulate_clear_state()
2941 gfx10_emulate_clear_state(cs, 1, &reg_offset, &reg_value, set_context_reg_seq_array); in ac_emulate_clear_state()
2953 unsigned reg_offset, unsigned count) in ac_check_shadowed_regs() argument
2965 unsigned end_reg_offset = reg_offset + count * 4; in ac_check_shadowed_regs()
2969 if (MAX2(ranges[i].offset, reg_offset) < MIN2(end_range_offset, end_reg_offset)) { in ac_check_shadowed_regs()
2978 if (reg_offset == R_00B858_COMPUTE_DESTINATION_EN_SE0 || in ac_check_shadowed_regs()
2979 reg_offset == R_00B864_COMPUTE_DESTINATION_EN_SE2) in ac_check_shadowed_regs()
2985 printf("%s .. %s\n", ac_get_register_name(chip_class, reg_offset), in ac_check_shadowed_regs()
2986 ac_get_register_name(chip_class, reg_offset + (count - 1) * 4)); in ac_check_shadowed_regs()
[all …]
Dac_shadowed_regs.h59 unsigned reg_offset, unsigned count);
/external/arm-trusted-firmware/include/drivers/arm/
Dccn.h106 unsigned int reg_offset,
110 unsigned int reg_offset);
/external/llvm-project/lldb/test/API/tools/lldb-server/register-reading/
DTestGdbRemoteGPacket.py11 reg_offset = int(reg_info["offset"])*2
14 reg_slice = reg_bank[reg_offset:reg_offset+reg_byte_size]
/external/arm-trusted-firmware/plat/rockchip/rk3288/drivers/pmu/
Dpmu.c125 static const uint32_t reg_offset[] = { GRF_UOC0_CON0, GRF_UOC1_CON0, in rk3288_sleep_disable_osc() local
134 for (i = 0; i < ARRAY_SIZE(reg_offset); i++) { in rk3288_sleep_disable_osc()
135 reg = mmio_read_32(GRF_BASE + reg_offset[i]); in rk3288_sleep_disable_osc()
/external/llvm-project/lldb/unittests/tools/lldb-server/tests/
DTestClient.cpp222 uint32_t reg_offset = 0; in qRegisterInfos() local
233 m_register_infos[Reg].byte_offset = reg_offset; in qRegisterInfos()
235 reg_offset = in qRegisterInfos()
/external/mesa3d/src/gallium/drivers/radeonsi/
Dsi_build_pm4.h37 #define SI_CHECK_SHADOWED_REGS(reg_offset, count) ac_check_shadowed_regs(GFX10, CHIP_NAVI14, reg_of…
39 #define SI_CHECK_SHADOWED_REGS(reg_offset, count) argument
/external/mesa3d/src/amd/vulkan/winsys/amdgpu/
Dradv_amdgpu_winsys.c145 unsigned reg_offset, in radv_amdgpu_winsys_read_registers() argument
150 return amdgpu_read_mm_registers(ws->dev, reg_offset / 4, num_registers, in radv_amdgpu_winsys_read_registers()
/external/llvm-project/lldb/source/Plugins/Process/Utility/
DDynamicRegisterInfo.cpp456 uint32_t reg_offset = 0; in Finalize() local
460 m_regs[regnum_pair.second].byte_offset = reg_offset; in Finalize()
462 reg_offset = m_regs[regnum_pair.second].byte_offset + in Finalize()
503 reg_offset = m_regs[i].byte_offset + m_regs[i].byte_size; in Finalize()
504 if (m_reg_data_byte_size < reg_offset) in Finalize()
505 m_reg_data_byte_size = reg_offset; in Finalize()
/external/mesa3d/src/intel/tools/
Daub_read.h51 void (*reg_write)(void *user_data, uint32_t reg_offset, uint32_t reg_value);
/external/llvm-project/lldb/source/Plugins/Process/FreeBSDRemote/
DNativeRegisterContextFreeBSD_x86_64.h82 uint8_t *GetOffsetRegSetData(uint32_t set, size_t reg_offset);
DNativeRegisterContextFreeBSD_x86_64.cpp620 size_t reg_offset) { in GetOffsetRegSetData() argument
635 assert(reg_offset >= m_regset_offsets[set]); in GetOffsetRegSetData()
636 return base + (reg_offset - m_regset_offsets[set]); in GetOffsetRegSetData()
/external/elfutils/libdw/
Ddwarf_frame_register.c76 case reg_offset: in dwarf_frame_register()
Dcfi.h127 reg_offset, /* DW_CFA_offset_extended et al */ enumerator
/external/mesa3d/src/gallium/drivers/r600/
Deg_debug.c134 unsigned reg_offset) in ac_parse_set_reg_packet() argument
136 unsigned reg = (ib[1] << 2) + reg_offset; in ac_parse_set_reg_packet()
/external/arm-trusted-firmware/drivers/marvell/comphy/
Dphy-comphy-3700.c262 static void comphy_usb3_set_direct(uintptr_t addr, uint32_t reg_offset, in comphy_usb3_set_direct() argument
265 reg_set16((reg_offset * PHY_SHFT(USB3) + addr), data, mask); in comphy_usb3_set_direct()
612 void (*usb3_reg_set)(uintptr_t addr, uint32_t reg_offset, uint16_t data, in mvebu_a3700_comphy_usb3_power_on()
/external/crosvm/devices/src/pci/
Dpci_configuration.rs345 let reg_offset = reg_idx * 4 + offset as usize; in write_reg() localVariable
347 1 => self.write_byte(reg_offset, data[0]), in write_reg()
348 2 => self.write_word(reg_offset, u16::from_le_bytes(data.try_into().unwrap())), in write_reg()
349 4 => self.write_dword(reg_offset, u32::from_le_bytes(data.try_into().unwrap())), in write_reg()
/external/crosvm/hypervisor/src/kvm/
Dx86_64.rs814 let reg_offset = 16 * reg; in from() localVariable
819 &mut state.regs[reg_offset..reg_offset + 4], in from()
834 let reg_offset = 16 * reg; in from() localVariable
838 std::mem::transmute::<&[i8], &[u8]>(&item.regs[reg_offset..reg_offset + 4]) in from()
/external/mesa3d/src/gallium/winsys/amdgpu/drm/
Damdgpu_winsys.c261 unsigned reg_offset, in amdgpu_read_registers() argument
266 return amdgpu_read_mm_registers(ws->dev, reg_offset / 4, num_registers, in amdgpu_read_registers()
/external/mesa3d/src/panfrost/midgard/
Dmidgard_ra.c45 offset_swizzle(unsigned *swizzle, unsigned reg_offset, unsigned srcshift, unsigned dstshift, unsign… in offset_swizzle() argument
49 signed reg_comp = reg_offset >> srcshift; in offset_swizzle()
54 assert(reg_comp << srcshift == reg_offset); in offset_swizzle()

12