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Searched refs:reg_val (Results 1 – 25 of 30) sorted by relevance

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/external/arm-trusted-firmware/plat/marvell/armada/a8k/common/
Dplat_pm.c119 uint32_t reg_val; in plat_marvell_cpu_powerdown() local
125 reg_val = mmio_read_32(PWRC_CPUN_CR_REG(cpu_id)); in plat_marvell_cpu_powerdown()
126 reg_val |= 0x1 << PWRC_CPUN_CR_ISO_ENABLE_OFFSET; in plat_marvell_cpu_powerdown()
127 mmio_write_32(PWRC_CPUN_CR_REG(cpu_id), reg_val); in plat_marvell_cpu_powerdown()
131 reg_val = mmio_read_32(PWRC_CPUN_CR_REG(cpu_id)); in plat_marvell_cpu_powerdown()
133 } while (!(reg_val & (0x1 << PWRC_CPUN_CR_ISO_ENABLE_OFFSET)) && in plat_marvell_cpu_powerdown()
137 reg_val = mmio_read_32(PWRC_CPUN_CR_REG(cpu_id)); in plat_marvell_cpu_powerdown()
138 reg_val &= ~PWRC_CPUN_CR_PWR_DN_RQ_MASK; in plat_marvell_cpu_powerdown()
139 mmio_write_32(PWRC_CPUN_CR_REG(cpu_id), reg_val); in plat_marvell_cpu_powerdown()
144 reg_val = mmio_read_32(PWRC_CPUN_CR_REG(cpu_id)); in plat_marvell_cpu_powerdown()
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Dplat_ble_setup.c372 uint32_t reg_val, avs_workpoint, freq_pidi_mode; in ble_plat_svc_config() local
385 reg_val = mmio_read_32(MVEBU_AP_EFUSE_SRV_CTRL_REG); in ble_plat_svc_config()
386 reg_val &= ~EFUSE_SRV_CTRL_LD_SELECT_OFFS; in ble_plat_svc_config()
387 mmio_write_32(MVEBU_AP_EFUSE_SRV_CTRL_REG, reg_val); in ble_plat_svc_config()
543 reg_val = mmio_read_32(AVS_EN_CTRL_REG); in ble_plat_svc_config()
544 avs_workpoint = (reg_val & in ble_plat_svc_config()
624 reg_val = mmio_read_32(AVS_EN_CTRL_REG); in ble_plat_svc_config()
626 (reg_val & AVS_VDD_LOW_LIMIT_MASK) >> AVS_LOW_VDD_LIMIT_OFFSET, in ble_plat_svc_config()
628 reg_val &= ~(AVS_VDD_LOW_LIMIT_MASK | AVS_VDD_HIGH_LIMIT_MASK); in ble_plat_svc_config()
629 reg_val |= 0x1 << AVS_ENABLE_OFFSET; in ble_plat_svc_config()
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/external/arm-trusted-firmware/drivers/brcm/emmc/
Demmc_chal_sd.c194 uint32_t reg_val; in chal_sd_init() local
207 reg_val = 0; in chal_sd_init()
208 reg_val |= (1 << ICFG_SDIO0_CAP0__SLOT_TYPE_R); in chal_sd_init()
209 reg_val |= (0 << ICFG_SDIO0_CAP0__INT_MODE_R); in chal_sd_init()
210 reg_val |= (0 << ICFG_SDIO0_CAP0__SYS_BUS_64BIT_R); in chal_sd_init()
211 reg_val |= (1 << ICFG_SDIO0_CAP0__VOLTAGE_1P8V_R); in chal_sd_init()
212 reg_val |= (1 << ICFG_SDIO0_CAP0__VOLTAGE_3P0V_R); in chal_sd_init()
213 reg_val |= (1 << ICFG_SDIO0_CAP0__VOLTAGE_3P3V_R); in chal_sd_init()
214 reg_val |= (1 << ICFG_SDIO0_CAP0__SUSPEND_RESUME_R); in chal_sd_init()
215 reg_val |= (1 << ICFG_SDIO0_CAP0__SDMA_R); in chal_sd_init()
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/external/arm-trusted-firmware/drivers/arm/gic/v2/
Dgicdv2_helpers.c249 unsigned int reg_val = gicd_read_igroupr(base, id); in gicd_get_igroupr() local
251 return (reg_val >> bit_num) & 0x1U; in gicd_get_igroupr()
257 unsigned int reg_val = gicd_read_igroupr(base, id); in gicd_set_igroupr() local
259 gicd_write_igroupr(base, id, reg_val | (1U << bit_num)); in gicd_set_igroupr()
265 unsigned int reg_val = gicd_read_igroupr(base, id); in gicd_clr_igroupr() local
267 gicd_write_igroupr(base, id, reg_val & ~(1U << bit_num)); in gicd_clr_igroupr()
301 unsigned int reg_val = gicd_read_isactiver(base, id); in gicd_get_isactiver() local
303 return (reg_val >> bit_num) & 0x1U; in gicd_get_isactiver()
333 uint32_t reg_val = gicd_read_icfgr(base, id); in gicd_set_icfgr() local
336 reg_val &= ~(GIC_CFG_MASK << bit_shift); in gicd_set_icfgr()
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/external/arm-trusted-firmware/drivers/arm/gic/common/
Dgic_common.c251 unsigned int reg_val = gicd_read_igroupr(base, id); in gicd_get_igroupr() local
253 return (reg_val >> bit_num) & 0x1U; in gicd_get_igroupr()
259 unsigned int reg_val = gicd_read_igroupr(base, id); in gicd_set_igroupr() local
261 gicd_write_igroupr(base, id, reg_val | (1U << bit_num)); in gicd_set_igroupr()
267 unsigned int reg_val = gicd_read_igroupr(base, id); in gicd_clr_igroupr() local
269 gicd_write_igroupr(base, id, reg_val & ~(1U << bit_num)); in gicd_clr_igroupr()
303 unsigned int reg_val = gicd_read_isactiver(base, id); in gicd_get_isactiver() local
305 return (reg_val >> bit_num) & 0x1U; in gicd_get_isactiver()
335 uint32_t reg_val = gicd_read_icfgr(base, id); in gicd_set_icfgr() local
338 reg_val &= ~(GIC_CFG_MASK << bit_shift); in gicd_set_icfgr()
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/external/arm-trusted-firmware/drivers/arm/smmu/
Dsmmu_v3.c19 uint32_t reg_val; in smmuv3_poll() local
25 reg_val = mmio_read_32(smmu_reg); in smmuv3_poll()
26 if ((reg_val & mask) == value) in smmuv3_poll()
31 ERROR("Read value 0x%x, expected 0x%x\n", reg_val, in smmuv3_poll()
32 value == 0U ? reg_val & ~mask : reg_val | mask); in smmuv3_poll()
/external/arm-trusted-firmware/plat/arm/common/
Darm_common.c132 unsigned int reg_val; in arm_configure_sys_timer() local
138 reg_val = (1U << CNTACR_RPCT_SHIFT) | (1U << CNTACR_RVCT_SHIFT); in arm_configure_sys_timer()
139 reg_val |= (1U << CNTACR_RFRQ_SHIFT) | (1U << CNTACR_RVOFF_SHIFT); in arm_configure_sys_timer()
140 reg_val |= (1U << CNTACR_RWVT_SHIFT) | (1U << CNTACR_RWPT_SHIFT); in arm_configure_sys_timer()
141 mmio_write_32(ARM_SYS_TIMCTL_BASE + CNTACR_BASE(PLAT_ARM_NSTIMER_FRAME_ID), reg_val); in arm_configure_sys_timer()
144 reg_val = (1U << CNTNSAR_NS_SHIFT(PLAT_ARM_NSTIMER_FRAME_ID)); in arm_configure_sys_timer()
145 mmio_write_32(ARM_SYS_TIMCTL_BASE + CNTNSAR, reg_val); in arm_configure_sys_timer()
/external/arm-trusted-firmware/plat/socionext/synquacer/
Dsq_bl31_setup.c121 unsigned int reg_val; in sq_configure_sys_timer() local
123 reg_val = (1 << CNTACR_RPCT_SHIFT) | (1 << CNTACR_RVCT_SHIFT); in sq_configure_sys_timer()
124 reg_val |= (1 << CNTACR_RFRQ_SHIFT) | (1 << CNTACR_RVOFF_SHIFT); in sq_configure_sys_timer()
125 reg_val |= (1 << CNTACR_RWVT_SHIFT) | (1 << CNTACR_RWPT_SHIFT); in sq_configure_sys_timer()
127 CNTACR_BASE(PLAT_SQ_NSTIMER_FRAME_ID), reg_val); in sq_configure_sys_timer()
129 reg_val = (1 << CNTNSAR_NS_SHIFT(PLAT_SQ_NSTIMER_FRAME_ID)); in sq_configure_sys_timer()
130 mmio_write_32(SQ_SYS_TIMCTL_BASE + CNTNSAR, reg_val); in sq_configure_sys_timer()
/external/arm-trusted-firmware/drivers/marvell/mochi/
Dap807_setup.c283 uint32_t reg_val; in ap807_dram_phy_access_config() local
285 reg_val = mmio_read_32(DSS_SCR_REG); in ap807_dram_phy_access_config()
286 reg_val &= ~(DSS_PPROT_MASK << DSS_PPROT_OFFS); in ap807_dram_phy_access_config()
287 reg_val |= ((DSS_PPROT_PRIV_SECURE_DATA & DSS_PPROT_MASK) << in ap807_dram_phy_access_config()
289 mmio_write_32(DSS_SCR_REG, reg_val); in ap807_dram_phy_access_config()
/external/crosvm/devices/src/
Dpl030.rs87 let reg_val = u32::from_ne_bytes(*data_array); in write() localVariable
93 self.match_value = reg_val; in write()
100 if reg_val == 0 { in write()
/external/llvm-project/lldb/source/Core/
DDumpRegisterValue.cpp18 bool lldb_private::DumpRegisterValue(const RegisterValue &reg_val, Stream *s, in DumpRegisterValue() argument
24 if (reg_val.GetData(data)) { in DumpRegisterValue()
/external/llvm-project/lldb/include/lldb/Core/
DDumpRegisterValue.h23 bool DumpRegisterValue(const RegisterValue &reg_val, Stream *s,
/external/mesa3d/src/freedreno/decode/
Dcffdec.c321 reg_val(uint32_t regbase) in reg_val() function
353 reg_val(r + 4), reg_val(r + 5), in reg_dump_scratch()
354 reg_val(r + 6), reg_val(r + 7)); in reg_dump_scratch()
484 return reg_val(regbase(count_reg)); in get_tex_count()
832 gpuaddr = (((uint64_t)dword) << 32) | reg_val(regbase-1); in dump_register_val()
834 gpuaddr = (((uint64_t)reg_val(regbase+1)) << 32) | dword; in dump_register_val()
997 uint32_t lastval = reg_val(regbase); in skip_query()
1013 uint32_t scissor_tl = reg_val(regbase("GRAS_SC_WINDOW_SCISSOR_TL")); in __do_query()
1014 uint32_t scissor_br = reg_val(regbase("GRAS_SC_WINDOW_SCISSOR_BR")); in __do_query()
1025 uint32_t lastval = reg_val(regbase); in __do_query()
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Dcffdec.h83 uint32_t reg_val(uint32_t regbase);
Dcrashdec.c85 uint64_t val = reg_val(reg); in regval64()
87 val |= ((uint64_t)reg_val(reg + 1)) << 32; in regval64()
96 return reg_val(reg); in regval()
Dscript.c75 return reg_val(regbase); in rnn_val()
535 lua_pushnumber(L, reg_val(regbase)); in l_reg_val()
/external/llvm-project/lldb/scripts/
Ddisasm-gdb-remote.pl570 my $reg_val = &$reg_extract($arrayref);
572 printf("\t%*s = $reg_format", $max_register_name_len, $reg_name, $reg_val);
574 printf("%s = $reg_format", $reg_name, $reg_val);
894 my $reg_val = &$reg_extract(\@_);
895 printf("\t%*s = $reg_format\n", $max_register_name_len, $reg_name, $reg_val);
915 my $reg_val = &$reg_extract(\@_);
916 printf("\t%*s = $reg_format\n", $max_register_name_len, $reg_name, $reg_val);
/external/mesa3d/src/gallium/drivers/iris/
Diris_state.c688 uint32_t reg_val; in init_glk_barrier_mode() local
689 iris_pack_state(GENX(SLICE_COMMON_ECO_CHICKEN1), &reg_val, reg) { in init_glk_barrier_mode()
693 iris_emit_lri(batch, SLICE_COMMON_ECO_CHICKEN1, reg_val); in init_glk_barrier_mode()
748 uint32_t reg_val; in iris_emit_l3_config() local
759 iris_pack_state(L3_ALLOCATION_REG, &reg_val, reg) { in iris_emit_l3_config()
782 _iris_emit_lri(batch, L3_ALLOCATION_REG_num, reg_val); in iris_emit_l3_config()
789 uint32_t reg_val; in iris_enable_obj_preemption() local
797 iris_pack_state(GENX(CS_CHICKEN1), &reg_val, reg) { in iris_enable_obj_preemption()
801 iris_emit_lri(batch, CS_CHICKEN1, reg_val); in iris_enable_obj_preemption()
919 uint32_t reg_val; in iris_init_common_context() local
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/external/llvm-project/lldb/source/Plugins/LanguageRuntime/RenderScript/RenderScriptRuntime/
DRenderScriptRuntime.cpp197 RegisterValue reg_val; in GetArgsX86_64() local
198 if (ctx.reg_ctx->ReadRegister(reg, reg_val)) in GetArgsX86_64()
199 arg.value = reg_val.GetAsUInt64(0, &success); in GetArgsX86_64()
241 RegisterValue reg_val; in GetArgsArm() local
242 if (ctx.reg_ctx->ReadRegister(reg, reg_val)) in GetArgsArm()
243 arg.value = reg_val.GetAsUInt32(0, &success); in GetArgsArm()
280 RegisterValue reg_val; in GetArgsAarch64() local
281 if (ctx.reg_ctx->ReadRegister(reg, reg_val)) in GetArgsAarch64()
282 arg.value = reg_val.GetAsUInt64(0, &success); in GetArgsAarch64()
320 RegisterValue reg_val; in GetArgsMipsel() local
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/external/llvm-project/lldb/source/Plugins/ABI/PowerPC/
DABISysV_ppc64.cpp457 RegisterValue reg_val; in GetRawData() local
458 if (!m_reg_ctx->ReadRegister(reg_info, reg_val)) { in GetRawData()
464 uint32_t rc = reg_val.GetAsMemoryData( in GetRawData()
/external/llvm-project/lldb/source/Target/
DRegisterContextUnwind.cpp303 addr_t reg_val; in InitializeNonZerothFrame() local
304 if (ReadGPRValue(eRegisterKindGeneric, LLDB_REGNUM_GENERIC_FP, reg_val)) in InitializeNonZerothFrame()
305 UnwindLogMsg("fp = 0x%" PRIx64, reg_val); in InitializeNonZerothFrame()
306 if (ReadGPRValue(eRegisterKindGeneric, LLDB_REGNUM_GENERIC_SP, reg_val)) in InitializeNonZerothFrame()
307 UnwindLogMsg("sp = 0x%" PRIx64, reg_val); in InitializeNonZerothFrame()
/external/llvm-project/lldb/source/Plugins/Instruction/ARM/
DEmulateInstructionARM.cpp2899 uint32_t reg_val = ReadCoreReg(Bits32(opcode, 2, 0), &success); in EmulateCB() local
2922 if (m_ignore_conditions || (nonzero ^ (reg_val == 0))) in EmulateCB()
3323 uint32_t reg_val = ReadCoreReg(Rn, &success); in EmulateCMNImm() local
3327 AddWithCarryResult res = AddWithCarry(reg_val, imm32, 0); in EmulateCMNImm()
3440 uint32_t reg_val = ReadCoreReg(Rn, &success); in EmulateCMPImm() local
3444 AddWithCarryResult res = AddWithCarry(reg_val, ~imm32, 1); in EmulateCMPImm()
9215 uint32_t reg_val = ReadCoreReg(Rn, &success); in EmulateRSBImm() local
9219 AddWithCarryResult res = AddWithCarry(~reg_val, imm32, 1); in EmulateRSBImm()
9352 uint32_t reg_val = ReadCoreReg(Rn, &success); in EmulateRSCImm() local
9356 AddWithCarryResult res = AddWithCarry(~reg_val, imm32, APSR_C); in EmulateRSCImm()
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/external/mesa3d/src/gallium/drivers/r600/
Devergreen_state.c4793 uint32_t reg_val = (base_reg_0 + atomic->hw_idx * 4 - EVERGREEN_CONTEXT_REG_OFFSET) >> 2; in evergreen_emit_set_append_cnt() local
4796 radeon_emit(cs, (reg_val << 16) | 0x3); in evergreen_emit_set_append_cnt()
4816 uint32_t reg_val = (base_reg_0 + atomic->hw_idx * 4) >> 2; in evergreen_emit_event_write_eos() local
4825 radeon_emit(cs, reg_val); in evergreen_emit_event_write_eos()
/external/cpuinfo/test/dmesg/
Dmeizu-pro-7-plus.log607 [ 0.576327] (5)[1:swapper/0][mt6335_get_auxadc_value] ch = 2, reg_val = 0x663, raw_data = 13111…
4666 [ 9.654302] (6)[419:cameraserver]twl ldo ldo4 enable! selector:2, voltage:2800000, reg_val:92.
4678 [ 9.655267] (7)[419:cameraserver]twl ldo ldo5 enable! selector:2, voltage:2800000, reg_val:92.
4689 [ 9.656199] (7)[419:cameraserver]twl ldo buck2 enable! selector:1, voltage:1100000, reg_val:40.
4701 [ 9.657120] (5)[419:cameraserver]twl ldo ldo3 enable! selector:1, voltage:1800000, reg_val:52.
4901 [ 10.175716] (0)[419:cameraserver]twl ldo ldo1 enable selector:2, voltage:2800000, reg_val:92.
4913 [ 10.176987] (3)[419:cameraserver]twl ldo ldo2 enable! selector:2, voltage:2800000, reg_val:92.
4924 [ 10.178073] (7)[419:cameraserver]twl ldo buck1 enable! selector:1, voltage:1100000, reg_val:40.
4936 [ 10.179075] (7)[419:cameraserver]twl ldo ldo3 enable! selector:1, voltage:1800000, reg_val:52.
Dhuawei-p9-lite.log1413 …oader_log: [3656 ms]cmdline: is_update_mode flag: 0x00000000, reg_val: 0x00000000, !reg_val: 0x000…
2205 …oader_log: [3636 ms]cmdline: is_update_mode flag: 0x00000000, reg_val: 0x00000000, !reg_val: 0x000…
3445 …oader_log: [3656 ms]cmdline: is_update_mode flag: 0x00000000, reg_val: 0x00000000, !reg_val: 0x000…

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