| /external/vixl/src/aarch32/ |
| D | instructions-aarch32.cc | 156 std::ostream& operator<<(std::ostream& os, SRegisterList reglist) { in operator <<() argument
157 SRegister first = reglist.GetFirstSRegister(); in operator <<()
158 SRegister last = reglist.GetLastSRegister(); in operator <<()
167 std::ostream& operator<<(std::ostream& os, DRegisterList reglist) { in operator <<() argument
168 DRegister first = reglist.GetFirstDRegister(); in operator <<()
169 DRegister last = reglist.GetLastDRegister(); in operator <<()
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMInstrThumb.td | 768 def tLDMIA : T1I<(outs), (ins tGPR:$Rn, pred:$p, reglist:$regs, variable_ops),
783 PseudoInstExpansion<(tLDMIA tGPR:$Rn, pred:$p, reglist:$regs)> {
786 let InOperandList = (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops);
796 (ins tGPR:$Rn, pred:$p, reglist:$regs, variable_ops),
809 (tLDMIA tGPR:$Rn, pred:$p, reglist:$regs), 0>,
813 def tPOP : T1I<(outs), (ins pred:$p, reglist:$regs, variable_ops),
823 def tPUSH : T1I<(outs), (ins pred:$p, reglist:$regs, variable_ops),
1531 def tPOP_RET : tPseudoExpand<(outs), (ins pred:$p, reglist:$regs, variable_ops),
1533 (tPOP pred:$p, reglist:$regs)>, Sched<[WriteBrL]>;
|
| D | ARMInstrThumb2.td | 1709 T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1724 T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1739 T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1754 T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1778 T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1796 T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1814 T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1832 T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3520 reglist:$regs, variable_ops),
3522 (t2LDMIA_UPD GPR:$wb, GPR:$Rn, pred:$p, reglist:$regs)>,
[all …]
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| D | ARMInstrInfo.td | 456 def reglist : Operand<i32> {
3131 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3140 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3151 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3160 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3171 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3180 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3191 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3200 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3230 reglist:$regs, variable_ops),
[all …]
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMInstrThumb.td | 805 def tLDMIA : T1I<(outs), (ins tGPR:$Rn, pred:$p, reglist:$regs, variable_ops),
820 PseudoInstExpansion<(tLDMIA tGPR:$Rn, pred:$p, reglist:$regs)> {
823 let InOperandList = (ins tGPR:$Rn, pred:$p, reglist:$regs, variable_ops);
833 (ins tGPR:$Rn, pred:$p, reglist:$regs, variable_ops),
846 (tLDMIA tGPR:$Rn, pred:$p, reglist:$regs), 0>,
851 def tPOP : T1I<(outs), (ins pred:$p, reglist:$regs, variable_ops),
861 def tPUSH : T1I<(outs), (ins pred:$p, reglist:$regs, variable_ops),
1717 def tPOP_RET : tPseudoExpand<(outs), (ins pred:$p, reglist:$regs, variable_ops),
1719 (tPOP pred:$p, reglist:$regs)>, Sched<[WriteBrL]>;
|
| D | ARMInstrThumb2.td | 1903 T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1918 T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1933 T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1948 T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1972 T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1990 T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2008 T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2026 T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3744 reglist:$regs, variable_ops),
3746 (t2LDMIA_UPD GPR:$wb, GPR:$Rn, pred:$p, reglist:$regs)>,
[all …]
|
| D | ARMInstrInfo.td | 462 def reglist : Operand<i32> {
3288 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3297 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3308 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3317 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3328 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3337 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3348 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3357 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3387 reglist:$regs, variable_ops),
[all …]
|
| /external/llvm-project/llvm/lib/Target/ARM/ |
| D | ARMInstrThumb.td | 817 def tLDMIA : T1I<(outs), (ins tGPR:$Rn, pred:$p, reglist:$regs, variable_ops),
832 PseudoInstExpansion<(tLDMIA tGPR:$Rn, pred:$p, reglist:$regs)> {
835 let InOperandList = (ins tGPR:$Rn, pred:$p, reglist:$regs, variable_ops);
845 (ins tGPR:$Rn, pred:$p, reglist:$regs, variable_ops),
858 (tLDMIA tGPR:$Rn, pred:$p, reglist:$regs), 0>,
863 def tPOP : T1I<(outs), (ins pred:$p, reglist:$regs, variable_ops),
873 def tPUSH : T1I<(outs), (ins pred:$p, reglist:$regs, variable_ops),
1729 def tPOP_RET : tPseudoExpand<(outs), (ins pred:$p, reglist:$regs, variable_ops),
1731 (tPOP pred:$p, reglist:$regs)>, Sched<[WriteBrL]>;
|
| D | ARMInstrThumb2.td | 1952 T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1967 T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1982 T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1997 T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2021 T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2039 T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2057 T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2075 T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3813 reglist:$regs, variable_ops),
3815 (t2LDMIA_UPD GPR:$wb, GPR:$Rn, pred:$p, reglist:$regs)>,
[all …]
|
| D | ARMInstrInfo.td | 575 def reglist : Operand<i32> {
3422 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3431 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3442 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3451 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3462 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3471 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3482 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3491 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3521 reglist:$regs, variable_ops),
[all …]
|
| /external/llvm/lib/Target/Mips/ |
| D | MicroMipsInstrInfo.td | 527 def reglist : Operand<i32> {
550 InstSE<(outs), (ins reglist:$rt, mem_mm_12:$addr),
558 InstSE<(outs reglist:$rt), (ins mem_mm_12:$addr),
814 MipsAsmPseudoInst<(outs reglist:$rt), (ins mem_mm_12:$addr),
818 MipsAsmPseudoInst<(outs), (ins reglist:$rt, mem_mm_12:$addr),
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| D | MicroMipsInstrInfo.td | 522 def reglist : Operand<i32> {
545 InstSE<(outs), (ins reglist:$rt, mem_mm_12:$addr),
553 InstSE<(outs reglist:$rt), (ins mem_mm_12:$addr),
893 MipsAsmPseudoInst<(outs reglist:$rt), (ins mem_mm_12:$addr),
897 MipsAsmPseudoInst<(outs), (ins reglist:$rt, mem_mm_12:$addr),
|
| /external/llvm-project/llvm/lib/Target/Mips/ |
| D | MicroMipsInstrInfo.td | 522 def reglist : Operand<i32> {
545 InstSE<(outs), (ins reglist:$rt, mem_mm_12:$addr),
553 InstSE<(outs reglist:$rt), (ins mem_mm_12:$addr),
893 MipsAsmPseudoInst<(outs reglist:$rt), (ins mem_mm_12:$addr),
897 MipsAsmPseudoInst<(outs), (ins reglist:$rt, mem_mm_12:$addr),
|
| /external/capstone/arch/M68K/ |
| D | M68KDisassembler.c | 1908 uint reglist = extension & 0xff; in fmovem() local
1926 op_reglist->reg = M68K_REG_D0 + ((reglist >> 4) & 7); in fmovem()
1932 op_reglist->register_bits = reglist << 16; in fmovem()
1938 op_reglist->register_bits = ((uint32_t)reverse_bits_8(reglist)) << 16; in fmovem()
|
| /external/llvm-project/llvm/lib/Target/ARM/Disassembler/ |
| D | ARMDisassembler.cpp | 2243 unsigned reglist = fieldFromInstruction(Insn, 0, 16); in DecodeMemMultipleWritebackInstruction() local
2321 if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder))) in DecodeMemMultipleWritebackInstruction()
6118 unsigned reglist = (fieldFromInstruction(Insn, 1, 7) << 1) | in DecodeVSCCLRM() local
6121 if (!Check(S, DecodeDPRRegListOperand(Inst, reglist, Address, Decoder))) { in DecodeVSCCLRM()
6125 unsigned reglist = fieldFromInstruction(Insn, 0, 8) | in DecodeVSCCLRM() local
6128 if (!Check(S, DecodeSPRRegListOperand(Inst, reglist, Address, Decoder))) { in DecodeVSCCLRM()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/Disassembler/ |
| D | ARMDisassembler.cpp | 2222 unsigned reglist = fieldFromInstruction(Insn, 0, 16); in DecodeMemMultipleWritebackInstruction() local
2300 if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder))) in DecodeMemMultipleWritebackInstruction()
6078 unsigned reglist = (fieldFromInstruction(Insn, 1, 7) << 1) | in DecodeVSCCLRM() local
6081 if (!Check(S, DecodeDPRRegListOperand(Inst, reglist, Address, Decoder))) { in DecodeVSCCLRM()
6085 unsigned reglist = fieldFromInstruction(Insn, 0, 8) | in DecodeVSCCLRM() local
6088 if (!Check(S, DecodeSPRRegListOperand(Inst, reglist, Address, Decoder))) { in DecodeVSCCLRM()
|
| /external/capstone/arch/ARM/ |
| D | ARMGenAsmWriter.inc | 8918 // (LDMIA_UPD SP, pred:$p, reglist:$regs)
9146 // (STMDB_UPD SP, pred:$p, reglist:$regs)
10743 // (t2LDMDB GPR:$Rn, pred:$p, reglist:$regs)
10752 // (t2LDMDB_UPD GPR:$Rn, pred:$p, reglist:$regs)
10761 // (t2LDMIA GPR:$Rn, pred:$p, reglist:$regs)
10770 // (t2LDMIA_UPD GPR:$Rn, pred:$p, reglist:$regs)
11363 // (t2STMDB GPR:$Rn, pred:$p, reglist:$regs)
11372 // (t2STMDB_UPD GPR:$Rn, pred:$p, reglist:$regs)
11381 // (t2STMIA_UPD GPR:$Rn, pred:$p, reglist:$regs)
11799 // (tLDMIA tGPR:$Rn, pred:$p, reglist:$regs)
|
| D | ARMDisassembler.c | 1924 unsigned reglist = fieldFromInstruction_4(Insn, 0, 16); in DecodeMemMultipleWritebackInstruction() local
2001 if (!Check(&S, DecodeRegListOperand(Inst, reglist, Address, Decoder))) in DecodeMemMultipleWritebackInstruction()
|
| /external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/ARM/ |
| D | ARMGenInstrInfo.inc | 14732 reglist = 203,
19316 OpTypes::GPR, OpTypes::GPR, OpTypes::i32imm, OpTypes::i32imm, OpTypes::reglist,
19628 OpTypes::GPR, OpTypes::GPR, OpTypes::i32imm, OpTypes::i32imm, OpTypes::reglist,
19682 OpTypes::tGPR, OpTypes::tGPR, OpTypes::i32imm, OpTypes::i32imm, OpTypes::reglist,
19692 OpTypes::i32imm, OpTypes::i32imm, OpTypes::reglist,
19804 OpTypes::GPR, OpTypes::i32imm, OpTypes::i32imm, OpTypes::reglist,
19805 OpTypes::GPR, OpTypes::GPR, OpTypes::i32imm, OpTypes::i32imm, OpTypes::reglist,
19806 OpTypes::GPR, OpTypes::i32imm, OpTypes::i32imm, OpTypes::reglist,
19807 OpTypes::GPR, OpTypes::GPR, OpTypes::i32imm, OpTypes::i32imm, OpTypes::reglist,
19808 OpTypes::GPR, OpTypes::i32imm, OpTypes::i32imm, OpTypes::reglist,
[all …]
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| /external/llvm/lib/Target/ARM/Disassembler/ |
| D | ARMDisassembler.cpp | 1870 unsigned reglist = fieldFromInstruction(Insn, 0, 16); in DecodeMemMultipleWritebackInstruction() local
1948 if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder))) in DecodeMemMultipleWritebackInstruction()
|
| /external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/Mips/ |
| D | MipsGenInstrInfo.inc | 10671 reglist = 64,
14003 OpTypes::reglist, -1, OpTypes::simm12,
14164 OpTypes::reglist, -1, OpTypes::simm12,
15415 OpTypes::reglist, -1, OpTypes::simm12,
16214 OpTypes::reglist, -1, OpTypes::simm12,
|