| /external/eigen/test/ |
| D | schur_real.cpp | 70 RealSchur<MatrixType> rs3; in schur() local
71 rs3.setMaxIterations(RealSchur<MatrixType>::m_maxIterationsPerRow * size).compute(A); in schur()
72 VERIFY_IS_EQUAL(rs3.info(), Success); in schur()
73 VERIFY_IS_EQUAL(rs3.matrixT(), rs1.matrixT()); in schur()
74 VERIFY_IS_EQUAL(rs3.matrixU(), rs1.matrixU()); in schur()
76 rs3.setMaxIterations(1).compute(A); in schur()
77 VERIFY_IS_EQUAL(rs3.info(), NoConvergence); in schur()
78 VERIFY_IS_EQUAL(rs3.getMaxIterations(), 1); in schur()
83 rs3.setMaxIterations(1).compute(Atriangular); // triangular matrices do not need any iterations in schur()
84 VERIFY_IS_EQUAL(rs3.info(), Success); in schur()
[all …]
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| /external/llvm-project/llvm/lib/Target/RISCV/ |
| D | RISCVInstrInfoZfh.td | 37 (ins FPR16:$rs1, FPR16:$rs2, FPR16:$rs3, frmarg:$funct3),
38 opcodestr, "$rd, $rs1, $rs2, $rs3, $funct3">;
41 : InstAlias<OpcodeStr#" $rd, $rs1, $rs2, $rs3",
42 (Inst FPR16:$rd, FPR16:$rs1, FPR16:$rs2, FPR16:$rs3, 0b111)>;
288 // fmadd: rs1 * rs2 + rs3
289 def : Pat<(fma FPR16:$rs1, FPR16:$rs2, FPR16:$rs3),
290 (FMADD_H $rs1, $rs2, $rs3, 0b111)>;
292 // fmsub: rs1 * rs2 - rs3
293 def : Pat<(fma FPR16:$rs1, FPR16:$rs2, (fneg FPR16:$rs3)),
294 (FMSUB_H FPR16:$rs1, FPR16:$rs2, FPR16:$rs3, 0b111)>;
[all …]
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| D | RISCVInstrInfoD.td | 35 (ins FPR64:$rs1, FPR64:$rs2, FPR64:$rs3, frmarg:$funct3),
36 opcodestr, "$rd, $rs1, $rs2, $rs3, $funct3">;
39 : InstAlias<OpcodeStr#" $rd, $rs1, $rs2, $rs3",
40 (Inst FPR64:$rd, FPR64:$rs1, FPR64:$rs2, FPR64:$rs3, 0b111)>;
268 // fmadd: rs1 * rs2 + rs3
269 def : Pat<(fma FPR64:$rs1, FPR64:$rs2, FPR64:$rs3),
270 (FMADD_D $rs1, $rs2, $rs3, 0b111)>;
272 // fmsub: rs1 * rs2 - rs3
273 def : Pat<(fma FPR64:$rs1, FPR64:$rs2, (fneg FPR64:$rs3)),
274 (FMSUB_D FPR64:$rs1, FPR64:$rs2, FPR64:$rs3, 0b111)>;
[all …]
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| D | RISCVInstrInfoF.td | 53 (ins FPR32:$rs1, FPR32:$rs2, FPR32:$rs3, frmarg:$funct3),
54 opcodestr, "$rd, $rs1, $rs2, $rs3, $funct3">;
57 : InstAlias<OpcodeStr#" $rd, $rs1, $rs2, $rs3",
58 (Inst FPR32:$rd, FPR32:$rs1, FPR32:$rs2, FPR32:$rs3, 0b111)>;
324 // fmadd: rs1 * rs2 + rs3
325 def : Pat<(fma FPR32:$rs1, FPR32:$rs2, FPR32:$rs3),
326 (FMADD_S $rs1, $rs2, $rs3, 0b111)>;
328 // fmsub: rs1 * rs2 - rs3
329 def : Pat<(fma FPR32:$rs1, FPR32:$rs2, (fneg FPR32:$rs3)),
330 (FMSUB_S FPR32:$rs1, FPR32:$rs2, FPR32:$rs3, 0b111)>;
[all …]
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| D | RISCVInstrInfoB.td | 162 (ins GPR:$rs1, GPR:$rs2, GPR:$rs3), opcodestr, argstr> {
171 (ins GPR:$rs1, GPR:$rs3, uimmlog2xlen:$shamt),
190 (ins GPR:$rs1, GPR:$rs3, uimm5:$shamt), opcodestr, argstr> {
250 def CMIX : RVBTernaryR<0b11, 0b001, OPC_OP, "cmix", "$rd, $rs2, $rs1, $rs3">,
252 def CMOV : RVBTernaryR<0b11, 0b101, OPC_OP, "cmov", "$rd, $rs2, $rs1, $rs3">,
254 def FSL : RVBTernaryR<0b10, 0b001, OPC_OP, "fsl", "$rd, $rs1, $rs3, $rs2">,
256 def FSR : RVBTernaryR<0b10, 0b101, OPC_OP, "fsr", "$rd, $rs1, $rs3, $rs2">,
259 "$rd, $rs1, $rs3, $shamt">, Sched<[]>;
407 "fslw", "$rd, $rs1, $rs3, $rs2">, Sched<[]>;
409 "$rd, $rs1, $rs3, $rs2">, Sched<[]>;
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| D | RISCVInstrFormats.td | 203 bits<5> rs3;
209 let Inst{31-27} = rs3;
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/ |
| D | RISCVInstrInfoD.td | 35 (ins FPR64:$rs1, FPR64:$rs2, FPR64:$rs3, frmarg:$funct3),
36 opcodestr, "$rd, $rs1, $rs2, $rs3, $funct3">;
39 : InstAlias<OpcodeStr#" $rd, $rs1, $rs2, $rs3",
40 (Inst FPR64:$rd, FPR64:$rs1, FPR64:$rs2, FPR64:$rs3, 0b111)>;
261 // fmadd: rs1 * rs2 + rs3
262 def : Pat<(fma FPR64:$rs1, FPR64:$rs2, FPR64:$rs3),
263 (FMADD_D $rs1, $rs2, $rs3, 0b111)>;
265 // fmsub: rs1 * rs2 - rs3
266 def : Pat<(fma FPR64:$rs1, FPR64:$rs2, (fneg FPR64:$rs3)),
267 (FMSUB_D FPR64:$rs1, FPR64:$rs2, FPR64:$rs3, 0b111)>;
[all …]
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| D | RISCVInstrInfoF.td | 53 (ins FPR32:$rs1, FPR32:$rs2, FPR32:$rs3, frmarg:$funct3),
54 opcodestr, "$rd, $rs1, $rs2, $rs3, $funct3">;
57 : InstAlias<OpcodeStr#" $rd, $rs1, $rs2, $rs3",
58 (Inst FPR32:$rd, FPR32:$rs1, FPR32:$rs2, FPR32:$rs3, 0b111)>;
318 // fmadd: rs1 * rs2 + rs3
319 def : Pat<(fma FPR32:$rs1, FPR32:$rs2, FPR32:$rs3),
320 (FMADD_S $rs1, $rs2, $rs3, 0b111)>;
322 // fmsub: rs1 * rs2 - rs3
323 def : Pat<(fma FPR32:$rs1, FPR32:$rs2, (fneg FPR32:$rs3)),
324 (FMSUB_S FPR32:$rs1, FPR32:$rs2, FPR32:$rs3, 0b111)>;
[all …]
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| D | RISCVInstrFormats.td | 163 bits<5> rs3;
169 let Inst{31-27} = rs3;
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| /external/elfutils/libcpu/ |
| D | riscv_disasm.c | 551 uint32_t rs3; in riscv_disasm() local
794 rs3 = (word >> 27) & 0x1f; in riscv_disasm()
809 op[3] = FREG (rs3); in riscv_disasm()
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| /external/hyphenation-patterns/nn/ |
| D | hyph-nn.pat.txt | 5121 dtørs3
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| /external/hyphenation-patterns/nb/ |
| D | hyph-nb.pat.txt | 5121 dtørs3
|