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/external/llvm-project/llvm/test/CodeGen/X86/GlobalISel/
Dx86_64-legalize-fcmp.mir164 ; CHECK: [[COPY:%[0-9]+]]:_(s128) = COPY $xmm0
165 ; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s128)
166 ; CHECK: [[COPY1:%[0-9]+]]:_(s128) = COPY $xmm1
167 ; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s128)
172 %2:_(s128) = COPY $xmm0
173 %0:_(s32) = G_TRUNC %2(s128)
174 %3:_(s128) = COPY $xmm1
175 %1:_(s32) = G_TRUNC %3(s128)
199 ; CHECK: [[COPY:%[0-9]+]]:_(s128) = COPY $xmm0
200 ; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s128)
[all …]
Dlegalize-fsub-scalar.mir37 ; CHECK: [[COPY:%[0-9]+]]:_(s128) = COPY $xmm0
38 ; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s128)
39 ; CHECK: [[COPY1:%[0-9]+]]:_(s128) = COPY $xmm1
40 ; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s128)
42 ; CHECK: [[ANYEXT:%[0-9]+]]:_(s128) = G_ANYEXT [[FSUB]](s32)
43 ; CHECK: $xmm0 = COPY [[ANYEXT]](s128)
45 %2:_(s128) = COPY $xmm0
46 %0:_(s32) = G_TRUNC %2(s128)
47 %3:_(s128) = COPY $xmm1
48 %1:_(s32) = G_TRUNC %3(s128)
[all …]
Dlegalize-fadd-scalar.mir37 ; CHECK: [[COPY:%[0-9]+]]:_(s128) = COPY $xmm0
38 ; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s128)
39 ; CHECK: [[COPY1:%[0-9]+]]:_(s128) = COPY $xmm1
40 ; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s128)
42 ; CHECK: [[ANYEXT:%[0-9]+]]:_(s128) = G_ANYEXT [[FADD]](s32)
43 ; CHECK: $xmm0 = COPY [[ANYEXT]](s128)
45 %2:_(s128) = COPY $xmm0
46 %0:_(s32) = G_TRUNC %2(s128)
47 %3:_(s128) = COPY $xmm1
48 %1:_(s32) = G_TRUNC %3(s128)
[all …]
Dlegalize-fmul-scalar.mir37 ; CHECK: [[COPY:%[0-9]+]]:_(s128) = COPY $xmm0
38 ; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s128)
39 ; CHECK: [[COPY1:%[0-9]+]]:_(s128) = COPY $xmm1
40 ; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s128)
42 ; CHECK: [[ANYEXT:%[0-9]+]]:_(s128) = G_ANYEXT [[FMUL]](s32)
43 ; CHECK: $xmm0 = COPY [[ANYEXT]](s128)
45 %2:_(s128) = COPY $xmm0
46 %0:_(s32) = G_TRUNC %2(s128)
47 %3:_(s128) = COPY $xmm1
48 %1:_(s32) = G_TRUNC %3(s128)
[all …]
Dlegalize-fdiv-scalar.mir37 ; CHECK: [[COPY:%[0-9]+]]:_(s128) = COPY $xmm0
38 ; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s128)
39 ; CHECK: [[COPY1:%[0-9]+]]:_(s128) = COPY $xmm1
40 ; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s128)
42 ; CHECK: [[ANYEXT:%[0-9]+]]:_(s128) = G_ANYEXT [[FDIV]](s32)
43 ; CHECK: $xmm0 = COPY [[ANYEXT]](s128)
45 %2:_(s128) = COPY $xmm0
46 %0:_(s32) = G_TRUNC %2(s128)
47 %3:_(s128) = COPY $xmm1
48 %1:_(s32) = G_TRUNC %3(s128)
[all …]
Dregbankselect-X86_64.mir677 ; FAST: [[COPY:%[0-9]+]]:vecr(s128) = COPY $xmm0
678 ; FAST: [[TRUNC:%[0-9]+]]:vecr(s32) = G_TRUNC [[COPY]](s128)
679 ; FAST: [[COPY1:%[0-9]+]]:vecr(s128) = COPY $xmm1
680 ; FAST: [[TRUNC1:%[0-9]+]]:vecr(s32) = G_TRUNC [[COPY1]](s128)
682 ; FAST: [[ANYEXT:%[0-9]+]]:vecr(s128) = G_ANYEXT [[FADD]](s32)
683 ; FAST: $xmm0 = COPY [[ANYEXT]](s128)
687 ; GREEDY: [[COPY:%[0-9]+]]:vecr(s128) = COPY $xmm0
688 ; GREEDY: [[TRUNC:%[0-9]+]]:vecr(s32) = G_TRUNC [[COPY]](s128)
689 ; GREEDY: [[COPY1:%[0-9]+]]:vecr(s128) = COPY $xmm1
690 ; GREEDY: [[TRUNC1:%[0-9]+]]:vecr(s32) = G_TRUNC [[COPY1]](s128)
[all …]
Dx86_64-legalize-fptosi.mir69 ; CHECK: [[COPY:%[0-9]+]]:_(s128) = COPY $xmm0
70 ; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s128)
75 %1:_(s128) = COPY $xmm0
76 %0:_(s32) = G_TRUNC %1(s128)
96 ; CHECK: [[COPY:%[0-9]+]]:_(s128) = COPY $xmm0
97 ; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s128)
102 %1:_(s128) = COPY $xmm0
103 %0:_(s32) = G_TRUNC %1(s128)
123 ; CHECK: [[COPY:%[0-9]+]]:_(s128) = COPY $xmm0
124 ; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s128)
[all …]
Dx86_64-select-fcmp.mir177 %2:vecr(s128) = COPY $xmm0
178 %0:vecr(s32) = G_TRUNC %2(s128)
179 %3:vecr(s128) = COPY $xmm1
180 %1:vecr(s32) = G_TRUNC %3(s128)
215 %2:vecr(s128) = COPY $xmm0
216 %0:vecr(s32) = G_TRUNC %2(s128)
217 %3:vecr(s128) = COPY $xmm1
218 %1:vecr(s32) = G_TRUNC %3(s128)
253 %2:vecr(s128) = COPY $xmm0
254 %0:vecr(s32) = G_TRUNC %2(s128)
[all …]
Dx86_64-legalize-sitofp.mir97 ; CHECK: [[ANYEXT:%[0-9]+]]:_(s128) = G_ANYEXT [[SITOFP]](s32)
98 ; CHECK: $xmm0 = COPY [[ANYEXT]](s128)
103 %3:_(s128) = G_ANYEXT %2(s32)
104 $xmm0 = COPY %3(s128)
130 ; CHECK: [[ANYEXT:%[0-9]+]]:_(s128) = G_ANYEXT [[SITOFP]](s32)
131 ; CHECK: $xmm0 = COPY [[ANYEXT]](s128)
136 %3:_(s128) = G_ANYEXT %2(s32)
137 $xmm0 = COPY %3(s128)
157 ; CHECK: [[ANYEXT:%[0-9]+]]:_(s128) = G_ANYEXT [[SITOFP]](s32)
158 ; CHECK: $xmm0 = COPY [[ANYEXT]](s128)
[all …]
Dlegalize-fptrunc-scalar.mir26 ; ALL: [[COPY:%[0-9]+]]:_(s128) = COPY $xmm0
27 ; ALL: [[TRUNC:%[0-9]+]]:_(s64) = G_TRUNC [[COPY]](s128)
29 ; ALL: [[ANYEXT:%[0-9]+]]:_(s128) = G_ANYEXT [[FPTRUNC]](s32)
30 ; ALL: $xmm0 = COPY [[ANYEXT]](s128)
32 %1:_(s128) = COPY $xmm0
33 %0:_(s64) = G_TRUNC %1(s128)
35 %3:_(s128) = G_ANYEXT %2(s32)
36 $xmm0 = COPY %3(s128)
Dlegalize-fpext-scalar.mir27 ; ALL: [[COPY:%[0-9]+]]:_(s128) = COPY $xmm0
28 ; ALL: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s128)
30 ; ALL: [[ANYEXT:%[0-9]+]]:_(s128) = G_ANYEXT [[FPEXT]](s64)
31 ; ALL: $xmm0 = COPY [[ANYEXT]](s128)
33 %1:_(s128) = COPY $xmm0
34 %0:_(s32) = G_TRUNC %1(s128)
36 %3:_(s128) = G_ANYEXT %2(s64)
37 $xmm0 = COPY %3(s128)
Dx86_64-select-fptosi.mir78 %1:vecr(s128) = COPY $xmm0
79 %0:vecr(s32) = G_TRUNC %1(s128)
109 %1:vecr(s128) = COPY $xmm0
110 %0:vecr(s32) = G_TRUNC %1(s128)
138 %1:vecr(s128) = COPY $xmm0
139 %0:vecr(s32) = G_TRUNC %1(s128)
166 %1:vecr(s128) = COPY $xmm0
167 %0:vecr(s32) = G_TRUNC %1(s128)
196 %1:vecr(s128) = COPY $xmm0
197 %0:vecr(s64) = G_TRUNC %1(s128)
[all …]
Dselect-fmul-scalar.mir78 %2:vecr(s128) = COPY $xmm0
79 %0:vecr(s32) = G_TRUNC %2(s128)
80 %3:vecr(s128) = COPY $xmm1
81 %1:vecr(s32) = G_TRUNC %3(s128)
83 %5:vecr(s128) = G_ANYEXT %4(s32)
84 $xmm0 = COPY %5(s128)
147 %2:vecr(s128) = COPY $xmm0
148 %0:vecr(s64) = G_TRUNC %2(s128)
149 %3:vecr(s128) = COPY $xmm1
150 %1:vecr(s64) = G_TRUNC %3(s128)
[all …]
Dselect-fadd-scalar.mir78 %2:vecr(s128) = COPY $xmm0
79 %0:vecr(s32) = G_TRUNC %2(s128)
80 %3:vecr(s128) = COPY $xmm1
81 %1:vecr(s32) = G_TRUNC %3(s128)
83 %5:vecr(s128) = G_ANYEXT %4(s32)
84 $xmm0 = COPY %5(s128)
147 %2:vecr(s128) = COPY $xmm0
148 %0:vecr(s64) = G_TRUNC %2(s128)
149 %3:vecr(s128) = COPY $xmm1
150 %1:vecr(s64) = G_TRUNC %3(s128)
[all …]
Dselect-fsub-scalar.mir78 %2:vecr(s128) = COPY $xmm0
79 %0:vecr(s32) = G_TRUNC %2(s128)
80 %3:vecr(s128) = COPY $xmm1
81 %1:vecr(s32) = G_TRUNC %3(s128)
83 %5:vecr(s128) = G_ANYEXT %4(s32)
84 $xmm0 = COPY %5(s128)
147 %2:vecr(s128) = COPY $xmm0
148 %0:vecr(s64) = G_TRUNC %2(s128)
149 %3:vecr(s128) = COPY $xmm1
150 %1:vecr(s64) = G_TRUNC %3(s128)
[all …]
Dselect-fdiv-scalar.mir78 %2:vecr(s128) = COPY $xmm0
79 %0:vecr(s32) = G_TRUNC %2(s128)
80 %3:vecr(s128) = COPY $xmm1
81 %1:vecr(s32) = G_TRUNC %3(s128)
83 %5:vecr(s128) = G_ANYEXT %4(s32)
84 $xmm0 = COPY %5(s128)
147 %2:vecr(s128) = COPY $xmm0
148 %0:vecr(s64) = G_TRUNC %2(s128)
149 %3:vecr(s128) = COPY $xmm1
150 %1:vecr(s64) = G_TRUNC %3(s128)
[all …]
/external/llvm-project/llvm/test/CodeGen/AArch64/GlobalISel/
Dlegalize-s128-div.mir28 ; CHECK: [[LOAD:%[0-9]+]]:_(s128) = G_LOAD [[COPY]](p0) :: (load 16 from %ir.v1ptr)
29 ; CHECK: [[LOAD1:%[0-9]+]]:_(s128) = G_LOAD [[COPY1]](p0) :: (load 16 from %ir.v2ptr)
31 ; CHECK: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[LOAD]](s128)
32 ; CHECK: [[UV2:%[0-9]+]]:_(s64), [[UV3:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[LOAD1]](s128)
40 ; CHECK: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[COPY2]](s64), [[COPY3]](s64)
42 ; CHECK: G_STORE [[MV]](s128), [[COPY]](p0) :: (store 16 into %ir.v1ptr)
46 %2:_(s128) = G_LOAD %0(p0) :: (load 16 from %ir.v1ptr)
47 %3:_(s128) = G_LOAD %1(p0) :: (load 16 from %ir.v2ptr)
48 %4:_(s128) = G_UDIV %2, %3
49 G_STORE %4(s128), %0(p0) :: (store 16 into %ir.v1ptr)
[all …]
Dlegalize-sext-zext-128.mir16 ; CHECK: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[COPY]](s64), [[ASHR]](s64)
17 ; CHECK: G_STORE [[MV]](s128), [[COPY1]](p0) :: (store 16)
21 %2:_(s128) = G_SEXT %0(s64)
22 G_STORE %2(s128), %1(p0) :: (store 16)
38 ; CHECK: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[COPY]](s64), [[C]](s64)
39 ; CHECK: G_STORE [[MV]](s128), [[COPY1]](p0) :: (store 16)
43 %2:_(s128) = G_ZEXT %0(s64)
44 G_STORE %2(s128), %1(p0) :: (store 16)
62 ; CHECK: [[MV1:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[MV]](s64), [[C1]](s64)
63 ; CHECK: G_STORE [[MV1]](s128), [[COPY1]](p0) :: (store 16)
[all …]
Dinline-memcpy.mir99 ; CHECK: [[LOAD:%[0-9]+]]:_(s128) = G_LOAD [[COPY1]](p0) :: (load 16 from %ir.1, align 4)
100 ; CHECK: G_STORE [[LOAD]](s128), [[COPY]](p0) :: (store 16 into %ir.0, align 4)
103 ; CHECK: [[LOAD1:%[0-9]+]]:_(s128) = G_LOAD [[GEP]](p0) :: (load 16 from %ir.1 + 16, align 4)
105 ; CHECK: G_STORE [[LOAD1]](s128), [[GEP1]](p0) :: (store 16 into %ir.0 + 16, align 4)
108 ; CHECK: [[LOAD2:%[0-9]+]]:_(s128) = G_LOAD [[GEP2]](p0) :: (load 16 from %ir.1 + 32, align 4)
110 ; CHECK: G_STORE [[LOAD2]](s128), [[GEP3]](p0) :: (store 16 into %ir.0 + 32, align 4)
113 ; CHECK: [[LOAD3:%[0-9]+]]:_(s128) = G_LOAD [[GEP4]](p0) :: (load 16 from %ir.1 + 48, align 4)
115 ; CHECK: G_STORE [[LOAD3]](s128), [[GEP5]](p0) :: (store 16 into %ir.0 + 48, align 4)
146 ; CHECK: [[LOAD:%[0-9]+]]:_(s128) = G_LOAD [[COPY1]](p0) :: (load 16 from %ir.1, align 4)
147 ; CHECK: G_STORE [[LOAD]](s128), [[COPY]](p0) :: (store 16 into %ir.0, align 4)
[all …]
Dlegalizer-combiner.mir52 ; CHECK: [[BITCAST:%[0-9]+]]:_(s128) = G_BITCAST [[COPY]](<2 x s64>)
53 ; CHECK: [[BITCAST1:%[0-9]+]]:_(s128) = G_BITCAST [[COPY1]](<2 x s64>)
54 ; CHECK: $q0 = COPY [[BITCAST]](s128)
55 ; CHECK: $q1 = COPY [[BITCAST1]](s128)
59 %3:_(s128), %4:_(s128) = G_UNMERGE_VALUES %2(<4 x s64>)
60 $q0 = COPY %3(s128)
61 $q1 = COPY %4(s128)
105 ; CHECK: [[LOAD1:%[0-9]+]]:_(s128) = G_LOAD [[COPY]](p0) :: (load 16)
106 ; CHECK: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[LOAD1]](s128)
113 ; CHECK: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[MUL]](s64), [[ADD1]](s64)
[all …]
/external/llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/
Dlegalize-shl.mir970 ; SI: [[COPY:%[0-9]+]]:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
975 ; SI: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](s128)
988 ; SI: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[SELECT]](s64), [[SELECT2]](s64)
989 ; SI: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[MV]](s128)
991 ; VI: [[COPY:%[0-9]+]]:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
996 ; VI: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](s128)
1009 ; VI: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[SELECT]](s64), [[SELECT2]](s64)
1010 ; VI: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[MV]](s128)
1012 ; GFX9: [[COPY:%[0-9]+]]:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
1017 ; GFX9: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](s128)
[all …]
Dlegalize-insert.mir109 ; CHECK: [[COPY:%[0-9]+]]:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
111 ; CHECK: [[INSERT:%[0-9]+]]:_(s128) = G_INSERT [[COPY]], [[COPY1]](s32), 0
112 ; CHECK: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[INSERT]](s128)
113 %0:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
115 %2:_(s128) = G_INSERT %0, %1, 0
125 ; CHECK: [[COPY:%[0-9]+]]:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
127 ; CHECK: [[INSERT:%[0-9]+]]:_(s128) = G_INSERT [[COPY]], [[COPY1]](s32), 32
128 ; CHECK: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[INSERT]](s128)
129 %0:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
131 %2:_(s128) = G_INSERT %0, %1, 32
[all …]
Dlegalize-ashr.mir1045 ; SI: [[COPY:%[0-9]+]]:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
1050 ; SI: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](s128)
1065 ; SI: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[SELECT1]](s64), [[SELECT2]](s64)
1066 ; SI: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[MV]](s128)
1068 ; VI: [[COPY:%[0-9]+]]:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
1073 ; VI: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](s128)
1088 ; VI: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[SELECT1]](s64), [[SELECT2]](s64)
1089 ; VI: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[MV]](s128)
1091 ; GFX9: [[COPY:%[0-9]+]]:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
1096 ; GFX9: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](s128)
[all …]
Dlegalize-lshr.mir1048 ; SI: [[COPY:%[0-9]+]]:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
1053 ; SI: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](s128)
1066 ; SI: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[SELECT1]](s64), [[SELECT2]](s64)
1067 ; SI: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[MV]](s128)
1069 ; VI: [[COPY:%[0-9]+]]:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
1074 ; VI: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](s128)
1087 ; VI: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[SELECT1]](s64), [[SELECT2]](s64)
1088 ; VI: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[MV]](s128)
1090 ; GFX9: [[COPY:%[0-9]+]]:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
1095 ; GFX9: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](s128)
[all …]
Dartifact-combiner-trunc.mir54 %2:_(s128) = G_MERGE_VALUES %0, %1, %0, %1
68 ; CHECK: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[C]](p0), [[C1]](p0)
69 ; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[MV]](s128)
73 %2:_(s128) = G_MERGE_VALUES %0, %1
87 ; CHECK: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[C]](p0), [[C1]](p0)
88 ; CHECK: [[TRUNC:%[0-9]+]]:_(s64) = G_TRUNC [[MV]](s128)
92 %2:_(s128) = G_MERGE_VALUES %0, %1
107 ; CHECK: [[TRUNC:%[0-9]+]]:_(s128) = G_TRUNC [[MV]](s192)
108 ; CHECK: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[TRUNC]](s128)
112 %3:_(s128) = G_TRUNC %2
[all …]

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