1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2# RUN: llc -mtriple=x86_64-linux-gnu -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s 3 4--- | 5 6 define signext i8 @float_to_int8(float %val) { 7 entry: 8 %conv = fptosi float %val to i8 9 ret i8 %conv 10 } 11 12 define signext i16 @float_to_int16(float %val) { 13 entry: 14 %conv = fptosi float %val to i16 15 ret i16 %conv 16 } 17 18 define i32 @float_to_int32(float %val) { 19 entry: 20 %conv = fptosi float %val to i32 21 ret i32 %conv 22 } 23 24 define i64 @float_to_int64(float %val) { 25 entry: 26 %conv = fptosi float %val to i64 27 ret i64 %conv 28 } 29 30 define signext i8 @double_to_int8(double %val) { 31 entry: 32 %conv = fptosi double %val to i8 33 ret i8 %conv 34 } 35 36 define signext i16 @double_to_int16(double %val) { 37 entry: 38 %conv = fptosi double %val to i16 39 ret i16 %conv 40 } 41 42 define i32 @double_to_int32(double %val) { 43 entry: 44 %conv = fptosi double %val to i32 45 ret i32 %conv 46 } 47 48 define i64 @double_to_int64(double %val) { 49 entry: 50 %conv = fptosi double %val to i64 51 ret i64 %conv 52 } 53 54... 55--- 56name: float_to_int8 57alignment: 16 58legalized: true 59regBankSelected: true 60tracksRegLiveness: true 61registers: 62 - { id: 0, class: vecr } 63 - { id: 1, class: vecr } 64 - { id: 2, class: gpr } 65 - { id: 3, class: gpr } 66body: | 67 bb.1.entry: 68 liveins: $xmm0 69 70 ; CHECK-LABEL: name: float_to_int8 71 ; CHECK: liveins: $xmm0 72 ; CHECK: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0 73 ; CHECK: [[COPY1:%[0-9]+]]:fr32 = COPY [[COPY]] 74 ; CHECK: %3:gr32 = nofpexcept CVTTSS2SIrr [[COPY1]], implicit $mxcsr 75 ; CHECK: [[COPY2:%[0-9]+]]:gr8 = COPY %3.sub_8bit 76 ; CHECK: $al = COPY [[COPY2]] 77 ; CHECK: RET 0, implicit $al 78 %1:vecr(s128) = COPY $xmm0 79 %0:vecr(s32) = G_TRUNC %1(s128) 80 %3:gpr(s32) = G_FPTOSI %0(s32) 81 %2:gpr(s8) = G_TRUNC %3(s32) 82 $al = COPY %2(s8) 83 RET 0, implicit $al 84 85... 86--- 87name: float_to_int16 88alignment: 16 89legalized: true 90regBankSelected: true 91tracksRegLiveness: true 92registers: 93 - { id: 0, class: vecr } 94 - { id: 1, class: vecr } 95 - { id: 2, class: gpr } 96 - { id: 3, class: gpr } 97body: | 98 bb.1.entry: 99 liveins: $xmm0 100 101 ; CHECK-LABEL: name: float_to_int16 102 ; CHECK: liveins: $xmm0 103 ; CHECK: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0 104 ; CHECK: [[COPY1:%[0-9]+]]:fr32 = COPY [[COPY]] 105 ; CHECK: %3:gr32 = nofpexcept CVTTSS2SIrr [[COPY1]], implicit $mxcsr 106 ; CHECK: [[COPY2:%[0-9]+]]:gr16 = COPY %3.sub_16bit 107 ; CHECK: $ax = COPY [[COPY2]] 108 ; CHECK: RET 0, implicit $ax 109 %1:vecr(s128) = COPY $xmm0 110 %0:vecr(s32) = G_TRUNC %1(s128) 111 %3:gpr(s32) = G_FPTOSI %0(s32) 112 %2:gpr(s16) = G_TRUNC %3(s32) 113 $ax = COPY %2(s16) 114 RET 0, implicit $ax 115 116... 117--- 118name: float_to_int32 119alignment: 16 120legalized: true 121regBankSelected: true 122tracksRegLiveness: true 123registers: 124 - { id: 0, class: vecr } 125 - { id: 1, class: vecr } 126 - { id: 2, class: gpr } 127body: | 128 bb.1.entry: 129 liveins: $xmm0 130 131 ; CHECK-LABEL: name: float_to_int32 132 ; CHECK: liveins: $xmm0 133 ; CHECK: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0 134 ; CHECK: [[COPY1:%[0-9]+]]:fr32 = COPY [[COPY]] 135 ; CHECK: %2:gr32 = nofpexcept CVTTSS2SIrr [[COPY1]], implicit $mxcsr 136 ; CHECK: $eax = COPY %2 137 ; CHECK: RET 0, implicit $eax 138 %1:vecr(s128) = COPY $xmm0 139 %0:vecr(s32) = G_TRUNC %1(s128) 140 %2:gpr(s32) = G_FPTOSI %0(s32) 141 $eax = COPY %2(s32) 142 RET 0, implicit $eax 143 144... 145--- 146name: float_to_int64 147alignment: 16 148legalized: true 149regBankSelected: true 150tracksRegLiveness: true 151registers: 152 - { id: 0, class: vecr } 153 - { id: 1, class: vecr } 154 - { id: 2, class: gpr } 155body: | 156 bb.1.entry: 157 liveins: $xmm0 158 159 ; CHECK-LABEL: name: float_to_int64 160 ; CHECK: liveins: $xmm0 161 ; CHECK: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0 162 ; CHECK: [[COPY1:%[0-9]+]]:fr32 = COPY [[COPY]] 163 ; CHECK: %2:gr64 = nofpexcept CVTTSS2SI64rr [[COPY1]], implicit $mxcsr 164 ; CHECK: $rax = COPY %2 165 ; CHECK: RET 0, implicit $rax 166 %1:vecr(s128) = COPY $xmm0 167 %0:vecr(s32) = G_TRUNC %1(s128) 168 %2:gpr(s64) = G_FPTOSI %0(s32) 169 $rax = COPY %2(s64) 170 RET 0, implicit $rax 171 172... 173--- 174name: double_to_int8 175alignment: 16 176legalized: true 177regBankSelected: true 178tracksRegLiveness: true 179registers: 180 - { id: 0, class: vecr } 181 - { id: 1, class: vecr } 182 - { id: 2, class: gpr } 183 - { id: 3, class: gpr } 184body: | 185 bb.1.entry: 186 liveins: $xmm0 187 188 ; CHECK-LABEL: name: double_to_int8 189 ; CHECK: liveins: $xmm0 190 ; CHECK: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0 191 ; CHECK: [[COPY1:%[0-9]+]]:fr64 = COPY [[COPY]] 192 ; CHECK: %3:gr32 = nofpexcept CVTTSD2SIrr [[COPY1]], implicit $mxcsr 193 ; CHECK: [[COPY2:%[0-9]+]]:gr8 = COPY %3.sub_8bit 194 ; CHECK: $al = COPY [[COPY2]] 195 ; CHECK: RET 0, implicit $al 196 %1:vecr(s128) = COPY $xmm0 197 %0:vecr(s64) = G_TRUNC %1(s128) 198 %3:gpr(s32) = G_FPTOSI %0(s64) 199 %2:gpr(s8) = G_TRUNC %3(s32) 200 $al = COPY %2(s8) 201 RET 0, implicit $al 202 203... 204--- 205name: double_to_int16 206alignment: 16 207legalized: true 208regBankSelected: true 209tracksRegLiveness: true 210registers: 211 - { id: 0, class: vecr } 212 - { id: 1, class: vecr } 213 - { id: 2, class: gpr } 214 - { id: 3, class: gpr } 215body: | 216 bb.1.entry: 217 liveins: $xmm0 218 219 ; CHECK-LABEL: name: double_to_int16 220 ; CHECK: liveins: $xmm0 221 ; CHECK: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0 222 ; CHECK: [[COPY1:%[0-9]+]]:fr64 = COPY [[COPY]] 223 ; CHECK: %3:gr32 = nofpexcept CVTTSD2SIrr [[COPY1]], implicit $mxcsr 224 ; CHECK: [[COPY2:%[0-9]+]]:gr16 = COPY %3.sub_16bit 225 ; CHECK: $ax = COPY [[COPY2]] 226 ; CHECK: RET 0, implicit $ax 227 %1:vecr(s128) = COPY $xmm0 228 %0:vecr(s64) = G_TRUNC %1(s128) 229 %3:gpr(s32) = G_FPTOSI %0(s64) 230 %2:gpr(s16) = G_TRUNC %3(s32) 231 $ax = COPY %2(s16) 232 RET 0, implicit $ax 233 234... 235--- 236name: double_to_int32 237alignment: 16 238legalized: true 239regBankSelected: true 240tracksRegLiveness: true 241registers: 242 - { id: 0, class: vecr } 243 - { id: 1, class: vecr } 244 - { id: 2, class: gpr } 245body: | 246 bb.1.entry: 247 liveins: $xmm0 248 249 ; CHECK-LABEL: name: double_to_int32 250 ; CHECK: liveins: $xmm0 251 ; CHECK: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0 252 ; CHECK: [[COPY1:%[0-9]+]]:fr64 = COPY [[COPY]] 253 ; CHECK: %2:gr32 = nofpexcept CVTTSD2SIrr [[COPY1]], implicit $mxcsr 254 ; CHECK: $eax = COPY %2 255 ; CHECK: RET 0, implicit $eax 256 %1:vecr(s128) = COPY $xmm0 257 %0:vecr(s64) = G_TRUNC %1(s128) 258 %2:gpr(s32) = G_FPTOSI %0(s64) 259 $eax = COPY %2(s32) 260 RET 0, implicit $eax 261 262... 263--- 264name: double_to_int64 265alignment: 16 266legalized: true 267regBankSelected: true 268tracksRegLiveness: true 269registers: 270 - { id: 0, class: vecr } 271 - { id: 1, class: vecr } 272 - { id: 2, class: gpr } 273body: | 274 bb.1.entry: 275 liveins: $xmm0 276 277 ; CHECK-LABEL: name: double_to_int64 278 ; CHECK: liveins: $xmm0 279 ; CHECK: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0 280 ; CHECK: [[COPY1:%[0-9]+]]:fr64 = COPY [[COPY]] 281 ; CHECK: %2:gr64 = nofpexcept CVTTSD2SI64rr [[COPY1]], implicit $mxcsr 282 ; CHECK: $rax = COPY %2 283 ; CHECK: RET 0, implicit $rax 284 %1:vecr(s128) = COPY $xmm0 285 %0:vecr(s64) = G_TRUNC %1(s128) 286 %2:gpr(s64) = G_FPTOSI %0(s64) 287 $rax = COPY %2(s64) 288 RET 0, implicit $rax 289 290... 291