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/external/llvm-project/llvm/test/CodeGen/AArch64/GlobalISel/
Dpostlegalizercombiner-extractvec-faddp.mir16 ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0
17 ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
18 ; CHECK: [[EVEC:%[0-9]+]]:_(s64) = G_EXTRACT_VECTOR_ELT [[COPY]](<2 x s64>), [[C]](s64)
19 ; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
20 ; CHECK: [[EVEC1:%[0-9]+]]:_(s64) = G_EXTRACT_VECTOR_ELT [[COPY]](<2 x s64>), [[C1]](s64)
21 ; CHECK: [[FADD:%[0-9]+]]:_(s64) = G_FADD [[EVEC]], [[EVEC1]]
22 ; CHECK: $d0 = COPY [[FADD]](s64)
24 %0:_(<2 x s64>) = COPY $q0
25 %2:_(<2 x s64>) = G_IMPLICIT_DEF
26 %5:_(s64) = G_CONSTANT i64 0
[all …]
Dlegalize-add.mir8 ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
9 ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
10 ; CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
11 ; CHECK: [[COPY3:%[0-9]+]]:_(s64) = COPY $x3
12 ; CHECK: [[UADDO:%[0-9]+]]:_(s64), [[UADDO1:%[0-9]+]]:_(s1) = G_UADDO [[COPY]], [[COPY2]]
13 …; CHECK: [[UADDE:%[0-9]+]]:_(s64), [[UADDE1:%[0-9]+]]:_(s1) = G_UADDE [[COPY1]], [[COPY3]], [[UADD…
14 ; CHECK: $x0 = COPY [[UADDO]](s64)
15 ; CHECK: $x1 = COPY [[UADDE]](s64)
16 %0:_(s64) = COPY $x0
17 %1:_(s64) = COPY $x1
[all …]
Dprelegalizercombiner-hoist-same-hands.mir18 ; CHECK: %logic_op:_(s64) = G_SEXT [[OR]](s32)
19 ; CHECK: $x0 = COPY %logic_op(s64)
23 %hand1:_(s64) = G_SEXT %x(s32)
24 %hand2:_(s64) = G_SEXT %y(s32)
25 %logic_op:_(s64) = G_OR %hand1, %hand2
26 $x0 = COPY %logic_op(s64)
43 ; CHECK: %logic_op:_(s64) = G_ZEXT [[OR]](s32)
44 ; CHECK: $x0 = COPY %logic_op(s64)
48 %hand1:_(s64) = G_ZEXT %x(s32)
49 %hand2:_(s64) = G_ZEXT %y(s32)
[all …]
Dlegalize-mul.mir8 ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
9 ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
10 ; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
11 ; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
13 ; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[MUL]](s32)
14 ; CHECK: $x0 = COPY [[ANYEXT]](s64)
15 %0:_(s64) = COPY $x0
16 %1:_(s64) = COPY $x1
17 %2:_(s8) = G_TRUNC %0(s64)
18 %3:_(s8) = G_TRUNC %1(s64)
[all …]
Dcombine-copy.mir11 ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
12 ; CHECK: $x0 = COPY [[COPY]](s64)
13 %0:_(s64) = COPY $x0
14 %1:_(s64) = COPY %0(s64)
15 $x0 = COPY %1(s64)
22 ; CHECK: [[COPY:%[0-9]+]]:gpr(s64) = COPY $x0
23 ; CHECK: $x0 = COPY [[COPY]](s64)
24 %0:gpr(s64) = COPY $x0
25 %1:_(s64) = COPY %0(s64)
26 $x0 = COPY %1(s64)
[all …]
Dlegalize-simple.mir9 ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
10 ; CHECK: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[COPY]](s64)
11 ; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
12 ; CHECK: [[INTTOPTR:%[0-9]+]]:_(p0) = G_INTTOPTR [[COPY]](s64)
13 ; CHECK: [[PTRTOINT:%[0-9]+]]:_(s64) = G_PTRTOINT [[INTTOPTR]](p0)
14 ; CHECK: $x0 = COPY [[PTRTOINT]](s64)
17 ; CHECK: [[TRUNC2:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
18 ; CHECK: [[TRUNC3:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
22 ; CHECK: [[TRUNC4:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
23 ; CHECK: [[TRUNC5:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
[all …]
Dlegalizer-combiner.mir39 # vector type (4 x s64) by combining the G_UNMERGE_VALUES
50 ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0
51 ; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $q1
52 ; CHECK: [[BITCAST:%[0-9]+]]:_(s128) = G_BITCAST [[COPY]](<2 x s64>)
53 ; CHECK: [[BITCAST1:%[0-9]+]]:_(s128) = G_BITCAST [[COPY1]](<2 x s64>)
56 %0:_(<2 x s64>) = COPY $q0
57 %1:_(<2 x s64>) = COPY $q1
58 %2:_(<4 x s64>) = G_CONCAT_VECTORS %0(<2 x s64>), %1(<2 x s64>)
59 %3:_(s128), %4:_(s128) = G_UNMERGE_VALUES %2(<4 x s64>)
65 # vector type (4 x s64) by combining the G_UNMERGE_VALUES
[all …]
Dprelegalizercombiner-concat-vectors.mir15 ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
16 ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
17 ; CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
18 ; CHECK: [[COPY3:%[0-9]+]]:_(s64) = COPY $x3
19 …K: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s64>) = G_BUILD_VECTOR [[COPY]](s64), [[COPY1]](s64), [[COPY2]]…
20 ; CHECK: RET_ReallyLR implicit [[BUILD_VECTOR]](<4 x s64>)
21 %0:_(s64) = COPY $x0
22 %1:_(s64) = COPY $x1
23 %2:_(s64) = COPY $x2
24 %3:_(s64) = COPY $x3
[all …]
Dlegalize-dyn-alloca.mir41 ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
42 ; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[COPY]](s32)
43 ; CHECK: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[ZEXT]], [[C]]
44 ; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 15
45 ; CHECK: [[ADD:%[0-9]+]]:_(s64) = nuw G_ADD [[MUL]], [[C1]]
46 ; CHECK: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 -16
47 ; CHECK: [[AND:%[0-9]+]]:_(s64) = G_AND [[ADD]], [[C2]]
49 ; CHECK: [[PTRTOINT:%[0-9]+]]:_(s64) = G_PTRTOINT [[COPY1]](p0)
50 ; CHECK: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[PTRTOINT]], [[AND]]
51 ; CHECK: [[INTTOPTR:%[0-9]+]]:_(p0) = G_INTTOPTR [[SUB]](s64)
[all …]
Dcombine-ext.mir9 ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
10 ; CHECK: $x1 = COPY [[COPY]](s64)
11 %0:_(s64) = COPY $x0
12 %1:_(s32) = G_TRUNC %0(s64)
13 %2:_(s64) = G_ANYEXT %1(s32)
14 $x1 = COPY %2(s64)
22 ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0
23 ; CHECK: $q0 = COPY [[COPY]](<2 x s64>)
24 %0:_(<2 x s64>) = COPY $q0
25 %1:_(<2 x s32>) = G_TRUNC %0(<2 x s64>)
[all …]
Dlegalize-extract-vector-elt.mir10 ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0
12 ; CHECK: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[C]](s32)
13 ; CHECK: [[EVEC:%[0-9]+]]:_(s64) = G_EXTRACT_VECTOR_ELT [[COPY]](<2 x s64>), [[SEXT]](s64)
14 ; CHECK: $x0 = COPY [[EVEC]](s64)
16 %0:_(<2 x s64>) = COPY $q0
18 %2:_(s64) = G_EXTRACT_VECTOR_ELT %0(<2 x s64>), %1(s32)
19 $x0 = COPY %2(s64)
28 ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0
29 ; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $q1
30 ; CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY $x0
[all …]
Dselect-logical-shifted-reg.mir21 %0:gpr(s64) = COPY $x0
22 %1:gpr(s64) = G_CONSTANT i64 8
23 %2:gpr(s64) = G_CONSTANT i64 -1
24 %3:gpr(s64) = G_SHL %0, %1:gpr(s64)
25 %4:gpr(s64) = G_XOR %3, %2:gpr(s64)
26 %5:gpr(s64) = G_AND %0, %4:gpr(s64)
27 $x0 = COPY %5:gpr(s64)
44 %0:gpr(s64) = COPY $x0
45 %1:gpr(s64) = G_CONSTANT i64 8
46 %2:gpr(s64) = G_CONSTANT i64 -1
[all …]
Dlegalize-rem.mir8 ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
9 ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
10 ; CHECK: [[UDIV:%[0-9]+]]:_(s64) = G_UDIV [[COPY]], [[COPY1]]
11 ; CHECK: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[UDIV]], [[COPY1]]
12 ; CHECK: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[COPY]], [[MUL]]
13 ; CHECK: $x0 = COPY [[SUB]](s64)
14 %0:_(s64) = COPY $x0
15 %1:_(s64) = COPY $x1
16 %2:_(s64) = G_UREM %0, %1
17 $x0 = COPY %2(s64)
[all …]
Dprelegalizercombiner-binop-same-val.mir13 ; CHECK: %copy:_(s64) = COPY $x0
14 ; CHECK: $x0 = COPY %copy(s64)
16 %copy:_(s64) = COPY $x0
17 %or:_(s64) = G_OR %copy, %copy
18 $x0 = COPY %or(s64)
33 ; CHECK: %copy:_(s64) = COPY $x0
34 ; CHECK: $x0 = COPY %copy(s64)
36 %copy:_(s64) = COPY $x0
37 %and:_(s64) = G_AND %copy, %copy
38 $x0 = COPY %and(s64)
[all …]
/external/llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/
Dlegalize-fmad.s64.mir18 ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
19 ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3
20 ; CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY $vgpr4_vgpr5
21 ; CHECK: [[FMUL:%[0-9]+]]:_(s64) = G_FMUL [[COPY]], [[COPY1]]
22 ; CHECK: [[FADD:%[0-9]+]]:_(s64) = G_FADD [[FMUL]], [[COPY2]]
23 ; CHECK: $vgpr0_vgpr1 = COPY [[FADD]](s64)
24 %0:_(s64) = COPY $vgpr0_vgpr1
25 %1:_(s64) = COPY $vgpr2_vgpr3
26 %2:_(s64) = COPY $vgpr4_vgpr5
27 %3:_(s64) = G_FMAD %0, %1, %2
[all …]
Dlegalize-anyext.mir12 ; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[COPY]](s32)
13 ; CHECK: $vgpr0_vgpr1 = COPY [[ANYEXT]](s64)
15 %1:_(s64) = G_ANYEXT %0
27 ; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[COPY]](s32)
28 ; CHECK: $vgpr0_vgpr1 = COPY [[ANYEXT]](s64)
31 %2:_(s64) = G_ANYEXT %1
86 ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
87 ; CHECK: $vgpr0_vgpr1 = COPY [[C]](s64)
89 %1:_(s64) = G_ANYEXT %0
164 ; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[UV]](s32)
[all …]
Dregbankselect-icmp.mir101 ; GFX7: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1
102 ; GFX7: [[COPY1:%[0-9]+]]:sgpr(s64) = COPY $sgpr2_sgpr3
103 ; GFX7: [[COPY2:%[0-9]+]]:vgpr(s64) = COPY [[COPY]](s64)
104 ; GFX7: [[COPY3:%[0-9]+]]:vgpr(s64) = COPY [[COPY1]](s64)
105 ; GFX7: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY2]](s64), [[COPY3]]
107 ; GFX8: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1
108 ; GFX8: [[COPY1:%[0-9]+]]:sgpr(s64) = COPY $sgpr2_sgpr3
109 ; GFX8: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY]](s64), [[COPY1]]
111 %0:_(s64) = COPY $sgpr0_sgpr1
112 %1:_(s64) = COPY $sgpr2_sgpr3
[all …]
Dlegalize-fptosi.mir31 ; SI: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
32 ; SI: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s64)
35 ; VI: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
36 ; VI: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s64)
38 %0:_(s64) = COPY $vgpr0_vgpr1
75 ; SI: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
76 ; SI: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](<2 x s64>)
77 ; SI: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[UV]](s64)
78 ; SI: [[FPTOSI1:%[0-9]+]]:_(s32) = G_FPTOSI [[UV1]](s64)
82 ; VI: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
[all …]
Dlegalize-zext.mir12 ; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[COPY]](s32)
13 ; CHECK: $vgpr0_vgpr1 = COPY [[ZEXT]](s64)
15 %1:_(s64) = G_ZEXT %0
27 ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 65535
28 ; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[COPY]](s32)
29 ; CHECK: [[AND:%[0-9]+]]:_(s64) = G_AND [[ANYEXT]], [[C]]
30 ; CHECK: $vgpr0_vgpr1 = COPY [[AND]](s64)
33 %2:_(s64) = G_ZEXT %1
82 ; CHECK: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[C]](s32)
83 ; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
[all …]
Dinst-select-fract.f64.mir32 %7:sgpr(s64) = G_CONSTANT i64 36
33 %8:sgpr(p4) = G_PTR_ADD %2, %7(s64)
34 %9:sgpr(<2 x s64>) = G_LOAD %8(p4) :: (dereferenceable invariant load 16, align 4, addrspace 4)
35 %10:sgpr(s64) = G_EXTRACT %9(<2 x s64>), 0
36 %13:sgpr(s64) = G_EXTRACT %9(<2 x s64>), 64
37 %15:sgpr(p1) = G_INTTOPTR %13(s64)
38 %18:sgpr(s64) = G_LOAD %15(p1) :: (load 8, addrspace 1)
39 %19:sgpr(s64) = G_FCONSTANT double -0.000000e+00
40 %24:sgpr(s64) = G_FNEG %18
41 %25:vgpr(s64) = COPY %19(s64)
[all …]
Dlegalize-fptoui.mir31 ; SI: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
32 ; SI: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[COPY]](s64)
35 ; VI: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
36 ; VI: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[COPY]](s64)
38 %0:_(s64) = COPY $vgpr0_vgpr1
75 ; SI: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
76 ; SI: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](<2 x s64>)
77 ; SI: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[UV]](s64)
78 ; SI: [[FPTOUI1:%[0-9]+]]:_(s32) = G_FPTOUI [[UV1]](s64)
82 ; VI: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
[all …]
Dregbankselect-sext-inreg.mir32 ; CHECK: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1
33 ; CHECK: [[SEXT_INREG:%[0-9]+]]:sgpr(s64) = G_SEXT_INREG [[COPY]], 1
34 ; CHECK: S_ENDPGM 0, implicit [[SEXT_INREG]](s64)
35 %0:_(s64) = COPY $sgpr0_sgpr1
36 %1:_(s64) = G_SEXT_INREG %0, 1
50 ; CHECK: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1
51 ; CHECK: [[SEXT_INREG:%[0-9]+]]:sgpr(s64) = G_SEXT_INREG [[COPY]], 31
52 ; CHECK: S_ENDPGM 0, implicit [[SEXT_INREG]](s64)
53 %0:_(s64) = COPY $sgpr0_sgpr1
54 %1:_(s64) = G_SEXT_INREG %0, 31
[all …]
Dinst-select-fadd.s64.mir18 %0:vgpr(s64) = COPY $vgpr0_vgpr1
19 %1:vgpr(s64) = COPY $vgpr2_vgpr3
20 %2:vgpr(s64) = G_FADD %0, %1
39 %0:sgpr(s64) = COPY $sgpr0_sgpr1
40 %1:vgpr(s64) = COPY $vgpr0_vgpr1
41 %2:vgpr(s64) = G_FADD %0, %1
60 %0:vgpr(s64) = COPY $vgpr0_vgpr1
61 %1:sgpr(s64) = COPY $sgpr0_sgpr1
62 %2:vgpr(s64) = G_FADD %0, %1
81 %0:vgpr(s64) = COPY $vgpr0_vgpr1
[all …]
Dartifact-combiner-extract.mir16 %2:_(s64) = G_MERGE_VALUES %0, %1
33 %2:_(s64) = G_MERGE_VALUES %0, %1
44 ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
45 ; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
46 ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY [[C]](s64)
47 ; CHECK: $vgpr0_vgpr1 = COPY [[COPY]](s64)
48 %0:_(s64) = G_CONSTANT i64 0
49 %1:_(s64) = G_CONSTANT i64 1
51 %3:_(s64) = G_EXTRACT %2, 0
61 ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
[all …]
Dlegalize-sitofp.mir32 ; GFX6: [[SITOFP:%[0-9]+]]:_(s64) = G_SITOFP [[COPY]](s32)
33 ; GFX6: $vgpr0_vgpr1 = COPY [[SITOFP]](s64)
36 ; GFX8: [[SITOFP:%[0-9]+]]:_(s64) = G_SITOFP [[COPY]](s32)
37 ; GFX8: $vgpr0_vgpr1 = COPY [[SITOFP]](s64)
39 %1:_(s64) = G_SITOFP %0
77 ; GFX6: [[SITOFP:%[0-9]+]]:_(s64) = G_SITOFP [[UV]](s32)
78 ; GFX6: [[SITOFP1:%[0-9]+]]:_(s64) = G_SITOFP [[UV1]](s32)
79 ; GFX6: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[SITOFP]](s64), [[SITOFP1]](s64)
80 ; GFX6: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
84 ; GFX8: [[SITOFP:%[0-9]+]]:_(s64) = G_SITOFP [[UV]](s32)
[all …]

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