1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -run-pass=legalizer -global-isel-abort=0 -o - %s | FileCheck %s 3 4--- 5name: test_zext_s32_to_s64 6body: | 7 bb.0: 8 liveins: $vgpr0 9 10 ; CHECK-LABEL: name: test_zext_s32_to_s64 11 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 12 ; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[COPY]](s32) 13 ; CHECK: $vgpr0_vgpr1 = COPY [[ZEXT]](s64) 14 %0:_(s32) = COPY $vgpr0 15 %1:_(s64) = G_ZEXT %0 16 $vgpr0_vgpr1 = COPY %1 17... 18 19--- 20name: test_zext_s16_to_s64 21body: | 22 bb.0: 23 liveins: $vgpr0 24 25 ; CHECK-LABEL: name: test_zext_s16_to_s64 26 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 27 ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 65535 28 ; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[COPY]](s32) 29 ; CHECK: [[AND:%[0-9]+]]:_(s64) = G_AND [[ANYEXT]], [[C]] 30 ; CHECK: $vgpr0_vgpr1 = COPY [[AND]](s64) 31 %0:_(s32) = COPY $vgpr0 32 %1:_(s16) = G_TRUNC %0 33 %2:_(s64) = G_ZEXT %1 34 $vgpr0_vgpr1 = COPY %2 35... 36 37--- 38name: test_zext_s16_to_s32 39body: | 40 bb.0: 41 liveins: $vgpr0 42 43 ; CHECK-LABEL: name: test_zext_s16_to_s32 44 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 45 ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535 46 ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) 47 ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]] 48 ; CHECK: $vgpr0 = COPY [[AND]](s32) 49 %0:_(s32) = COPY $vgpr0 50 %1:_(s16) = G_TRUNC %0 51 %2:_(s32) = G_ZEXT %1 52 $vgpr0 = COPY %2 53... 54 55--- 56name: test_zext_s24_to_s32 57body: | 58 bb.0: 59 liveins: $vgpr0 60 61 ; CHECK-LABEL: name: test_zext_s24_to_s32 62 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 63 ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16777215 64 ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) 65 ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]] 66 ; CHECK: $vgpr0 = COPY [[AND]](s32) 67 %0:_(s32) = COPY $vgpr0 68 %1:_(s24) = G_TRUNC %0 69 %2:_(s32) = G_ZEXT %1 70 $vgpr0 = COPY %2 71... 72 73--- 74name: test_zext_s32_to_s96 75body: | 76 bb.0: 77 liveins: $vgpr0 78 79 ; CHECK-LABEL: name: test_zext_s32_to_s96 80 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 81 ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 82 ; CHECK: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[C]](s32) 83 ; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 84 ; CHECK: [[MV1:%[0-9]+]]:_(s192) = G_MERGE_VALUES [[MV]](s64), [[C1]](s64), [[C1]](s64) 85 ; CHECK: [[TRUNC:%[0-9]+]]:_(s96) = G_TRUNC [[MV1]](s192) 86 ; CHECK: $vgpr0_vgpr1_vgpr2 = COPY [[TRUNC]](s96) 87 %0:_(s32) = COPY $vgpr0 88 %1:_(s96) = G_ZEXT %0 89 $vgpr0_vgpr1_vgpr2 = COPY %1 90... 91 92--- 93name: test_zext_i1_to_s32 94body: | 95 bb.0: 96 97 ; CHECK-LABEL: name: test_zext_i1_to_s32 98 ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 99 ; CHECK: $vgpr0 = COPY [[C]](s32) 100 %0:_(s1) = G_CONSTANT i1 0 101 %1:_(s32) = G_ZEXT %0 102 $vgpr0 = COPY %1 103... 104 105--- 106name: test_zext_i1_to_i64 107body: | 108 bb.0: 109 110 ; CHECK-LABEL: name: test_zext_i1_to_i64 111 ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 112 ; CHECK: $vgpr0_vgpr1 = COPY [[C]](s64) 113 %0:_(s1) = G_CONSTANT i1 0 114 %1:_(s64) = G_ZEXT %0 115 $vgpr0_vgpr1 = COPY %1 116... 117 118--- 119name: test_zext_v2s16_to_v2s32 120body: | 121 bb.0: 122 liveins: $vgpr0 123 124 ; CHECK-LABEL: name: test_zext_v2s16_to_v2s32 125 ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0 126 ; CHECK: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY]](<2 x s16>) 127 ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 128 ; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32) 129 ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535 130 ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32) 131 ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]] 132 ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32) 133 ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]] 134 ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[AND]](s32), [[AND1]](s32) 135 ; CHECK: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>) 136 %0:_(<2 x s16>) = COPY $vgpr0 137 %1:_(<2 x s32>) = G_ZEXT %0 138 $vgpr0_vgpr1 = COPY %1 139... 140 141--- 142name: test_zext_v3s16_to_v3s32 143body: | 144 bb.0: 145 liveins: $vgpr0_vgpr1 146 147 ; CHECK-LABEL: name: test_zext_v3s16_to_v3s32 148 ; CHECK: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr0_vgpr1 149 ; CHECK: [[EXTRACT:%[0-9]+]]:_(<3 x s16>) = G_EXTRACT [[COPY]](<4 x s16>), 0 150 ; CHECK: [[DEF:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF 151 ; CHECK: [[INSERT:%[0-9]+]]:_(<4 x s16>) = G_INSERT [[DEF]], [[EXTRACT]](<3 x s16>), 0 152 ; CHECK: [[UV:%[0-9]+]]:_(<2 x s16>), [[UV1:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[INSERT]](<4 x s16>) 153 ; CHECK: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[UV]](<2 x s16>) 154 ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 155 ; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32) 156 ; CHECK: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[UV1]](<2 x s16>) 157 ; CHECK: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32) 158 ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535 159 ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32) 160 ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]] 161 ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32) 162 ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]] 163 ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32) 164 ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]] 165 ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[AND]](s32), [[AND1]](s32), [[AND2]](s32) 166 ; CHECK: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x s32>) 167 %0:_(<4 x s16>) = COPY $vgpr0_vgpr1 168 %1:_(<3 x s16>) = G_EXTRACT %0, 0 169 %2:_(<3 x s32>) = G_ZEXT %1 170 $vgpr0_vgpr1_vgpr2 = COPY %2 171... 172 173--- 174name: test_zext_v4s16_to_v4s32 175body: | 176 bb.0: 177 liveins: $vgpr0_vgpr1 178 179 ; CHECK-LABEL: name: test_zext_v4s16_to_v4s32 180 ; CHECK: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr0_vgpr1 181 ; CHECK: [[UV:%[0-9]+]]:_(<2 x s16>), [[UV1:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[COPY]](<4 x s16>) 182 ; CHECK: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[UV]](<2 x s16>) 183 ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 184 ; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32) 185 ; CHECK: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[UV1]](<2 x s16>) 186 ; CHECK: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32) 187 ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535 188 ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32) 189 ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]] 190 ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32) 191 ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]] 192 ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32) 193 ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]] 194 ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32) 195 ; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]] 196 ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[AND]](s32), [[AND1]](s32), [[AND2]](s32), [[AND3]](s32) 197 ; CHECK: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<4 x s32>) 198 %0:_(<4 x s16>) = COPY $vgpr0_vgpr1 199 %1:_(<4 x s32>) = G_ZEXT %0 200 $vgpr0_vgpr1_vgpr2_vgpr3 = COPY %1 201... 202 203--- 204name: test_zext_v2s32_to_v2s64 205body: | 206 bb.0: 207 liveins: $vgpr0_vgpr1 208 209 ; CHECK-LABEL: name: test_zext_v2s32_to_v2s64 210 ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1 211 ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>) 212 ; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[UV]](s32) 213 ; CHECK: [[ZEXT1:%[0-9]+]]:_(s64) = G_ZEXT [[UV1]](s32) 214 ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[ZEXT]](s64), [[ZEXT1]](s64) 215 ; CHECK: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>) 216 %0:_(<2 x s32>) = COPY $vgpr0_vgpr1 217 %1:_(<2 x s64>) = G_ZEXT %0 218 $vgpr0_vgpr1_vgpr2_vgpr3 = COPY %1 219... 220 221--- 222name: test_zext_v3s32_to_v3s64 223body: | 224 bb.0: 225 liveins: $vgpr0_vgpr1_vgpr2 226 227 ; CHECK-LABEL: name: test_zext_v3s32_to_v3s64 228 ; CHECK: [[COPY:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2 229 ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<3 x s32>) 230 ; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[UV]](s32) 231 ; CHECK: [[ZEXT1:%[0-9]+]]:_(s64) = G_ZEXT [[UV1]](s32) 232 ; CHECK: [[ZEXT2:%[0-9]+]]:_(s64) = G_ZEXT [[UV2]](s32) 233 ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s64>) = G_BUILD_VECTOR [[ZEXT]](s64), [[ZEXT1]](s64), [[ZEXT2]](s64) 234 ; CHECK: S_NOP 0, implicit [[BUILD_VECTOR]](<3 x s64>) 235 %0:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2 236 %1:_(<3 x s64>) = G_ZEXT %0 237 S_NOP 0, implicit %1 238 239... 240 241--- 242name: test_zext_v4s32_to_v4s64 243body: | 244 bb.0: 245 liveins: $vgpr0_vgpr1_vgpr2_vgpr3 246 247 ; CHECK-LABEL: name: test_zext_v4s32_to_v4s64 248 ; CHECK: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3 249 ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<4 x s32>) 250 ; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[UV]](s32) 251 ; CHECK: [[ZEXT1:%[0-9]+]]:_(s64) = G_ZEXT [[UV1]](s32) 252 ; CHECK: [[ZEXT2:%[0-9]+]]:_(s64) = G_ZEXT [[UV2]](s32) 253 ; CHECK: [[ZEXT3:%[0-9]+]]:_(s64) = G_ZEXT [[UV3]](s32) 254 ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s64>) = G_BUILD_VECTOR [[ZEXT]](s64), [[ZEXT1]](s64), [[ZEXT2]](s64), [[ZEXT3]](s64) 255 ; CHECK: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[BUILD_VECTOR]](<4 x s64>) 256 %0:_(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3 257 %1:_(<4 x s64>) = G_ZEXT %0 258 $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY %1 259... 260 261--- 262name: test_zext_s8_to_s16 263body: | 264 bb.0: 265 liveins: $vgpr0 266 267 ; CHECK-LABEL: name: test_zext_s8_to_s16 268 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 269 ; CHECK: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 255 270 ; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32) 271 ; CHECK: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C]] 272 ; CHECK: S_ENDPGM 0, implicit [[AND]](s16) 273 %0:_(s32) = COPY $vgpr0 274 %1:_(s8) = G_TRUNC %0 275 %2:_(s16) = G_ZEXT %1 276 S_ENDPGM 0, implicit %2 277... 278 279--- 280name: test_zext_s8_to_s24 281body: | 282 bb.0: 283 liveins: $vgpr0 284 285 ; CHECK-LABEL: name: test_zext_s8_to_s24 286 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 287 ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255 288 ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) 289 ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C]](s32) 290 ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[COPY2]] 291 ; CHECK: [[TRUNC:%[0-9]+]]:_(s24) = G_TRUNC [[AND]](s32) 292 ; CHECK: S_ENDPGM 0, implicit [[TRUNC]](s24) 293 %0:_(s32) = COPY $vgpr0 294 %1:_(s8) = G_TRUNC %0 295 %2:_(s24) = G_ZEXT %1 296 S_ENDPGM 0, implicit %2 297... 298 299 300--- 301name: test_zext_s7_to_s32 302body: | 303 bb.0: 304 liveins: $vgpr0 305 306 ; CHECK-LABEL: name: test_zext_s7_to_s32 307 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 308 ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 127 309 ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) 310 ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]] 311 ; CHECK: S_ENDPGM 0, implicit [[AND]](s32) 312 %0:_(s32) = COPY $vgpr0 313 %1:_(s7) = G_TRUNC %0 314 %2:_(s32) = G_ZEXT %1 315 S_ENDPGM 0, implicit %2 316... 317 318--- 319name: test_zext_s8_to_s32 320body: | 321 bb.0: 322 liveins: $vgpr0 323 324 ; CHECK-LABEL: name: test_zext_s8_to_s32 325 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 326 ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255 327 ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) 328 ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]] 329 ; CHECK: S_ENDPGM 0, implicit [[AND]](s32) 330 %0:_(s32) = COPY $vgpr0 331 %1:_(s8) = G_TRUNC %0 332 %2:_(s32) = G_ZEXT %1 333 S_ENDPGM 0, implicit %2 334... 335 336--- 337name: test_zext_s32_to_s128 338body: | 339 bb.0: 340 liveins: $vgpr0 341 342 ; CHECK-LABEL: name: test_zext_s32_to_s128 343 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 344 ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 345 ; CHECK: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[C]](s32) 346 ; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 347 ; CHECK: [[MV1:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[MV]](s64), [[C1]](s64) 348 ; CHECK: S_ENDPGM 0, implicit [[MV1]](s128) 349 %0:_(s32) = COPY $vgpr0 350 %1:_(s128) = G_ZEXT %0 351 S_ENDPGM 0, implicit %1 352... 353 354--- 355name: test_zext_s32_to_s160 356body: | 357 bb.0: 358 liveins: $vgpr0 359 360 ; CHECK-LABEL: name: test_zext_s32_to_s160 361 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 362 ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 363 ; CHECK: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[C]](s32) 364 ; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 365 ; CHECK: [[MV1:%[0-9]+]]:_(s320) = G_MERGE_VALUES [[MV]](s64), [[C1]](s64), [[C1]](s64), [[C1]](s64), [[C1]](s64) 366 ; CHECK: [[TRUNC:%[0-9]+]]:_(s160) = G_TRUNC [[MV1]](s320) 367 ; CHECK: S_ENDPGM 0, implicit [[TRUNC]](s160) 368 %0:_(s32) = COPY $vgpr0 369 %1:_(s160) = G_ZEXT %0 370 S_ENDPGM 0, implicit %1 371... 372 373 374--- 375name: test_zext_s32_to_s192 376body: | 377 bb.0: 378 liveins: $vgpr0 379 380 ; CHECK-LABEL: name: test_zext_s32_to_s192 381 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 382 ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 383 ; CHECK: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[C]](s32) 384 ; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 385 ; CHECK: [[MV1:%[0-9]+]]:_(s192) = G_MERGE_VALUES [[MV]](s64), [[C1]](s64), [[C1]](s64) 386 ; CHECK: S_ENDPGM 0, implicit [[MV1]](s192) 387 %0:_(s32) = COPY $vgpr0 388 %1:_(s192) = G_ZEXT %0 389 S_ENDPGM 0, implicit %1 390... 391 392--- 393name: test_zext_s32_to_s224 394body: | 395 bb.0: 396 liveins: $vgpr0 397 398 ; CHECK-LABEL: name: test_zext_s32_to_s224 399 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 400 ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 401 ; CHECK: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[C]](s32) 402 ; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 403 ; CHECK: [[MV1:%[0-9]+]]:_(s448) = G_MERGE_VALUES [[MV]](s64), [[C1]](s64), [[C1]](s64), [[C1]](s64), [[C1]](s64), [[C1]](s64), [[C1]](s64) 404 ; CHECK: [[TRUNC:%[0-9]+]]:_(s224) = G_TRUNC [[MV1]](s448) 405 ; CHECK: S_ENDPGM 0, implicit [[TRUNC]](s224) 406 %0:_(s32) = COPY $vgpr0 407 %1:_(s224) = G_ZEXT %0 408 S_ENDPGM 0, implicit %1 409... 410 411--- 412name: test_zext_s32_to_s256 413body: | 414 bb.0: 415 liveins: $vgpr0 416 417 ; CHECK-LABEL: name: test_zext_s32_to_s256 418 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 419 ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 420 ; CHECK: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[C]](s32) 421 ; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 422 ; CHECK: [[MV1:%[0-9]+]]:_(s256) = G_MERGE_VALUES [[MV]](s64), [[C1]](s64), [[C1]](s64), [[C1]](s64) 423 ; CHECK: S_ENDPGM 0, implicit [[MV1]](s256) 424 %0:_(s32) = COPY $vgpr0 425 %1:_(s256) = G_ZEXT %0 426 S_ENDPGM 0, implicit %1 427... 428 429--- 430name: test_zext_s32_to_s512 431body: | 432 bb.0: 433 liveins: $vgpr0 434 435 ; CHECK-LABEL: name: test_zext_s32_to_s512 436 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 437 ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 438 ; CHECK: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[C]](s32) 439 ; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 440 ; CHECK: [[MV1:%[0-9]+]]:_(s512) = G_MERGE_VALUES [[MV]](s64), [[C1]](s64), [[C1]](s64), [[C1]](s64), [[C1]](s64), [[C1]](s64), [[C1]](s64), [[C1]](s64) 441 ; CHECK: S_ENDPGM 0, implicit [[MV1]](s512) 442 %0:_(s32) = COPY $vgpr0 443 %1:_(s512) = G_ZEXT %0 444 S_ENDPGM 0, implicit %1 445... 446 447--- 448name: test_zext_s32_to_s992 449body: | 450 bb.0: 451 liveins: $vgpr0 452 453 ; CHECK-LABEL: name: test_zext_s32_to_s992 454 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 455 ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 456 ; CHECK: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[C]](s32) 457 ; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 458 ; CHECK: [[MV1:%[0-9]+]]:_(s448) = G_MERGE_VALUES [[MV]](s64), [[C1]](s64), [[C1]](s64), [[C1]](s64), [[C1]](s64), [[C1]](s64), [[C1]](s64) 459 ; CHECK: [[TRUNC:%[0-9]+]]:_(s224) = G_TRUNC [[MV1]](s448) 460 ; CHECK: S_ENDPGM 0, implicit [[TRUNC]](s224) 461 %0:_(s32) = COPY $vgpr0 462 %1:_(s224) = G_ZEXT %0 463 S_ENDPGM 0, implicit %1 464... 465 466--- 467name: test_zext_s32_to_s1024 468body: | 469 bb.0: 470 liveins: $vgpr0 471 472 ; CHECK-LABEL: name: test_zext_s32_to_s1024 473 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 474 ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 475 ; CHECK: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[C]](s32) 476 ; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 477 ; CHECK: [[MV1:%[0-9]+]]:_(s1024) = G_MERGE_VALUES [[MV]](s64), [[C1]](s64), [[C1]](s64), [[C1]](s64), [[C1]](s64), [[C1]](s64), [[C1]](s64), [[C1]](s64), [[C1]](s64), [[C1]](s64), [[C1]](s64), [[C1]](s64), [[C1]](s64), [[C1]](s64), [[C1]](s64), [[C1]](s64) 478 ; CHECK: S_ENDPGM 0, implicit [[MV1]](s1024) 479 %0:_(s32) = COPY $vgpr0 480 %1:_(s1024) = G_ZEXT %0 481 S_ENDPGM 0, implicit %1 482... 483 484--- 485name: test_zext_s64_to_s128 486body: | 487 bb.0: 488 liveins: $vgpr0_vgpr1 489 490 ; CHECK-LABEL: name: test_zext_s64_to_s128 491 ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1 492 ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 493 ; CHECK: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[COPY]](s64), [[C]](s64) 494 ; CHECK: S_ENDPGM 0, implicit [[MV]](s128) 495 %0:_(s64) = COPY $vgpr0_vgpr1 496 %1:_(s128) = G_ZEXT %0 497 S_ENDPGM 0, implicit %1 498... 499 500--- 501name: test_zext_s64_to_s192 502body: | 503 bb.0: 504 liveins: $vgpr0_vgpr1 505 506 ; CHECK-LABEL: name: test_zext_s64_to_s192 507 ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1 508 ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 509 ; CHECK: [[MV:%[0-9]+]]:_(s192) = G_MERGE_VALUES [[COPY]](s64), [[C]](s64), [[C]](s64) 510 ; CHECK: S_ENDPGM 0, implicit [[MV]](s192) 511 %0:_(s64) = COPY $vgpr0_vgpr1 512 %1:_(s192) = G_ZEXT %0 513 S_ENDPGM 0, implicit %1 514... 515 516--- 517name: test_zext_s64_to_s256 518body: | 519 bb.0: 520 liveins: $vgpr0_vgpr1 521 522 ; CHECK-LABEL: name: test_zext_s64_to_s256 523 ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1 524 ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 525 ; CHECK: [[MV:%[0-9]+]]:_(s256) = G_MERGE_VALUES [[COPY]](s64), [[C]](s64), [[C]](s64), [[C]](s64) 526 ; CHECK: S_ENDPGM 0, implicit [[MV]](s256) 527 %0:_(s64) = COPY $vgpr0_vgpr1 528 %1:_(s256) = G_ZEXT %0 529 S_ENDPGM 0, implicit %1 530... 531 532--- 533name: test_zext_s64_to_s512 534body: | 535 bb.0: 536 liveins: $vgpr0_vgpr1 537 538 ; CHECK-LABEL: name: test_zext_s64_to_s512 539 ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1 540 ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 541 ; CHECK: [[MV:%[0-9]+]]:_(s512) = G_MERGE_VALUES [[COPY]](s64), [[C]](s64), [[C]](s64), [[C]](s64), [[C]](s64), [[C]](s64), [[C]](s64), [[C]](s64) 542 ; CHECK: S_ENDPGM 0, implicit [[MV]](s512) 543 %0:_(s64) = COPY $vgpr0_vgpr1 544 %1:_(s512) = G_ZEXT %0 545 S_ENDPGM 0, implicit %1 546... 547 548--- 549name: test_zext_s64_to_s1024 550body: | 551 bb.0: 552 liveins: $vgpr0_vgpr1 553 554 ; CHECK-LABEL: name: test_zext_s64_to_s1024 555 ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1 556 ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 557 ; CHECK: [[MV:%[0-9]+]]:_(s1024) = G_MERGE_VALUES [[COPY]](s64), [[C]](s64), [[C]](s64), [[C]](s64), [[C]](s64), [[C]](s64), [[C]](s64), [[C]](s64), [[C]](s64), [[C]](s64), [[C]](s64), [[C]](s64), [[C]](s64), [[C]](s64), [[C]](s64), [[C]](s64) 558 ; CHECK: S_ENDPGM 0, implicit [[MV]](s1024) 559 %0:_(s64) = COPY $vgpr0_vgpr1 560 %1:_(s1024) = G_ZEXT %0 561 S_ENDPGM 0, implicit %1 562... 563 564--- 565name: test_zext_s96_to_s128 566body: | 567 bb.0: 568 liveins: $vgpr0_vgpr1_vgpr2 569 570 ; CHECK-LABEL: name: test_zext_s96_to_s128 571 ; CHECK: [[COPY:%[0-9]+]]:_(s96) = COPY $vgpr0_vgpr1_vgpr2 572 ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s96) 573 ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 574 ; CHECK: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV]](s32), [[UV1]](s32) 575 ; CHECK: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV2]](s32), [[C]](s32) 576 ; CHECK: [[MV2:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[MV]](s64), [[MV1]](s64) 577 ; CHECK: S_ENDPGM 0, implicit [[MV2]](s128) 578 %0:_(s96) = COPY $vgpr0_vgpr1_vgpr2 579 %1:_(s128) = G_ZEXT %0 580 S_ENDPGM 0, implicit %1 581... 582 583--- 584name: test_zext_s128_to_s256 585body: | 586 bb.0: 587 liveins: $vgpr0_vgpr1_vgpr2_vgpr3 588 589 ; CHECK-LABEL: name: test_zext_s128_to_s256 590 ; CHECK: [[COPY:%[0-9]+]]:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3 591 ; CHECK: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](s128) 592 ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 593 ; CHECK: [[MV:%[0-9]+]]:_(s256) = G_MERGE_VALUES [[UV]](s64), [[UV1]](s64), [[C]](s64), [[C]](s64) 594 ; CHECK: S_ENDPGM 0, implicit [[MV]](s256) 595 %0:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3 596 %1:_(s256) = G_ZEXT %0 597 S_ENDPGM 0, implicit %1 598... 599 600--- 601name: test_zext_s32_to_s88 602body: | 603 bb.0: 604 liveins: $vgpr0 605 606 ; CHECK-LABEL: name: test_zext_s32_to_s88 607 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 608 ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 8 609 ; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C]](s32) 610 ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 611 ; CHECK: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C1]](s32) 612 ; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 24 613 ; CHECK: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C2]](s32) 614 ; CHECK: [[C3:%[0-9]+]]:_(s16) = G_CONSTANT i16 255 615 ; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32) 616 ; CHECK: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C3]] 617 ; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32) 618 ; CHECK: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C3]] 619 ; CHECK: [[C4:%[0-9]+]]:_(s16) = G_CONSTANT i16 8 620 ; CHECK: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[AND1]], [[C4]](s16) 621 ; CHECK: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[SHL]] 622 ; CHECK: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR1]](s32) 623 ; CHECK: [[AND2:%[0-9]+]]:_(s16) = G_AND [[TRUNC2]], [[C3]] 624 ; CHECK: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR2]](s32) 625 ; CHECK: [[AND3:%[0-9]+]]:_(s16) = G_AND [[TRUNC3]], [[C3]] 626 ; CHECK: [[SHL1:%[0-9]+]]:_(s16) = G_SHL [[AND3]], [[C4]](s16) 627 ; CHECK: [[OR1:%[0-9]+]]:_(s16) = G_OR [[AND2]], [[SHL1]] 628 ; CHECK: [[C5:%[0-9]+]]:_(s16) = G_CONSTANT i16 0 629 ; CHECK: [[AND4:%[0-9]+]]:_(s16) = G_AND [[C5]], [[C3]] 630 ; CHECK: [[SHL2:%[0-9]+]]:_(s16) = G_SHL [[AND4]], [[C4]](s16) 631 ; CHECK: [[OR2:%[0-9]+]]:_(s16) = G_OR [[AND4]], [[SHL2]] 632 ; CHECK: [[COPY1:%[0-9]+]]:_(s16) = COPY [[OR2]](s16) 633 ; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[OR]](s16) 634 ; CHECK: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[OR1]](s16) 635 ; CHECK: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C1]](s32) 636 ; CHECK: [[OR3:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL3]] 637 ; CHECK: [[ZEXT2:%[0-9]+]]:_(s32) = G_ZEXT [[OR2]](s16) 638 ; CHECK: [[ZEXT3:%[0-9]+]]:_(s32) = G_ZEXT [[COPY1]](s16) 639 ; CHECK: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[ZEXT3]], [[C1]](s32) 640 ; CHECK: [[OR4:%[0-9]+]]:_(s32) = G_OR [[ZEXT2]], [[SHL4]] 641 ; CHECK: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[OR3]](s32), [[OR4]](s32) 642 ; CHECK: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 643 ; CHECK: [[MV1:%[0-9]+]]:_(s704) = G_MERGE_VALUES [[MV]](s64), [[C6]](s64), [[C6]](s64), [[C6]](s64), [[C6]](s64), [[C6]](s64), [[C6]](s64), [[C6]](s64), [[C6]](s64), [[C6]](s64), [[C6]](s64) 644 ; CHECK: [[TRUNC4:%[0-9]+]]:_(s88) = G_TRUNC [[MV1]](s704) 645 ; CHECK: S_ENDPGM 0, implicit [[TRUNC4]](s88) 646 %0:_(s32) = COPY $vgpr0 647 %1:_(s88) = G_ZEXT %0 648 S_ENDPGM 0, implicit %1 649... 650 651# The instruction count blows up for this and takes too long to 652# generate checks. This fails on a G_MERGE_VALUES to s4160 653# 654# --- 655# name: test_zext_s32_to_s65 656# body: | 657# bb.0: 658# liveins: $vgpr0 659 660# %0:_(s32) = COPY $vgpr0 661# %1:_(s65) = G_ZEXT %0 662# S_ENDPGM 0, implicit %1 663# ... 664 665--- 666name: test_zext_s2_to_s112 667body: | 668 bb.0: 669 liveins: $vgpr0 670 671 ; CHECK-LABEL: name: test_zext_s2_to_s112 672 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 673 ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 3 674 ; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 675 ; CHECK: [[TRUNC:%[0-9]+]]:_(s48) = G_TRUNC [[C1]](s64) 676 ; CHECK: [[DEF:%[0-9]+]]:_(s128) = G_IMPLICIT_DEF 677 ; CHECK: [[COPY1:%[0-9]+]]:_(s128) = COPY [[DEF]](s128) 678 ; CHECK: [[INSERT:%[0-9]+]]:_(s128) = G_INSERT [[COPY1]], [[C]](s64), 0 679 ; CHECK: [[COPY2:%[0-9]+]]:_(s128) = COPY [[INSERT]](s128) 680 ; CHECK: [[INSERT1:%[0-9]+]]:_(s128) = G_INSERT [[COPY2]], [[TRUNC]](s48), 64 681 ; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 682 ; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C2]](s32) 683 ; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535 684 ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) 685 ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]] 686 ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32) 687 ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]] 688 ; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32) 689 ; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]] 690 ; CHECK: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 691 ; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[C4]], [[C2]](s32) 692 ; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[C4]], [[SHL1]] 693 ; CHECK: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[OR]](s32), [[OR1]](s32) 694 ; CHECK: [[DEF1:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF 695 ; CHECK: [[COPY5:%[0-9]+]]:_(s64) = COPY [[MV]](s64) 696 ; CHECK: [[EXTRACT:%[0-9]+]]:_(s48) = G_EXTRACT [[DEF1]](s64), 0 697 ; CHECK: [[COPY6:%[0-9]+]]:_(s128) = COPY [[INSERT1]](s128) 698 ; CHECK: [[EXTRACT1:%[0-9]+]]:_(s64) = G_EXTRACT [[COPY6]](s128), 0 699 ; CHECK: [[EXTRACT2:%[0-9]+]]:_(s48) = G_EXTRACT [[COPY6]](s128), 64 700 ; CHECK: [[AND2:%[0-9]+]]:_(s64) = G_AND [[COPY5]], [[EXTRACT1]] 701 ; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[EXTRACT]](s48) 702 ; CHECK: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[EXTRACT2]](s48) 703 ; CHECK: [[AND3:%[0-9]+]]:_(s64) = G_AND [[ANYEXT]], [[ANYEXT1]] 704 ; CHECK: [[TRUNC1:%[0-9]+]]:_(s48) = G_TRUNC [[AND3]](s64) 705 ; CHECK: [[DEF2:%[0-9]+]]:_(s128) = G_IMPLICIT_DEF 706 ; CHECK: [[COPY7:%[0-9]+]]:_(s128) = COPY [[DEF2]](s128) 707 ; CHECK: [[INSERT2:%[0-9]+]]:_(s128) = G_INSERT [[COPY7]], [[AND2]](s64), 0 708 ; CHECK: [[COPY8:%[0-9]+]]:_(s128) = COPY [[INSERT2]](s128) 709 ; CHECK: [[INSERT3:%[0-9]+]]:_(s128) = G_INSERT [[COPY8]], [[TRUNC1]](s48), 64 710 ; CHECK: [[TRUNC2:%[0-9]+]]:_(s112) = G_TRUNC [[INSERT3]](s128) 711 ; CHECK: S_ENDPGM 0, implicit [[TRUNC2]](s112) 712 %0:_(s32) = COPY $vgpr0 713 %1:_(s2) = G_TRUNC %0 714 %2:_(s112) = G_ZEXT %1 715 S_ENDPGM 0, implicit %2 716... 717 718--- 719name: test_zext_s112_to_s128 720body: | 721 bb.0: 722 liveins: $vgpr0_vgpr1_vgpr2_vgpr3 723 ; CHECK-LABEL: name: test_zext_s112_to_s128 724 ; CHECK: [[COPY:%[0-9]+]]:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3 725 ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1 726 ; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 281474976710655 727 ; CHECK: [[COPY1:%[0-9]+]]:_(s128) = COPY [[COPY]](s128) 728 ; CHECK: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY1]](s128) 729 ; CHECK: [[AND:%[0-9]+]]:_(s64) = G_AND [[UV]], [[C]] 730 ; CHECK: [[AND1:%[0-9]+]]:_(s64) = G_AND [[UV1]], [[C1]] 731 ; CHECK: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[AND]](s64), [[AND1]](s64) 732 ; CHECK: S_ENDPGM 0, implicit [[MV]](s128) 733 %0:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3 734 %1:_(s112) = G_TRUNC %0 735 %2:_(s128) = G_ZEXT %1 736 S_ENDPGM 0, implicit %2 737... 738