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Searched refs:sbclrw (Results 1 – 4 of 4) sorted by relevance

/external/llvm-project/llvm/test/MC/RISCV/
Drv64zbs-valid.s15 # CHECK-ASM-AND-OBJ: sbclrw t0, t1, t2
17 sbclrw t0, t1, t2 label
Drv64zbs-invalid.s4 sbclrw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction label
/external/llvm-project/llvm/test/CodeGen/RISCV/
Drv64Zbs.ll20 ; RV64IB-NEXT: sbclrw a0, a0, a1
25 ; RV64IBS-NEXT: sbclrw a0, a0, a1
45 ; RV64IB-NEXT: sbclrw a0, a0, a1
50 ; RV64IBS-NEXT: sbclrw a0, a0, a1
72 ; RV64IB-NEXT: sbclrw a0, a0, a1
78 ; RV64IBS-NEXT: sbclrw a0, a0, a1
/external/llvm-project/llvm/lib/Target/RISCV/
DRISCVInstrInfoB.td372 def SBCLRW : ALUW_rr<0b0100100, 0b001, "sbclrw">, Sched<[]>;