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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
3; RUN:   | FileCheck %s -check-prefix=RV64I
4; RUN: llc -mtriple=riscv64 -mattr=+experimental-b -verify-machineinstrs < %s \
5; RUN:   | FileCheck %s -check-prefix=RV64IB
6; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbs -verify-machineinstrs < %s \
7; RUN:   | FileCheck %s -check-prefix=RV64IBS
8
9define signext i32 @sbclr_i32(i32 signext %a, i32 signext %b) nounwind {
10; RV64I-LABEL: sbclr_i32:
11; RV64I:       # %bb.0:
12; RV64I-NEXT:    addi a2, zero, 1
13; RV64I-NEXT:    sllw a1, a2, a1
14; RV64I-NEXT:    not a1, a1
15; RV64I-NEXT:    and a0, a1, a0
16; RV64I-NEXT:    ret
17;
18; RV64IB-LABEL: sbclr_i32:
19; RV64IB:       # %bb.0:
20; RV64IB-NEXT:    sbclrw a0, a0, a1
21; RV64IB-NEXT:    ret
22;
23; RV64IBS-LABEL: sbclr_i32:
24; RV64IBS:       # %bb.0:
25; RV64IBS-NEXT:    sbclrw a0, a0, a1
26; RV64IBS-NEXT:    ret
27  %and = and i32 %b, 31
28  %shl = shl nuw i32 1, %and
29  %neg = xor i32 %shl, -1
30  %and1 = and i32 %neg, %a
31  ret i32 %and1
32}
33
34define signext i32 @sbclr_i32_no_mask(i32 signext %a, i32 signext %b) nounwind {
35; RV64I-LABEL: sbclr_i32_no_mask:
36; RV64I:       # %bb.0:
37; RV64I-NEXT:    addi a2, zero, 1
38; RV64I-NEXT:    sllw a1, a2, a1
39; RV64I-NEXT:    not a1, a1
40; RV64I-NEXT:    and a0, a1, a0
41; RV64I-NEXT:    ret
42;
43; RV64IB-LABEL: sbclr_i32_no_mask:
44; RV64IB:       # %bb.0:
45; RV64IB-NEXT:    sbclrw a0, a0, a1
46; RV64IB-NEXT:    ret
47;
48; RV64IBS-LABEL: sbclr_i32_no_mask:
49; RV64IBS:       # %bb.0:
50; RV64IBS-NEXT:    sbclrw a0, a0, a1
51; RV64IBS-NEXT:    ret
52  %shl = shl i32 1, %b
53  %neg = xor i32 %shl, -1
54  %and1 = and i32 %neg, %a
55  ret i32 %and1
56}
57
58define signext i32 @sbclr_i32_load(i32* %p, i32 signext %b) nounwind {
59; RV64I-LABEL: sbclr_i32_load:
60; RV64I:       # %bb.0:
61; RV64I-NEXT:    lw a0, 0(a0)
62; RV64I-NEXT:    addi a2, zero, 1
63; RV64I-NEXT:    sllw a1, a2, a1
64; RV64I-NEXT:    not a1, a1
65; RV64I-NEXT:    and a0, a1, a0
66; RV64I-NEXT:    sext.w a0, a0
67; RV64I-NEXT:    ret
68;
69; RV64IB-LABEL: sbclr_i32_load:
70; RV64IB:       # %bb.0:
71; RV64IB-NEXT:    lw a0, 0(a0)
72; RV64IB-NEXT:    sbclrw a0, a0, a1
73; RV64IB-NEXT:    ret
74;
75; RV64IBS-LABEL: sbclr_i32_load:
76; RV64IBS:       # %bb.0:
77; RV64IBS-NEXT:    lw a0, 0(a0)
78; RV64IBS-NEXT:    sbclrw a0, a0, a1
79; RV64IBS-NEXT:    ret
80  %a = load i32, i32* %p
81  %shl = shl i32 1, %b
82  %neg = xor i32 %shl, -1
83  %and1 = and i32 %neg, %a
84  ret i32 %and1
85}
86
87define i64 @sbclr_i64(i64 %a, i64 %b) nounwind {
88; RV64I-LABEL: sbclr_i64:
89; RV64I:       # %bb.0:
90; RV64I-NEXT:    addi a2, zero, 1
91; RV64I-NEXT:    sll a1, a2, a1
92; RV64I-NEXT:    not a1, a1
93; RV64I-NEXT:    and a0, a1, a0
94; RV64I-NEXT:    ret
95;
96; RV64IB-LABEL: sbclr_i64:
97; RV64IB:       # %bb.0:
98; RV64IB-NEXT:    sbclr a0, a0, a1
99; RV64IB-NEXT:    ret
100;
101; RV64IBS-LABEL: sbclr_i64:
102; RV64IBS:       # %bb.0:
103; RV64IBS-NEXT:    sbclr a0, a0, a1
104; RV64IBS-NEXT:    ret
105  %and = and i64 %b, 63
106  %shl = shl nuw i64 1, %and
107  %neg = xor i64 %shl, -1
108  %and1 = and i64 %neg, %a
109  ret i64 %and1
110}
111
112define i64 @sbclr_i64_no_mask(i64 %a, i64 %b) nounwind {
113; RV64I-LABEL: sbclr_i64_no_mask:
114; RV64I:       # %bb.0:
115; RV64I-NEXT:    addi a2, zero, 1
116; RV64I-NEXT:    sll a1, a2, a1
117; RV64I-NEXT:    not a1, a1
118; RV64I-NEXT:    and a0, a1, a0
119; RV64I-NEXT:    ret
120;
121; RV64IB-LABEL: sbclr_i64_no_mask:
122; RV64IB:       # %bb.0:
123; RV64IB-NEXT:    sbclr a0, a0, a1
124; RV64IB-NEXT:    ret
125;
126; RV64IBS-LABEL: sbclr_i64_no_mask:
127; RV64IBS:       # %bb.0:
128; RV64IBS-NEXT:    sbclr a0, a0, a1
129; RV64IBS-NEXT:    ret
130  %shl = shl i64 1, %b
131  %neg = xor i64 %shl, -1
132  %and1 = and i64 %neg, %a
133  ret i64 %and1
134}
135
136define signext i32 @sbset_i32(i32 signext %a, i32 signext %b) nounwind {
137; RV64I-LABEL: sbset_i32:
138; RV64I:       # %bb.0:
139; RV64I-NEXT:    addi a2, zero, 1
140; RV64I-NEXT:    sllw a1, a2, a1
141; RV64I-NEXT:    or a0, a1, a0
142; RV64I-NEXT:    ret
143;
144; RV64IB-LABEL: sbset_i32:
145; RV64IB:       # %bb.0:
146; RV64IB-NEXT:    sbsetw a0, a0, a1
147; RV64IB-NEXT:    ret
148;
149; RV64IBS-LABEL: sbset_i32:
150; RV64IBS:       # %bb.0:
151; RV64IBS-NEXT:    sbsetw a0, a0, a1
152; RV64IBS-NEXT:    ret
153  %and = and i32 %b, 31
154  %shl = shl nuw i32 1, %and
155  %or = or i32 %shl, %a
156  ret i32 %or
157}
158
159define signext i32 @sbset_i32_no_mask(i32 signext %a, i32 signext %b) nounwind {
160; RV64I-LABEL: sbset_i32_no_mask:
161; RV64I:       # %bb.0:
162; RV64I-NEXT:    addi a2, zero, 1
163; RV64I-NEXT:    sllw a1, a2, a1
164; RV64I-NEXT:    or a0, a1, a0
165; RV64I-NEXT:    ret
166;
167; RV64IB-LABEL: sbset_i32_no_mask:
168; RV64IB:       # %bb.0:
169; RV64IB-NEXT:    sbsetw a0, a0, a1
170; RV64IB-NEXT:    ret
171;
172; RV64IBS-LABEL: sbset_i32_no_mask:
173; RV64IBS:       # %bb.0:
174; RV64IBS-NEXT:    sbsetw a0, a0, a1
175; RV64IBS-NEXT:    ret
176  %shl = shl i32 1, %b
177  %or = or i32 %shl, %a
178  ret i32 %or
179}
180
181define signext i32 @sbset_i32_load(i32* %p, i32 signext %b) nounwind {
182; RV64I-LABEL: sbset_i32_load:
183; RV64I:       # %bb.0:
184; RV64I-NEXT:    lw a0, 0(a0)
185; RV64I-NEXT:    addi a2, zero, 1
186; RV64I-NEXT:    sllw a1, a2, a1
187; RV64I-NEXT:    or a0, a1, a0
188; RV64I-NEXT:    sext.w a0, a0
189; RV64I-NEXT:    ret
190;
191; RV64IB-LABEL: sbset_i32_load:
192; RV64IB:       # %bb.0:
193; RV64IB-NEXT:    lw a0, 0(a0)
194; RV64IB-NEXT:    sbsetw a0, a0, a1
195; RV64IB-NEXT:    ret
196;
197; RV64IBS-LABEL: sbset_i32_load:
198; RV64IBS:       # %bb.0:
199; RV64IBS-NEXT:    lw a0, 0(a0)
200; RV64IBS-NEXT:    sbsetw a0, a0, a1
201; RV64IBS-NEXT:    ret
202  %a = load i32, i32* %p
203  %shl = shl i32 1, %b
204  %or = or i32 %shl, %a
205  ret i32 %or
206}
207
208; We can use sbsetw for 1 << x by setting the first source to zero.
209define signext i32 @sbset_i32_zero(i32 signext %a) nounwind {
210; RV64I-LABEL: sbset_i32_zero:
211; RV64I:       # %bb.0:
212; RV64I-NEXT:    addi a1, zero, 1
213; RV64I-NEXT:    sllw a0, a1, a0
214; RV64I-NEXT:    ret
215;
216; RV64IB-LABEL: sbset_i32_zero:
217; RV64IB:       # %bb.0:
218; RV64IB-NEXT:    sbsetw a0, zero, a0
219; RV64IB-NEXT:    ret
220;
221; RV64IBS-LABEL: sbset_i32_zero:
222; RV64IBS:       # %bb.0:
223; RV64IBS-NEXT:    sbsetw a0, zero, a0
224; RV64IBS-NEXT:    ret
225  %shl = shl i32 1, %a
226  ret i32 %shl
227}
228
229define i64 @sbset_i64(i64 %a, i64 %b) nounwind {
230; RV64I-LABEL: sbset_i64:
231; RV64I:       # %bb.0:
232; RV64I-NEXT:    addi a2, zero, 1
233; RV64I-NEXT:    sll a1, a2, a1
234; RV64I-NEXT:    or a0, a1, a0
235; RV64I-NEXT:    ret
236;
237; RV64IB-LABEL: sbset_i64:
238; RV64IB:       # %bb.0:
239; RV64IB-NEXT:    sbset a0, a0, a1
240; RV64IB-NEXT:    ret
241;
242; RV64IBS-LABEL: sbset_i64:
243; RV64IBS:       # %bb.0:
244; RV64IBS-NEXT:    sbset a0, a0, a1
245; RV64IBS-NEXT:    ret
246  %conv = and i64 %b, 63
247  %shl = shl nuw i64 1, %conv
248  %or = or i64 %shl, %a
249  ret i64 %or
250}
251
252define i64 @sbset_i64_no_mask(i64 %a, i64 %b) nounwind {
253; RV64I-LABEL: sbset_i64_no_mask:
254; RV64I:       # %bb.0:
255; RV64I-NEXT:    addi a2, zero, 1
256; RV64I-NEXT:    sll a1, a2, a1
257; RV64I-NEXT:    or a0, a1, a0
258; RV64I-NEXT:    ret
259;
260; RV64IB-LABEL: sbset_i64_no_mask:
261; RV64IB:       # %bb.0:
262; RV64IB-NEXT:    sbset a0, a0, a1
263; RV64IB-NEXT:    ret
264;
265; RV64IBS-LABEL: sbset_i64_no_mask:
266; RV64IBS:       # %bb.0:
267; RV64IBS-NEXT:    sbset a0, a0, a1
268; RV64IBS-NEXT:    ret
269  %shl = shl i64 1, %b
270  %or = or i64 %shl, %a
271  ret i64 %or
272}
273
274; We can use sbsetw for 1 << x by setting the first source to zero.
275define signext i64 @sbset_i64_zero(i64 signext %a) nounwind {
276; RV64I-LABEL: sbset_i64_zero:
277; RV64I:       # %bb.0:
278; RV64I-NEXT:    addi a1, zero, 1
279; RV64I-NEXT:    sll a0, a1, a0
280; RV64I-NEXT:    ret
281;
282; RV64IB-LABEL: sbset_i64_zero:
283; RV64IB:       # %bb.0:
284; RV64IB-NEXT:    sbset a0, zero, a0
285; RV64IB-NEXT:    ret
286;
287; RV64IBS-LABEL: sbset_i64_zero:
288; RV64IBS:       # %bb.0:
289; RV64IBS-NEXT:    sbset a0, zero, a0
290; RV64IBS-NEXT:    ret
291  %shl = shl i64 1, %a
292  ret i64 %shl
293}
294
295define signext i32 @sbinv_i32(i32 signext %a, i32 signext %b) nounwind {
296; RV64I-LABEL: sbinv_i32:
297; RV64I:       # %bb.0:
298; RV64I-NEXT:    addi a2, zero, 1
299; RV64I-NEXT:    sllw a1, a2, a1
300; RV64I-NEXT:    xor a0, a1, a0
301; RV64I-NEXT:    ret
302;
303; RV64IB-LABEL: sbinv_i32:
304; RV64IB:       # %bb.0:
305; RV64IB-NEXT:    sbinvw a0, a0, a1
306; RV64IB-NEXT:    ret
307;
308; RV64IBS-LABEL: sbinv_i32:
309; RV64IBS:       # %bb.0:
310; RV64IBS-NEXT:    sbinvw a0, a0, a1
311; RV64IBS-NEXT:    ret
312  %and = and i32 %b, 31
313  %shl = shl nuw i32 1, %and
314  %xor = xor i32 %shl, %a
315  ret i32 %xor
316}
317
318define signext i32 @sbinv_i32_no_mask(i32 signext %a, i32 signext %b) nounwind {
319; RV64I-LABEL: sbinv_i32_no_mask:
320; RV64I:       # %bb.0:
321; RV64I-NEXT:    addi a2, zero, 1
322; RV64I-NEXT:    sllw a1, a2, a1
323; RV64I-NEXT:    xor a0, a1, a0
324; RV64I-NEXT:    ret
325;
326; RV64IB-LABEL: sbinv_i32_no_mask:
327; RV64IB:       # %bb.0:
328; RV64IB-NEXT:    sbinvw a0, a0, a1
329; RV64IB-NEXT:    ret
330;
331; RV64IBS-LABEL: sbinv_i32_no_mask:
332; RV64IBS:       # %bb.0:
333; RV64IBS-NEXT:    sbinvw a0, a0, a1
334; RV64IBS-NEXT:    ret
335  %shl = shl i32 1, %b
336  %xor = xor i32 %shl, %a
337  ret i32 %xor
338}
339
340define signext i32 @sbinv_i32_load(i32* %p, i32 signext %b) nounwind {
341; RV64I-LABEL: sbinv_i32_load:
342; RV64I:       # %bb.0:
343; RV64I-NEXT:    lw a0, 0(a0)
344; RV64I-NEXT:    addi a2, zero, 1
345; RV64I-NEXT:    sllw a1, a2, a1
346; RV64I-NEXT:    xor a0, a1, a0
347; RV64I-NEXT:    sext.w a0, a0
348; RV64I-NEXT:    ret
349;
350; RV64IB-LABEL: sbinv_i32_load:
351; RV64IB:       # %bb.0:
352; RV64IB-NEXT:    lw a0, 0(a0)
353; RV64IB-NEXT:    sbinvw a0, a0, a1
354; RV64IB-NEXT:    ret
355;
356; RV64IBS-LABEL: sbinv_i32_load:
357; RV64IBS:       # %bb.0:
358; RV64IBS-NEXT:    lw a0, 0(a0)
359; RV64IBS-NEXT:    sbinvw a0, a0, a1
360; RV64IBS-NEXT:    ret
361  %a = load i32, i32* %p
362  %shl = shl i32 1, %b
363  %xor = xor i32 %shl, %a
364  ret i32 %xor
365}
366
367define i64 @sbinv_i64(i64 %a, i64 %b) nounwind {
368; RV64I-LABEL: sbinv_i64:
369; RV64I:       # %bb.0:
370; RV64I-NEXT:    addi a2, zero, 1
371; RV64I-NEXT:    sll a1, a2, a1
372; RV64I-NEXT:    xor a0, a1, a0
373; RV64I-NEXT:    ret
374;
375; RV64IB-LABEL: sbinv_i64:
376; RV64IB:       # %bb.0:
377; RV64IB-NEXT:    sbinv a0, a0, a1
378; RV64IB-NEXT:    ret
379;
380; RV64IBS-LABEL: sbinv_i64:
381; RV64IBS:       # %bb.0:
382; RV64IBS-NEXT:    sbinv a0, a0, a1
383; RV64IBS-NEXT:    ret
384  %conv = and i64 %b, 63
385  %shl = shl nuw i64 1, %conv
386  %xor = xor i64 %shl, %a
387  ret i64 %xor
388}
389
390define i64 @sbinv_i64_no_mask(i64 %a, i64 %b) nounwind {
391; RV64I-LABEL: sbinv_i64_no_mask:
392; RV64I:       # %bb.0:
393; RV64I-NEXT:    addi a2, zero, 1
394; RV64I-NEXT:    sll a1, a2, a1
395; RV64I-NEXT:    xor a0, a1, a0
396; RV64I-NEXT:    ret
397;
398; RV64IB-LABEL: sbinv_i64_no_mask:
399; RV64IB:       # %bb.0:
400; RV64IB-NEXT:    sbinv a0, a0, a1
401; RV64IB-NEXT:    ret
402;
403; RV64IBS-LABEL: sbinv_i64_no_mask:
404; RV64IBS:       # %bb.0:
405; RV64IBS-NEXT:    sbinv a0, a0, a1
406; RV64IBS-NEXT:    ret
407  %shl = shl nuw i64 1, %b
408  %xor = xor i64 %shl, %a
409  ret i64 %xor
410}
411
412define signext i32 @sbext_i32(i32 signext %a, i32 signext %b) nounwind {
413; RV64I-LABEL: sbext_i32:
414; RV64I:       # %bb.0:
415; RV64I-NEXT:    srlw a0, a0, a1
416; RV64I-NEXT:    andi a0, a0, 1
417; RV64I-NEXT:    ret
418;
419; RV64IB-LABEL: sbext_i32:
420; RV64IB:       # %bb.0:
421; RV64IB-NEXT:    sbextw a0, a0, a1
422; RV64IB-NEXT:    ret
423;
424; RV64IBS-LABEL: sbext_i32:
425; RV64IBS:       # %bb.0:
426; RV64IBS-NEXT:    sbextw a0, a0, a1
427; RV64IBS-NEXT:    ret
428  %and = and i32 %b, 31
429  %shr = lshr i32 %a, %and
430  %and1 = and i32 %shr, 1
431  ret i32 %and1
432}
433
434define signext i32 @sbext_i32_no_mask(i32 signext %a, i32 signext %b) nounwind {
435; RV64I-LABEL: sbext_i32_no_mask:
436; RV64I:       # %bb.0:
437; RV64I-NEXT:    srlw a0, a0, a1
438; RV64I-NEXT:    andi a0, a0, 1
439; RV64I-NEXT:    ret
440;
441; RV64IB-LABEL: sbext_i32_no_mask:
442; RV64IB:       # %bb.0:
443; RV64IB-NEXT:    sbextw a0, a0, a1
444; RV64IB-NEXT:    ret
445;
446; RV64IBS-LABEL: sbext_i32_no_mask:
447; RV64IBS:       # %bb.0:
448; RV64IBS-NEXT:    sbextw a0, a0, a1
449; RV64IBS-NEXT:    ret
450  %shr = lshr i32 %a, %b
451  %and1 = and i32 %shr, 1
452  ret i32 %and1
453}
454
455define i64 @sbext_i64(i64 %a, i64 %b) nounwind {
456; RV64I-LABEL: sbext_i64:
457; RV64I:       # %bb.0:
458; RV64I-NEXT:    srl a0, a0, a1
459; RV64I-NEXT:    andi a0, a0, 1
460; RV64I-NEXT:    ret
461;
462; RV64IB-LABEL: sbext_i64:
463; RV64IB:       # %bb.0:
464; RV64IB-NEXT:    sbext a0, a0, a1
465; RV64IB-NEXT:    ret
466;
467; RV64IBS-LABEL: sbext_i64:
468; RV64IBS:       # %bb.0:
469; RV64IBS-NEXT:    sbext a0, a0, a1
470; RV64IBS-NEXT:    ret
471  %conv = and i64 %b, 63
472  %shr = lshr i64 %a, %conv
473  %and1 = and i64 %shr, 1
474  ret i64 %and1
475}
476
477define i64 @sbext_i64_no_mask(i64 %a, i64 %b) nounwind {
478; RV64I-LABEL: sbext_i64_no_mask:
479; RV64I:       # %bb.0:
480; RV64I-NEXT:    srl a0, a0, a1
481; RV64I-NEXT:    andi a0, a0, 1
482; RV64I-NEXT:    ret
483;
484; RV64IB-LABEL: sbext_i64_no_mask:
485; RV64IB:       # %bb.0:
486; RV64IB-NEXT:    sbext a0, a0, a1
487; RV64IB-NEXT:    ret
488;
489; RV64IBS-LABEL: sbext_i64_no_mask:
490; RV64IBS:       # %bb.0:
491; RV64IBS-NEXT:    sbext a0, a0, a1
492; RV64IBS-NEXT:    ret
493  %shr = lshr i64 %a, %b
494  %and1 = and i64 %shr, 1
495  ret i64 %and1
496}
497
498define signext i32 @sbexti_i32(i32 signext %a) nounwind {
499; RV64I-LABEL: sbexti_i32:
500; RV64I:       # %bb.0:
501; RV64I-NEXT:    srli a0, a0, 5
502; RV64I-NEXT:    andi a0, a0, 1
503; RV64I-NEXT:    ret
504;
505; RV64IB-LABEL: sbexti_i32:
506; RV64IB:       # %bb.0:
507; RV64IB-NEXT:    sbexti a0, a0, 5
508; RV64IB-NEXT:    ret
509;
510; RV64IBS-LABEL: sbexti_i32:
511; RV64IBS:       # %bb.0:
512; RV64IBS-NEXT:    sbexti a0, a0, 5
513; RV64IBS-NEXT:    ret
514  %shr = lshr i32 %a, 5
515  %and = and i32 %shr, 1
516  ret i32 %and
517}
518
519define i64 @sbexti_i64(i64 %a) nounwind {
520; RV64I-LABEL: sbexti_i64:
521; RV64I:       # %bb.0:
522; RV64I-NEXT:    srli a0, a0, 5
523; RV64I-NEXT:    andi a0, a0, 1
524; RV64I-NEXT:    ret
525;
526; RV64IB-LABEL: sbexti_i64:
527; RV64IB:       # %bb.0:
528; RV64IB-NEXT:    sbexti a0, a0, 5
529; RV64IB-NEXT:    ret
530;
531; RV64IBS-LABEL: sbexti_i64:
532; RV64IBS:       # %bb.0:
533; RV64IBS-NEXT:    sbexti a0, a0, 5
534; RV64IBS-NEXT:    ret
535  %shr = lshr i64 %a, 5
536  %and = and i64 %shr, 1
537  ret i64 %and
538}
539
540define signext i32 @sbclri_i32_10(i32 signext %a) nounwind {
541; RV64I-LABEL: sbclri_i32_10:
542; RV64I:       # %bb.0:
543; RV64I-NEXT:    andi a0, a0, -1025
544; RV64I-NEXT:    ret
545;
546; RV64IB-LABEL: sbclri_i32_10:
547; RV64IB:       # %bb.0:
548; RV64IB-NEXT:    andi a0, a0, -1025
549; RV64IB-NEXT:    ret
550;
551; RV64IBS-LABEL: sbclri_i32_10:
552; RV64IBS:       # %bb.0:
553; RV64IBS-NEXT:    andi a0, a0, -1025
554; RV64IBS-NEXT:    ret
555  %and = and i32 %a, -1025
556  ret i32 %and
557}
558
559define signext i32 @sbclri_i32_11(i32 signext %a) nounwind {
560; RV64I-LABEL: sbclri_i32_11:
561; RV64I:       # %bb.0:
562; RV64I-NEXT:    lui a1, 1048575
563; RV64I-NEXT:    addiw a1, a1, 2047
564; RV64I-NEXT:    and a0, a0, a1
565; RV64I-NEXT:    ret
566;
567; RV64IB-LABEL: sbclri_i32_11:
568; RV64IB:       # %bb.0:
569; RV64IB-NEXT:    sbclriw a0, a0, 11
570; RV64IB-NEXT:    ret
571;
572; RV64IBS-LABEL: sbclri_i32_11:
573; RV64IBS:       # %bb.0:
574; RV64IBS-NEXT:    sbclriw a0, a0, 11
575; RV64IBS-NEXT:    ret
576  %and = and i32 %a, -2049
577  ret i32 %and
578}
579
580define signext i32 @sbclri_i32_30(i32 signext %a) nounwind {
581; RV64I-LABEL: sbclri_i32_30:
582; RV64I:       # %bb.0:
583; RV64I-NEXT:    lui a1, 786432
584; RV64I-NEXT:    addiw a1, a1, -1
585; RV64I-NEXT:    and a0, a0, a1
586; RV64I-NEXT:    ret
587;
588; RV64IB-LABEL: sbclri_i32_30:
589; RV64IB:       # %bb.0:
590; RV64IB-NEXT:    sbclriw a0, a0, 30
591; RV64IB-NEXT:    ret
592;
593; RV64IBS-LABEL: sbclri_i32_30:
594; RV64IBS:       # %bb.0:
595; RV64IBS-NEXT:    sbclriw a0, a0, 30
596; RV64IBS-NEXT:    ret
597  %and = and i32 %a, -1073741825
598  ret i32 %and
599}
600
601define signext i32 @sbclri_i32_31(i32 signext %a) nounwind {
602; RV64I-LABEL: sbclri_i32_31:
603; RV64I:       # %bb.0:
604; RV64I-NEXT:    lui a1, 524288
605; RV64I-NEXT:    addiw a1, a1, -1
606; RV64I-NEXT:    and a0, a0, a1
607; RV64I-NEXT:    ret
608;
609; RV64IB-LABEL: sbclri_i32_31:
610; RV64IB:       # %bb.0:
611; RV64IB-NEXT:    sbclriw a0, a0, 31
612; RV64IB-NEXT:    ret
613;
614; RV64IBS-LABEL: sbclri_i32_31:
615; RV64IBS:       # %bb.0:
616; RV64IBS-NEXT:    sbclriw a0, a0, 31
617; RV64IBS-NEXT:    ret
618  %and = and i32 %a, -2147483649
619  ret i32 %and
620}
621
622define i64 @sbclri_i64_10(i64 %a) nounwind {
623; RV64I-LABEL: sbclri_i64_10:
624; RV64I:       # %bb.0:
625; RV64I-NEXT:    andi a0, a0, -1025
626; RV64I-NEXT:    ret
627;
628; RV64IB-LABEL: sbclri_i64_10:
629; RV64IB:       # %bb.0:
630; RV64IB-NEXT:    andi a0, a0, -1025
631; RV64IB-NEXT:    ret
632;
633; RV64IBS-LABEL: sbclri_i64_10:
634; RV64IBS:       # %bb.0:
635; RV64IBS-NEXT:    andi a0, a0, -1025
636; RV64IBS-NEXT:    ret
637  %and = and i64 %a, -1025
638  ret i64 %and
639}
640
641define i64 @sbclri_i64_11(i64 %a) nounwind {
642; RV64I-LABEL: sbclri_i64_11:
643; RV64I:       # %bb.0:
644; RV64I-NEXT:    lui a1, 1048575
645; RV64I-NEXT:    addiw a1, a1, 2047
646; RV64I-NEXT:    and a0, a0, a1
647; RV64I-NEXT:    ret
648;
649; RV64IB-LABEL: sbclri_i64_11:
650; RV64IB:       # %bb.0:
651; RV64IB-NEXT:    sbclri a0, a0, 11
652; RV64IB-NEXT:    ret
653;
654; RV64IBS-LABEL: sbclri_i64_11:
655; RV64IBS:       # %bb.0:
656; RV64IBS-NEXT:    sbclri a0, a0, 11
657; RV64IBS-NEXT:    ret
658  %and = and i64 %a, -2049
659  ret i64 %and
660}
661
662define i64 @sbclri_i64_30(i64 %a) nounwind {
663; RV64I-LABEL: sbclri_i64_30:
664; RV64I:       # %bb.0:
665; RV64I-NEXT:    lui a1, 786432
666; RV64I-NEXT:    addiw a1, a1, -1
667; RV64I-NEXT:    and a0, a0, a1
668; RV64I-NEXT:    ret
669;
670; RV64IB-LABEL: sbclri_i64_30:
671; RV64IB:       # %bb.0:
672; RV64IB-NEXT:    sbclri a0, a0, 30
673; RV64IB-NEXT:    ret
674;
675; RV64IBS-LABEL: sbclri_i64_30:
676; RV64IBS:       # %bb.0:
677; RV64IBS-NEXT:    sbclri a0, a0, 30
678; RV64IBS-NEXT:    ret
679  %and = and i64 %a, -1073741825
680  ret i64 %and
681}
682
683define i64 @sbclri_i64_31(i64 %a) nounwind {
684; RV64I-LABEL: sbclri_i64_31:
685; RV64I:       # %bb.0:
686; RV64I-NEXT:    addi a1, zero, -1
687; RV64I-NEXT:    slli a1, a1, 31
688; RV64I-NEXT:    addi a1, a1, -1
689; RV64I-NEXT:    and a0, a0, a1
690; RV64I-NEXT:    ret
691;
692; RV64IB-LABEL: sbclri_i64_31:
693; RV64IB:       # %bb.0:
694; RV64IB-NEXT:    sbclri a0, a0, 31
695; RV64IB-NEXT:    ret
696;
697; RV64IBS-LABEL: sbclri_i64_31:
698; RV64IBS:       # %bb.0:
699; RV64IBS-NEXT:    sbclri a0, a0, 31
700; RV64IBS-NEXT:    ret
701  %and = and i64 %a, -2147483649
702  ret i64 %and
703}
704
705define i64 @sbclri_i64_62(i64 %a) nounwind {
706; RV64I-LABEL: sbclri_i64_62:
707; RV64I:       # %bb.0:
708; RV64I-NEXT:    addi a1, zero, -1
709; RV64I-NEXT:    slli a1, a1, 62
710; RV64I-NEXT:    addi a1, a1, -1
711; RV64I-NEXT:    and a0, a0, a1
712; RV64I-NEXT:    ret
713;
714; RV64IB-LABEL: sbclri_i64_62:
715; RV64IB:       # %bb.0:
716; RV64IB-NEXT:    sbclri a0, a0, 62
717; RV64IB-NEXT:    ret
718;
719; RV64IBS-LABEL: sbclri_i64_62:
720; RV64IBS:       # %bb.0:
721; RV64IBS-NEXT:    sbclri a0, a0, 62
722; RV64IBS-NEXT:    ret
723  %and = and i64 %a, -4611686018427387905
724  ret i64 %and
725}
726
727define i64 @sbclri_i64_63(i64 %a) nounwind {
728; RV64I-LABEL: sbclri_i64_63:
729; RV64I:       # %bb.0:
730; RV64I-NEXT:    addi a1, zero, -1
731; RV64I-NEXT:    slli a1, a1, 63
732; RV64I-NEXT:    addi a1, a1, -1
733; RV64I-NEXT:    and a0, a0, a1
734; RV64I-NEXT:    ret
735;
736; RV64IB-LABEL: sbclri_i64_63:
737; RV64IB:       # %bb.0:
738; RV64IB-NEXT:    sbclri a0, a0, 63
739; RV64IB-NEXT:    ret
740;
741; RV64IBS-LABEL: sbclri_i64_63:
742; RV64IBS:       # %bb.0:
743; RV64IBS-NEXT:    sbclri a0, a0, 63
744; RV64IBS-NEXT:    ret
745  %and = and i64 %a, -9223372036854775809
746  ret i64 %and
747}
748
749define signext i32 @sbseti_i32_10(i32 signext %a) nounwind {
750; RV64I-LABEL: sbseti_i32_10:
751; RV64I:       # %bb.0:
752; RV64I-NEXT:    ori a0, a0, 1024
753; RV64I-NEXT:    ret
754;
755; RV64IB-LABEL: sbseti_i32_10:
756; RV64IB:       # %bb.0:
757; RV64IB-NEXT:    ori a0, a0, 1024
758; RV64IB-NEXT:    ret
759;
760; RV64IBS-LABEL: sbseti_i32_10:
761; RV64IBS:       # %bb.0:
762; RV64IBS-NEXT:    ori a0, a0, 1024
763; RV64IBS-NEXT:    ret
764  %or = or i32 %a, 1024
765  ret i32 %or
766}
767
768define signext i32 @sbseti_i32_11(i32 signext %a) nounwind {
769; RV64I-LABEL: sbseti_i32_11:
770; RV64I:       # %bb.0:
771; RV64I-NEXT:    lui a1, 1
772; RV64I-NEXT:    addiw a1, a1, -2048
773; RV64I-NEXT:    or a0, a0, a1
774; RV64I-NEXT:    ret
775;
776; RV64IB-LABEL: sbseti_i32_11:
777; RV64IB:       # %bb.0:
778; RV64IB-NEXT:    sbsetiw a0, a0, 11
779; RV64IB-NEXT:    ret
780;
781; RV64IBS-LABEL: sbseti_i32_11:
782; RV64IBS:       # %bb.0:
783; RV64IBS-NEXT:    sbsetiw a0, a0, 11
784; RV64IBS-NEXT:    ret
785  %or = or i32 %a, 2048
786  ret i32 %or
787}
788
789define signext i32 @sbseti_i32_30(i32 signext %a) nounwind {
790; RV64I-LABEL: sbseti_i32_30:
791; RV64I:       # %bb.0:
792; RV64I-NEXT:    lui a1, 262144
793; RV64I-NEXT:    or a0, a0, a1
794; RV64I-NEXT:    ret
795;
796; RV64IB-LABEL: sbseti_i32_30:
797; RV64IB:       # %bb.0:
798; RV64IB-NEXT:    sbsetiw a0, a0, 30
799; RV64IB-NEXT:    ret
800;
801; RV64IBS-LABEL: sbseti_i32_30:
802; RV64IBS:       # %bb.0:
803; RV64IBS-NEXT:    sbsetiw a0, a0, 30
804; RV64IBS-NEXT:    ret
805  %or = or i32 %a, 1073741824
806  ret i32 %or
807}
808
809define signext i32 @sbseti_i32_31(i32 signext %a) nounwind {
810; RV64I-LABEL: sbseti_i32_31:
811; RV64I:       # %bb.0:
812; RV64I-NEXT:    lui a1, 524288
813; RV64I-NEXT:    or a0, a0, a1
814; RV64I-NEXT:    ret
815;
816; RV64IB-LABEL: sbseti_i32_31:
817; RV64IB:       # %bb.0:
818; RV64IB-NEXT:    sbsetiw a0, a0, 31
819; RV64IB-NEXT:    ret
820;
821; RV64IBS-LABEL: sbseti_i32_31:
822; RV64IBS:       # %bb.0:
823; RV64IBS-NEXT:    sbsetiw a0, a0, 31
824; RV64IBS-NEXT:    ret
825  %or = or i32 %a, 2147483648
826  ret i32 %or
827}
828
829define i64 @sbseti_i64_10(i64 %a) nounwind {
830; RV64I-LABEL: sbseti_i64_10:
831; RV64I:       # %bb.0:
832; RV64I-NEXT:    ori a0, a0, 1024
833; RV64I-NEXT:    ret
834;
835; RV64IB-LABEL: sbseti_i64_10:
836; RV64IB:       # %bb.0:
837; RV64IB-NEXT:    ori a0, a0, 1024
838; RV64IB-NEXT:    ret
839;
840; RV64IBS-LABEL: sbseti_i64_10:
841; RV64IBS:       # %bb.0:
842; RV64IBS-NEXT:    ori a0, a0, 1024
843; RV64IBS-NEXT:    ret
844  %or = or i64 %a, 1024
845  ret i64 %or
846}
847
848define i64 @sbseti_i64_11(i64 %a) nounwind {
849; RV64I-LABEL: sbseti_i64_11:
850; RV64I:       # %bb.0:
851; RV64I-NEXT:    lui a1, 1
852; RV64I-NEXT:    addiw a1, a1, -2048
853; RV64I-NEXT:    or a0, a0, a1
854; RV64I-NEXT:    ret
855;
856; RV64IB-LABEL: sbseti_i64_11:
857; RV64IB:       # %bb.0:
858; RV64IB-NEXT:    sbseti a0, a0, 11
859; RV64IB-NEXT:    ret
860;
861; RV64IBS-LABEL: sbseti_i64_11:
862; RV64IBS:       # %bb.0:
863; RV64IBS-NEXT:    sbseti a0, a0, 11
864; RV64IBS-NEXT:    ret
865  %or = or i64 %a, 2048
866  ret i64 %or
867}
868
869define i64 @sbseti_i64_30(i64 %a) nounwind {
870; RV64I-LABEL: sbseti_i64_30:
871; RV64I:       # %bb.0:
872; RV64I-NEXT:    lui a1, 262144
873; RV64I-NEXT:    or a0, a0, a1
874; RV64I-NEXT:    ret
875;
876; RV64IB-LABEL: sbseti_i64_30:
877; RV64IB:       # %bb.0:
878; RV64IB-NEXT:    sbseti a0, a0, 30
879; RV64IB-NEXT:    ret
880;
881; RV64IBS-LABEL: sbseti_i64_30:
882; RV64IBS:       # %bb.0:
883; RV64IBS-NEXT:    sbseti a0, a0, 30
884; RV64IBS-NEXT:    ret
885  %or = or i64 %a, 1073741824
886  ret i64 %or
887}
888
889define i64 @sbseti_i64_31(i64 %a) nounwind {
890; RV64I-LABEL: sbseti_i64_31:
891; RV64I:       # %bb.0:
892; RV64I-NEXT:    addi a1, zero, 1
893; RV64I-NEXT:    slli a1, a1, 31
894; RV64I-NEXT:    or a0, a0, a1
895; RV64I-NEXT:    ret
896;
897; RV64IB-LABEL: sbseti_i64_31:
898; RV64IB:       # %bb.0:
899; RV64IB-NEXT:    sbseti a0, a0, 31
900; RV64IB-NEXT:    ret
901;
902; RV64IBS-LABEL: sbseti_i64_31:
903; RV64IBS:       # %bb.0:
904; RV64IBS-NEXT:    sbseti a0, a0, 31
905; RV64IBS-NEXT:    ret
906  %or = or i64 %a, 2147483648
907  ret i64 %or
908}
909
910define i64 @sbseti_i64_62(i64 %a) nounwind {
911; RV64I-LABEL: sbseti_i64_62:
912; RV64I:       # %bb.0:
913; RV64I-NEXT:    addi a1, zero, 1
914; RV64I-NEXT:    slli a1, a1, 62
915; RV64I-NEXT:    or a0, a0, a1
916; RV64I-NEXT:    ret
917;
918; RV64IB-LABEL: sbseti_i64_62:
919; RV64IB:       # %bb.0:
920; RV64IB-NEXT:    sbseti a0, a0, 62
921; RV64IB-NEXT:    ret
922;
923; RV64IBS-LABEL: sbseti_i64_62:
924; RV64IBS:       # %bb.0:
925; RV64IBS-NEXT:    sbseti a0, a0, 62
926; RV64IBS-NEXT:    ret
927  %or = or i64 %a, 4611686018427387904
928  ret i64 %or
929}
930
931define i64 @sbseti_i64_63(i64 %a) nounwind {
932; RV64I-LABEL: sbseti_i64_63:
933; RV64I:       # %bb.0:
934; RV64I-NEXT:    addi a1, zero, -1
935; RV64I-NEXT:    slli a1, a1, 63
936; RV64I-NEXT:    or a0, a0, a1
937; RV64I-NEXT:    ret
938;
939; RV64IB-LABEL: sbseti_i64_63:
940; RV64IB:       # %bb.0:
941; RV64IB-NEXT:    sbseti a0, a0, 63
942; RV64IB-NEXT:    ret
943;
944; RV64IBS-LABEL: sbseti_i64_63:
945; RV64IBS:       # %bb.0:
946; RV64IBS-NEXT:    sbseti a0, a0, 63
947; RV64IBS-NEXT:    ret
948  %or = or i64 %a, 9223372036854775808
949  ret i64 %or
950}
951
952define signext i32 @sbinvi_i32_10(i32 signext %a) nounwind {
953; RV64I-LABEL: sbinvi_i32_10:
954; RV64I:       # %bb.0:
955; RV64I-NEXT:    xori a0, a0, 1024
956; RV64I-NEXT:    ret
957;
958; RV64IB-LABEL: sbinvi_i32_10:
959; RV64IB:       # %bb.0:
960; RV64IB-NEXT:    xori a0, a0, 1024
961; RV64IB-NEXT:    ret
962;
963; RV64IBS-LABEL: sbinvi_i32_10:
964; RV64IBS:       # %bb.0:
965; RV64IBS-NEXT:    xori a0, a0, 1024
966; RV64IBS-NEXT:    ret
967  %xor = xor i32 %a, 1024
968  ret i32 %xor
969}
970
971define signext i32 @sbinvi_i32_11(i32 signext %a) nounwind {
972; RV64I-LABEL: sbinvi_i32_11:
973; RV64I:       # %bb.0:
974; RV64I-NEXT:    lui a1, 1
975; RV64I-NEXT:    addiw a1, a1, -2048
976; RV64I-NEXT:    xor a0, a0, a1
977; RV64I-NEXT:    ret
978;
979; RV64IB-LABEL: sbinvi_i32_11:
980; RV64IB:       # %bb.0:
981; RV64IB-NEXT:    sbinviw a0, a0, 11
982; RV64IB-NEXT:    ret
983;
984; RV64IBS-LABEL: sbinvi_i32_11:
985; RV64IBS:       # %bb.0:
986; RV64IBS-NEXT:    sbinviw a0, a0, 11
987; RV64IBS-NEXT:    ret
988  %xor = xor i32 %a, 2048
989  ret i32 %xor
990}
991
992define signext i32 @sbinvi_i32_30(i32 signext %a) nounwind {
993; RV64I-LABEL: sbinvi_i32_30:
994; RV64I:       # %bb.0:
995; RV64I-NEXT:    lui a1, 262144
996; RV64I-NEXT:    xor a0, a0, a1
997; RV64I-NEXT:    ret
998;
999; RV64IB-LABEL: sbinvi_i32_30:
1000; RV64IB:       # %bb.0:
1001; RV64IB-NEXT:    sbinviw a0, a0, 30
1002; RV64IB-NEXT:    ret
1003;
1004; RV64IBS-LABEL: sbinvi_i32_30:
1005; RV64IBS:       # %bb.0:
1006; RV64IBS-NEXT:    sbinviw a0, a0, 30
1007; RV64IBS-NEXT:    ret
1008  %xor = xor i32 %a, 1073741824
1009  ret i32 %xor
1010}
1011
1012define signext i32 @sbinvi_i32_31(i32 signext %a) nounwind {
1013; RV64I-LABEL: sbinvi_i32_31:
1014; RV64I:       # %bb.0:
1015; RV64I-NEXT:    lui a1, 524288
1016; RV64I-NEXT:    xor a0, a0, a1
1017; RV64I-NEXT:    ret
1018;
1019; RV64IB-LABEL: sbinvi_i32_31:
1020; RV64IB:       # %bb.0:
1021; RV64IB-NEXT:    sbinviw a0, a0, 31
1022; RV64IB-NEXT:    ret
1023;
1024; RV64IBS-LABEL: sbinvi_i32_31:
1025; RV64IBS:       # %bb.0:
1026; RV64IBS-NEXT:    sbinviw a0, a0, 31
1027; RV64IBS-NEXT:    ret
1028  %xor = xor i32 %a, 2147483648
1029  ret i32 %xor
1030}
1031
1032define i64 @sbinvi_i64_10(i64 %a) nounwind {
1033; RV64I-LABEL: sbinvi_i64_10:
1034; RV64I:       # %bb.0:
1035; RV64I-NEXT:    xori a0, a0, 1024
1036; RV64I-NEXT:    ret
1037;
1038; RV64IB-LABEL: sbinvi_i64_10:
1039; RV64IB:       # %bb.0:
1040; RV64IB-NEXT:    xori a0, a0, 1024
1041; RV64IB-NEXT:    ret
1042;
1043; RV64IBS-LABEL: sbinvi_i64_10:
1044; RV64IBS:       # %bb.0:
1045; RV64IBS-NEXT:    xori a0, a0, 1024
1046; RV64IBS-NEXT:    ret
1047  %xor = xor i64 %a, 1024
1048  ret i64 %xor
1049}
1050
1051define i64 @sbinvi_i64_11(i64 %a) nounwind {
1052; RV64I-LABEL: sbinvi_i64_11:
1053; RV64I:       # %bb.0:
1054; RV64I-NEXT:    lui a1, 1
1055; RV64I-NEXT:    addiw a1, a1, -2048
1056; RV64I-NEXT:    xor a0, a0, a1
1057; RV64I-NEXT:    ret
1058;
1059; RV64IB-LABEL: sbinvi_i64_11:
1060; RV64IB:       # %bb.0:
1061; RV64IB-NEXT:    sbinvi a0, a0, 11
1062; RV64IB-NEXT:    ret
1063;
1064; RV64IBS-LABEL: sbinvi_i64_11:
1065; RV64IBS:       # %bb.0:
1066; RV64IBS-NEXT:    sbinvi a0, a0, 11
1067; RV64IBS-NEXT:    ret
1068  %xor = xor i64 %a, 2048
1069  ret i64 %xor
1070}
1071
1072define i64 @sbinvi_i64_30(i64 %a) nounwind {
1073; RV64I-LABEL: sbinvi_i64_30:
1074; RV64I:       # %bb.0:
1075; RV64I-NEXT:    lui a1, 262144
1076; RV64I-NEXT:    xor a0, a0, a1
1077; RV64I-NEXT:    ret
1078;
1079; RV64IB-LABEL: sbinvi_i64_30:
1080; RV64IB:       # %bb.0:
1081; RV64IB-NEXT:    sbinvi a0, a0, 30
1082; RV64IB-NEXT:    ret
1083;
1084; RV64IBS-LABEL: sbinvi_i64_30:
1085; RV64IBS:       # %bb.0:
1086; RV64IBS-NEXT:    sbinvi a0, a0, 30
1087; RV64IBS-NEXT:    ret
1088  %xor = xor i64 %a, 1073741824
1089  ret i64 %xor
1090}
1091
1092define i64 @sbinvi_i64_31(i64 %a) nounwind {
1093; RV64I-LABEL: sbinvi_i64_31:
1094; RV64I:       # %bb.0:
1095; RV64I-NEXT:    addi a1, zero, 1
1096; RV64I-NEXT:    slli a1, a1, 31
1097; RV64I-NEXT:    xor a0, a0, a1
1098; RV64I-NEXT:    ret
1099;
1100; RV64IB-LABEL: sbinvi_i64_31:
1101; RV64IB:       # %bb.0:
1102; RV64IB-NEXT:    sbinvi a0, a0, 31
1103; RV64IB-NEXT:    ret
1104;
1105; RV64IBS-LABEL: sbinvi_i64_31:
1106; RV64IBS:       # %bb.0:
1107; RV64IBS-NEXT:    sbinvi a0, a0, 31
1108; RV64IBS-NEXT:    ret
1109  %xor = xor i64 %a, 2147483648
1110  ret i64 %xor
1111}
1112
1113define i64 @sbinvi_i64_62(i64 %a) nounwind {
1114; RV64I-LABEL: sbinvi_i64_62:
1115; RV64I:       # %bb.0:
1116; RV64I-NEXT:    addi a1, zero, 1
1117; RV64I-NEXT:    slli a1, a1, 62
1118; RV64I-NEXT:    xor a0, a0, a1
1119; RV64I-NEXT:    ret
1120;
1121; RV64IB-LABEL: sbinvi_i64_62:
1122; RV64IB:       # %bb.0:
1123; RV64IB-NEXT:    sbinvi a0, a0, 62
1124; RV64IB-NEXT:    ret
1125;
1126; RV64IBS-LABEL: sbinvi_i64_62:
1127; RV64IBS:       # %bb.0:
1128; RV64IBS-NEXT:    sbinvi a0, a0, 62
1129; RV64IBS-NEXT:    ret
1130  %xor = xor i64 %a, 4611686018427387904
1131  ret i64 %xor
1132}
1133
1134define i64 @sbinvi_i64_63(i64 %a) nounwind {
1135; RV64I-LABEL: sbinvi_i64_63:
1136; RV64I:       # %bb.0:
1137; RV64I-NEXT:    addi a1, zero, -1
1138; RV64I-NEXT:    slli a1, a1, 63
1139; RV64I-NEXT:    xor a0, a0, a1
1140; RV64I-NEXT:    ret
1141;
1142; RV64IB-LABEL: sbinvi_i64_63:
1143; RV64IB:       # %bb.0:
1144; RV64IB-NEXT:    sbinvi a0, a0, 63
1145; RV64IB-NEXT:    ret
1146;
1147; RV64IBS-LABEL: sbinvi_i64_63:
1148; RV64IBS:       # %bb.0:
1149; RV64IBS-NEXT:    sbinvi a0, a0, 63
1150; RV64IBS-NEXT:    ret
1151  %xor = xor i64 %a, 9223372036854775808
1152  ret i64 %xor
1153}
1154