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Searched refs:scavengeRegister (Results 1 – 24 of 24) sorted by relevance

/external/llvm/include/llvm/CodeGen/
DRegisterScavenging.h143 unsigned scavengeRegister(const TargetRegisterClass *RegClass,
145 unsigned scavengeRegister(const TargetRegisterClass *RegClass, int SPAdj) { in scavengeRegister() function
146 return scavengeRegister(RegClass, MBBI, SPAdj); in scavengeRegister()
/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/
DRegisterScavenging.h163 Register scavengeRegister(const TargetRegisterClass *RC,
166 Register scavengeRegister(const TargetRegisterClass *RegClass, int SPAdj,
168 return scavengeRegister(RegClass, MBBI, SPAdj, AllowSpill);
/external/llvm-project/llvm/include/llvm/CodeGen/
DRegisterScavenging.h154 Register scavengeRegister(const TargetRegisterClass *RC,
157 Register scavengeRegister(const TargetRegisterClass *RegClass, int SPAdj,
159 return scavengeRegister(RegClass, MBBI, SPAdj, AllowSpill);
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/XCore/
DXCoreRegisterInfo.cpp100 unsigned ScratchOffset = RS->scavengeRegister(&XCore::GRRegsRegClass, II, 0); in InsertFPConstInst()
172 ScratchBase = RS->scavengeRegister(&XCore::GRRegsRegClass, II, 0); in InsertSPConstInst()
177 unsigned ScratchOffset = RS->scavengeRegister(&XCore::GRRegsRegClass, II, 0); in InsertSPConstInst()
/external/llvm-project/llvm/lib/Target/XCore/
DXCoreRegisterInfo.cpp100 unsigned ScratchOffset = RS->scavengeRegister(&XCore::GRRegsRegClass, II, 0); in InsertFPConstInst()
172 ScratchBase = RS->scavengeRegister(&XCore::GRRegsRegClass, II, 0); in InsertSPConstInst()
177 unsigned ScratchOffset = RS->scavengeRegister(&XCore::GRRegsRegClass, II, 0); in InsertSPConstInst()
/external/llvm/lib/Target/XCore/
DXCoreRegisterInfo.cpp101 unsigned ScratchOffset = RS->scavengeRegister(&XCore::GRRegsRegClass, II, 0); in InsertFPConstInst()
173 ScratchBase = RS->scavengeRegister(&XCore::GRRegsRegClass, II, 0); in InsertSPConstInst()
178 unsigned ScratchOffset = RS->scavengeRegister(&XCore::GRRegsRegClass, II, 0); in InsertSPConstInst()
/external/llvm-project/llvm/lib/Target/AArch64/
DAArch64A57FPLoadBalancing.cpp141 int scavengeRegister(Chain *G, Color C, MachineBasicBlock &MBB);
496 int AArch64A57FPLoadBalancing::scavengeRegister(Chain *G, Color C, in scavengeRegister() function in AArch64A57FPLoadBalancing
538 int Reg = scavengeRegister(G, C, MBB); in colorChain()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64A57FPLoadBalancing.cpp141 int scavengeRegister(Chain *G, Color C, MachineBasicBlock &MBB);
496 int AArch64A57FPLoadBalancing::scavengeRegister(Chain *G, Color C, in scavengeRegister() function in AArch64A57FPLoadBalancing
538 int Reg = scavengeRegister(G, C, MBB); in colorChain()
/external/llvm/lib/Target/AArch64/
DAArch64A57FPLoadBalancing.cpp146 int scavengeRegister(Chain *G, Color C, MachineBasicBlock &MBB);
498 int AArch64A57FPLoadBalancing::scavengeRegister(Chain *G, Color C, in scavengeRegister() function in AArch64A57FPLoadBalancing
553 int Reg = scavengeRegister(G, C, MBB); in colorChain()
/external/llvm-project/llvm/test/CodeGen/AMDGPU/
Dpei-reg-scavenger-position.mir4 # The wrong form of scavengeRegister was used, so it wasn't accounting
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DSIRegisterInfo.cpp663 SOffset = RS->scavengeRegister(&AMDGPU::SGPR_32RegClass, MI, 0, false); in buildSpillLoadStore()
819 TmpVGPR = RS->scavengeRegister(&AMDGPU::VGPR_32RegClass, MI, 0); in spillSGPR()
908 TmpVGPR = RS->scavengeRegister(&AMDGPU::VGPR_32RegClass, MI, 0); in restoreSGPR()
1086 RS->scavengeRegister(&AMDGPU::SReg_32_XM0RegClass, MI, 0, false); in eliminateFrameIndex()
1094 RS->scavengeRegister(&AMDGPU::VGPR_32RegClass, MI, 0); in eliminateFrameIndex()
1109 RS->scavengeRegister(&AMDGPU::VGPR_32RegClass, MIB, 0); in eliminateFrameIndex()
1150 RS->scavengeRegister(&AMDGPU::SReg_32_XM0RegClass, MI, 0, false); in eliminateFrameIndex()
1218 Register TmpReg = RS->scavengeRegister(&AMDGPU::VGPR_32RegClass, MI, 0); in eliminateFrameIndex()
DSIInstrInfo.cpp663 unsigned Tmp = RS.scavengeRegister(&AMDGPU::VGPR_32RegClass, 0); in copyPhysReg()
671 unsigned Tmp2 = RS.scavengeRegister(&AMDGPU::VGPR_32RegClass, 0); in copyPhysReg()
1275 unsigned STmp0 = RS->scavengeRegister(&AMDGPU::SGPR_32RegClass, 0); in calculateLDSSpillAddress()
1276 unsigned STmp1 = RS->scavengeRegister(&AMDGPU::SGPR_32RegClass, 0); in calculateLDSSpillAddress()
6224 : RS.scavengeRegister(RI.getBoolRC(), I, 0, false); in getAddNoCarry()
/external/llvm-project/llvm/lib/Target/AMDGPU/
DSIRegisterInfo.cpp799 SOffset = RS->scavengeRegister(&AMDGPU::SGPR_32RegClass, MI, 0, false); in buildSpillLoadStore()
872 TmpReg = RS->scavengeRegister(&AMDGPU::VGPR_32RegClass, MI, 0); in buildSpillLoadStore()
1130 Register TmpVGPR = RS->scavengeRegister(&AMDGPU::VGPR_32RegClass, MI, 0); in spillSGPR()
1224 Register TmpVGPR = RS->scavengeRegister(&AMDGPU::VGPR_32RegClass, MI, 0); in restoreSGPR()
1469 Register TmpReg = RS->scavengeRegister(RC, MI, 0, !UseSGPR); in eliminateFrameIndex()
1486 : RS->scavengeRegister(&AMDGPU::SReg_32_XM0RegClass, MI, 0, in eliminateFrameIndex()
1530 : RS->scavengeRegister(&AMDGPU::VGPR_32RegClass, MI, 0); in eliminateFrameIndex()
1582 RS->scavengeRegister(&AMDGPU::SReg_32_XM0RegClass, MI, 0, false); in eliminateFrameIndex()
1651 Register TmpReg = RS->scavengeRegister(&AMDGPU::VGPR_32RegClass, MI, 0); in eliminateFrameIndex()
DSIInstrInfo.cpp602 Register Tmp = RS.scavengeRegister(&AMDGPU::VGPR_32RegClass, 0); in indirectCopyToAGPR()
610 Register Tmp2 = RS.scavengeRegister(&AMDGPU::VGPR_32RegClass, 0); in indirectCopyToAGPR()
7002 : RS.scavengeRegister(RI.getBoolRC(), I, 0, false); in getAddNoCarry()
/external/llvm-project/llvm/lib/Target/Lanai/
DLanaiRegisterInfo.cpp170 Reg = RS->scavengeRegister(&Lanai::GPRRegClass, II, SPAdj); in eliminateFrameIndex()
/external/llvm-project/llvm/lib/Target/ARC/
DARCRegisterInfo.cpp66 BaseReg = RS->scavengeRegister(&ARC::GPR32RegClass, II, SPAdj); in ReplaceFrameIndex()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Lanai/
DLanaiRegisterInfo.cpp175 Reg = RS->scavengeRegister(&Lanai::GPRRegClass, II, SPAdj); in eliminateFrameIndex()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARC/
DARCRegisterInfo.cpp66 BaseReg = RS->scavengeRegister(&ARC::GPR32RegClass, II, SPAdj); in ReplaceFrameIndex()
/external/llvm/lib/Target/Lanai/
DLanaiRegisterInfo.cpp174 Reg = RS->scavengeRegister(&Lanai::GPRRegClass, II, SPAdj); in eliminateFrameIndex()
/external/llvm/lib/CodeGen/
DRegisterScavenging.cpp349 unsigned RegScavenger::scavengeRegister(const TargetRegisterClass *RC, in scavengeRegister() function in RegScavenger
DPrologEpilogInserter.cpp1198 unsigned ScratchReg = RS->scavengeRegister(RC, J, SPAdj); in doScavengeFrameVirtualRegs()
/external/llvm-project/llvm/lib/CodeGen/
DRegisterScavenging.cpp516 Register RegScavenger::scavengeRegister(const TargetRegisterClass *RC, in scavengeRegister() function in RegScavenger
/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/
DRegisterScavenging.cpp535 Register RegScavenger::scavengeRegister(const TargetRegisterClass *RC, in scavengeRegister() function in RegScavenger
/external/llvm/lib/Target/AMDGPU/
DSIInstrInfo.cpp765 unsigned STmp0 = RS->scavengeRegister(&AMDGPU::SGPR_32RegClass, 0); in calculateLDSSpillAddress()
766 unsigned STmp1 = RS->scavengeRegister(&AMDGPU::SGPR_32RegClass, 0); in calculateLDSSpillAddress()