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/external/llvm/test/CodeGen/Mips/cconv/
Dcallee-saved-float.ll33 ; ALL-INV-NOT: sdc1 $f0,
34 ; ALL-INV-NOT: sdc1 $f1,
35 ; ALL-INV-NOT: sdc1 $f2,
36 ; ALL-INV-NOT: sdc1 $f3,
37 ; ALL-INV-NOT: sdc1 $f4,
38 ; ALL-INV-NOT: sdc1 $f5,
39 ; ALL-INV-NOT: sdc1 $f6,
40 ; ALL-INV-NOT: sdc1 $f7,
41 ; ALL-INV-NOT: sdc1 $f8,
42 ; ALL-INV-NOT: sdc1 $f9,
[all …]
Dcallee-saved-fpxx.ll18 ; O32-FPXX-INV-NOT: sdc1 $f0,
19 ; O32-FPXX-INV-NOT: sdc1 $f1,
20 ; O32-FPXX-INV-NOT: sdc1 $f2,
21 ; O32-FPXX-INV-NOT: sdc1 $f3,
22 ; O32-FPXX-INV-NOT: sdc1 $f4,
23 ; O32-FPXX-INV-NOT: sdc1 $f5,
24 ; O32-FPXX-INV-NOT: sdc1 $f6,
25 ; O32-FPXX-INV-NOT: sdc1 $f7,
26 ; O32-FPXX-INV-NOT: sdc1 $f8,
27 ; O32-FPXX-INV-NOT: sdc1 $f9,
[all …]
Darguments-hard-fp128.ll36 ; ALL-DAG: sdc1 $f12, 16([[R2]])
37 ; ALL-DAG: sdc1 $f13, 24([[R2]])
38 ; ALL-DAG: sdc1 $f14, 32([[R2]])
39 ; ALL-DAG: sdc1 $f15, 40([[R2]])
40 ; ALL-DAG: sdc1 $f16, 48([[R2]])
41 ; ALL-DAG: sdc1 $f17, 56([[R2]])
42 ; ALL-DAG: sdc1 $f18, 64([[R2]])
43 ; ALL-DAG: sdc1 $f19, 72([[R2]])
Darguments-hard-float.ll57 ; ALL-DAG: sdc1 $f12, 8([[R2]])
58 ; O32-DAG: sdc1 $f14, 16([[R2]])
59 ; NEW-DAG: sdc1 $f13, 16([[R2]])
63 ; O32-DAG: sdc1 [[F1]], 24([[R2]])
64 ; NEW-DAG: sdc1 $f14, 24([[R2]])
66 ; O32-DAG: sdc1 [[F1]], 32([[R2]])
67 ; NEW-DAG: sdc1 $f15, 32([[R2]])
69 ; O32-DAG: sdc1 [[F1]], 40([[R2]])
70 ; NEW-DAG: sdc1 $f16, 40([[R2]])
72 ; O32-DAG: sdc1 [[F1]], 48([[R2]])
[all …]
Dcallee-saved-fpxx1.ll20 ; O32-FP64-INV-NOT: sdc1 $f20,
21 ; O32-FPXX-DAG: sdc1 [[F20:\$f20]], [[OFF20:[0-9]+]]($sp)
/external/llvm-project/llvm/test/CodeGen/Mips/cconv/
Dcallee-saved-float.ll33 ; ALL-INV-NOT: sdc1 $f0,
34 ; ALL-INV-NOT: sdc1 $f1,
35 ; ALL-INV-NOT: sdc1 $f2,
36 ; ALL-INV-NOT: sdc1 $f3,
37 ; ALL-INV-NOT: sdc1 $f4,
38 ; ALL-INV-NOT: sdc1 $f5,
39 ; ALL-INV-NOT: sdc1 $f6,
40 ; ALL-INV-NOT: sdc1 $f7,
41 ; ALL-INV-NOT: sdc1 $f8,
42 ; ALL-INV-NOT: sdc1 $f9,
[all …]
Dcallee-saved-fpxx.ll18 ; O32-FPXX-INV-NOT: sdc1 $f0,
19 ; O32-FPXX-INV-NOT: sdc1 $f1,
20 ; O32-FPXX-INV-NOT: sdc1 $f2,
21 ; O32-FPXX-INV-NOT: sdc1 $f3,
22 ; O32-FPXX-INV-NOT: sdc1 $f4,
23 ; O32-FPXX-INV-NOT: sdc1 $f5,
24 ; O32-FPXX-INV-NOT: sdc1 $f6,
25 ; O32-FPXX-INV-NOT: sdc1 $f7,
26 ; O32-FPXX-INV-NOT: sdc1 $f8,
27 ; O32-FPXX-INV-NOT: sdc1 $f9,
[all …]
Darguments-hard-fp128.ll36 ; ALL-DAG: sdc1 $f12, 16([[R2]])
37 ; ALL-DAG: sdc1 $f13, 24([[R2]])
38 ; ALL-DAG: sdc1 $f14, 32([[R2]])
39 ; ALL-DAG: sdc1 $f15, 40([[R2]])
40 ; ALL-DAG: sdc1 $f16, 48([[R2]])
41 ; ALL-DAG: sdc1 $f17, 56([[R2]])
42 ; ALL-DAG: sdc1 $f18, 64([[R2]])
43 ; ALL-DAG: sdc1 $f19, 72([[R2]])
Darguments-hard-float.ll57 ; ALL-DAG: sdc1 $f12, 8([[R2]])
58 ; O32-DAG: sdc1 $f14, 16([[R2]])
59 ; NEW-DAG: sdc1 $f13, 16([[R2]])
63 ; O32-DAG: sdc1 [[F1]], 24([[R2]])
64 ; NEW-DAG: sdc1 $f14, 24([[R2]])
66 ; O32-DAG: sdc1 [[F1]], 32([[R2]])
67 ; NEW-DAG: sdc1 $f15, 32([[R2]])
69 ; O32-DAG: sdc1 [[F1]], 40([[R2]])
70 ; NEW-DAG: sdc1 $f16, 40([[R2]])
72 ; O32-DAG: sdc1 [[F1]], 48([[R2]])
[all …]
Dcallee-saved-fpxx1.ll22 ; O32-FP64-INV-NOT: sdc1 $f20,
23 ; O32-FPXX-DAG: sdc1 [[F20:\$f20]], [[OFF20:[0-9]+]]($sp)
/external/llvm-project/libunwind/src/
DUnwindRegistersSave.S171 sdc1 $f0, (4 * 36 + 8 * 0)($4)
172 sdc1 $f2, (4 * 36 + 8 * 2)($4)
173 sdc1 $f4, (4 * 36 + 8 * 4)($4)
174 sdc1 $f6, (4 * 36 + 8 * 6)($4)
175 sdc1 $f8, (4 * 36 + 8 * 8)($4)
176 sdc1 $f10, (4 * 36 + 8 * 10)($4)
177 sdc1 $f12, (4 * 36 + 8 * 12)($4)
178 sdc1 $f14, (4 * 36 + 8 * 14)($4)
179 sdc1 $f16, (4 * 36 + 8 * 16)($4)
180 sdc1 $f18, (4 * 36 + 8 * 18)($4)
[all …]
/external/llvm-project/compiler-rt/lib/xray/
Dxray_trampoline_mips64.S36 sdc1 $f19, 56($sp)
37 sdc1 $f18, 48($sp)
38 sdc1 $f17, 40($sp)
39 sdc1 $f16, 32($sp)
40 sdc1 $f15, 24($sp)
41 sdc1 $f14, 16($sp)
42 sdc1 $f13, 8($sp)
43 sdc1 $f12, 0($sp)
101 sdc1 $f2, 16($sp)
102 sdc1 $f1, 8($sp)
[all …]
Dxray_trampoline_mips.S34 sdc1 $f14, 8($sp)
35 sdc1 $f12, 0($sp)
81 sdc1 $f2, 8($sp)
82 sdc1 $f0, 0($sp)
/external/llvm/test/CodeGen/Mips/
Dmno-ldc1-sdc1.ll13 ; Check that -mno-ldc1-sdc1 disables [sl]dc1
14 ; RUN: llc -march=mipsel -relocation-model=pic -mno-ldc1-sdc1 \
17 ; RUN: llc -march=mipsel -relocation-model=pic -mno-ldc1-sdc1 \
20 ; RUN: llc -march=mipsel -relocation-model=pic -mno-ldc1-sdc1 \
23 ; RUN: llc -march=mipsel -relocation-model=pic -mno-ldc1-sdc1 -mcpu=mips32r3 \
26 ; RUN: llc -march=mipsel -relocation-model=pic -mno-ldc1-sdc1 -mcpu=mips32r6 \
31 ; RUN: llc -march=mips -relocation-model=pic -mno-ldc1-sdc1 \
34 ; RUN: llc -march=mips -relocation-model=pic -mno-ldc1-sdc1 \
37 ; RUN: llc -march=mips -relocation-model=pic -mno-ldc1-sdc1 \
40 ; RUN: llc -march=mips -relocation-model=pic -mno-ldc1-sdc1 -mcpu=mips32r3 \
[all …]
Dmips64-f128-call.ll7 ; CHECK: sdc1 $f13, 8(${{[0-9]+}})
8 ; CHECK: sdc1 $f12, 0(${{[0-9]+}})
31 ; CHECK: sdc1 $f2, 8($[[R0]])
32 ; CHECK: sdc1 $f0, 0($[[R0]])
Dfastcc.ll374 ; FP64-NOODDSPREG-DAG: sdc1 $[[F0]], 0($sp)
406 ; FP64-NOODDSPREG-DAG: sdc1 $f0, 0($[[R0]])
407 ; FP64-NOODDSPREG-DAG: sdc1 $f2, 8($[[R0]])
408 ; FP64-NOODDSPREG-DAG: sdc1 $f4, 16($[[R0]])
409 ; FP64-NOODDSPREG-DAG: sdc1 $f6, 24($[[R0]])
410 ; FP64-NOODDSPREG-DAG: sdc1 $f8, 32($[[R0]])
411 ; FP64-NOODDSPREG-DAG: sdc1 $f10, 40($[[R0]])
412 ; FP64-NOODDSPREG-DAG: sdc1 $f12, 48($[[R0]])
413 ; FP64-NOODDSPREG-DAG: sdc1 $f14, 56($[[R0]])
414 ; FP64-NOODDSPREG-DAG: sdc1 $f16, 64($[[R0]])
[all …]
Dcfi_offset.ll17 ; CHECK: sdc1 $f22, 32($sp)
18 ; CHECK: sdc1 $f20, 24($sp)
/external/llvm-project/llvm/test/CodeGen/Mips/
Dmno-ldc1-sdc1.ll13 ; Check that -mno-ldc1-sdc1 disables [sl]dc1
14 ; RUN: llc -march=mipsel -relocation-model=pic -mno-ldc1-sdc1 \
17 ; RUN: llc -march=mipsel -relocation-model=pic -mno-ldc1-sdc1 \
20 ; RUN: llc -march=mipsel -relocation-model=pic -mno-ldc1-sdc1 \
23 ; RUN: llc -march=mipsel -relocation-model=pic -mno-ldc1-sdc1 -mcpu=mips32r3 \
26 ; RUN: llc -march=mipsel -relocation-model=pic -mno-ldc1-sdc1 -mcpu=mips32r6 \
31 ; RUN: llc -march=mips -relocation-model=pic -mno-ldc1-sdc1 \
34 ; RUN: llc -march=mips -relocation-model=pic -mno-ldc1-sdc1 \
37 ; RUN: llc -march=mips -relocation-model=pic -mno-ldc1-sdc1 \
40 ; RUN: llc -march=mips -relocation-model=pic -mno-ldc1-sdc1 -mcpu=mips32r3 \
[all …]
Dmips64-f128-call.ll7 ; CHECK-DAG: sdc1 $f12, %lo(gld0)(${{[0-9]+}})
8 ; CHECK-DAG: sdc1 $f13, 8(${{[0-9]+}})
33 ; CHECK: sdc1 $f0, %lo(gld0)($[[R1]])
34 ; CHECK: sdc1 $f2, 8($[[R2]])
Dfastcc.ll371 ; FP64-NOODDSPREG-DAG: sdc1 $[[F0]], 0($sp)
402 ; FP64-NOODDSPREG-DAG: sdc1 $f0, 0($[[R0]])
403 ; FP64-NOODDSPREG-DAG: sdc1 $f2, 8($[[R0]])
404 ; FP64-NOODDSPREG-DAG: sdc1 $f4, 16($[[R0]])
405 ; FP64-NOODDSPREG-DAG: sdc1 $f6, 24($[[R0]])
406 ; FP64-NOODDSPREG-DAG: sdc1 $f8, 32($[[R0]])
407 ; FP64-NOODDSPREG-DAG: sdc1 $f10, 40($[[R0]])
408 ; FP64-NOODDSPREG-DAG: sdc1 $f12, 48($[[R0]])
409 ; FP64-NOODDSPREG-DAG: sdc1 $f14, 56($[[R0]])
410 ; FP64-NOODDSPREG-DAG: sdc1 $f16, 64($[[R0]])
[all …]
Dcfi_offset.ll17 ; CHECK: sdc1 $f22, 32($sp)
18 ; CHECK: sdc1 $f20, 24($sp)
/external/llvm-project/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/
Dlong_ambiguous_chain_s64.ll47 ; MIPS32-NEXT: sdc1 $f0, 32($sp) # 8-byte Folded Spill
53 ; MIPS32-NEXT: sdc1 $f0, 32($sp) # 8-byte Folded Spill
59 ; MIPS32-NEXT: sdc1 $f0, 32($sp) # 8-byte Folded Spill
63 ; MIPS32-NEXT: sdc1 $f0, 16($sp) # 8-byte Folded Spill
65 ; MIPS32-NEXT: sdc1 $f0, 24($sp) # 8-byte Folded Spill
74 ; MIPS32-NEXT: sdc1 $f0, 0($1)
89 ; MIPS32-NEXT: sdc1 $f0, 8($sp) # 8-byte Folded Spill
95 ; MIPS32-NEXT: sdc1 $f0, 8($sp) # 8-byte Folded Spill
99 ; MIPS32-NEXT: sdc1 $f0, 0($sp) # 8-byte Folded Spill
101 ; MIPS32-NEXT: sdc1 $f0, 24($sp) # 8-byte Folded Spill
[all …]
Dphi.ll222 ; MIPS32-NEXT: sdc1 $f0, 16($sp) # 8-byte Folded Spill
224 ; MIPS32-NEXT: sdc1 $f0, 24($sp) # 8-byte Folded Spill
233 ; MIPS32-NEXT: sdc1 $f0, 0($sp) # 8-byte Folded Spill
238 ; MIPS32-NEXT: sdc1 $f0, 0($sp) # 8-byte Folded Spill
242 ; MIPS32-NEXT: sdc1 $f0, 0($1)
357 ; MIPS32-NEXT: sdc1 $f12, 8($sp) # 8-byte Folded Spill
358 ; MIPS32-NEXT: sdc1 $f14, 16($sp) # 8-byte Folded Spill
369 ; MIPS32-NEXT: sdc1 $f0, 0($sp) # 8-byte Folded Spill
374 ; MIPS32-NEXT: sdc1 $f0, 0($sp) # 8-byte Folded Spill
/external/llvm/test/MC/Mips/
Delf-relsym.s63 sdc1 $f0, 0($2)
67 sdc1 $f0, 0($1)
/external/llvm-project/llvm/test/MC/Mips/
Delf-relsym.s63 sdc1 $f0, 0($2)
67 sdc1 $f0, 0($1)

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