| /external/llvm/test/Transforms/InstCombine/ |
| D | select-select.ll | 26 ; CHECK: %[[sel0:.*]] = select <2 x i1> %vec_bool, <2 x i32> zeroinitializer, <2 x i32> %V
27 ; CHECK: %[[sel1:.*]] = select i1 %bool, <2 x i32> %[[sel0]], <2 x i32> %V
29 %sel0 = select <2 x i1> %vec_bool, <2 x i32> zeroinitializer, <2 x i32> %V
30 %sel1 = select i1 %bool, <2 x i32> %sel0, <2 x i32> %V
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| D | sub.ll | 555 %sel0 = select i1 %A, i32 %D, i32 %B
557 %sub = sub i32 %sel0, %sel1
566 %sel0 = select i1 %A, i32 %B, i32 %D
568 %sub = sub i32 %sel0, %sel1
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| D | add2.ll | 400 %sel0 = select i1 %A, i32 0, i32 -2
402 %add = add i32 %sel0, %sel1
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| /external/llvm-project/llvm/test/CodeGen/SystemZ/ |
| D | signbits.ll | 2 ; DAGCombiner so that it knows that %sel0 is already sign extended.
16 %sel0 = select i1 %icmp0, i16 %Arg1, i16 1
24 %phi0 = phi i16 [ 2, %entry ], [ %sel0, %lab0 ]
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| D | fp-cmp-02.ll | 146 %sel0 = select i1 %cmp0, double %ret, double 0.0
147 %sel1 = select i1 %cmp1, double %sel0, double 1.0
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| D | fp-strict-cmps-02.ll | 197 %sel0 = select i1 %cmp0, double %ret, double 0.0
198 %sel1 = select i1 %cmp1, double %sel0, double 1.0
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| D | fp-strict-cmp-02.ll | 197 %sel0 = select i1 %cmp0, double %ret, double 0.0
198 %sel1 = select i1 %cmp1, double %sel0, double 1.0
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| D | int-cmp-05.ll | 280 %sel0 = select i1 %cmp0, i64 %ret, i64 0
281 %sel1 = select i1 %cmp1, i64 %sel0, i64 1
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| D | fp-cmp-01.ll | 146 %sel0 = select i1 %cmp0, float %ret, float 0.0
147 %sel1 = select i1 %cmp1, float %sel0, float 1.0
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| D | int-cmp-06.ll | 330 %sel0 = select i1 %cmp0, i64 %ret, i64 0
331 %sel1 = select i1 %cmp1, i64 %sel0, i64 1
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| /external/llvm-project/llvm/test/CodeGen/AMDGPU/ |
| D | sminmax.v2i16.ll | 168 %sel0 = select <2 x i1> %cond0, <2 x i16> %val0, <2 x i16> %val1
171 store volatile <2 x i16> %sel0, <2 x i16> addrspace(1)* %out0, align 4
184 %sel0 = select <2 x i1> %cond0, <2 x i16> %val0, <2 x i16> %val1
187 store volatile <2 x i16> %sel0, <2 x i16> addrspace(1)* %out0, align 4
199 %sel0 = select <4 x i1> %cond0, <4 x i16> %val0, <4 x i16> %val1
202 store volatile <4 x i16> %sel0, <4 x i16> addrspace(1)* %out0, align 4
213 %sel0 = select <2 x i1> %cond0, <2 x i16> %val0, <2 x i16> %val1
216 store volatile <2 x i16> %sel0, <2 x i16> addrspace(1)* %out0, align 4
227 %sel0 = select <2 x i1> %cond0, <2 x i16> %val0, <2 x i16> %val1
230 store volatile <2 x i16> %sel0, <2 x i16> addrspace(1)* %out0, align 4
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| D | sminmax.ll | 206 %sel0 = select i1 %cond0, i32 %val0, i32 %val1
209 store volatile i32 %sel0, i32 addrspace(1)* %out0, align 4
225 %sel0 = select i1 %cond0, i32 %val0, i32 %val1
228 store volatile i32 %sel0, i32 addrspace(1)* %out0, align 4
244 %sel0 = select <4 x i1> %cond0, <4 x i32> %val0, <4 x i32> %val1
247 store volatile <4 x i32> %sel0, <4 x i32> addrspace(1)* %out0, align 4
262 %sel0 = select i1 %cond0, i32 %val0, i32 %val1
265 store volatile i32 %sel0, i32 addrspace(1)* %out0, align 4
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| D | sext-in-reg.ll | 397 %sel0 = select i1 %cmp_slt, i8 0, i8 %a
399 %xor = xor i8 %sel0, %sel1
409 %sel0 = select i1 %cmp_slt, i8 0, i8 %a
411 %xor = xor i8 %sel0, %sel1
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| /external/llvm/test/CodeGen/AMDGPU/ |
| D | sminmax.ll | 161 %sel0 = select i1 %cond0, i32 %val0, i32 %val1
164 store volatile i32 %sel0, i32 addrspace(1)* %out0, align 4
180 %sel0 = select i1 %cond0, i32 %val0, i32 %val1
183 store volatile i32 %sel0, i32 addrspace(1)* %out0, align 4
199 %sel0 = select <4 x i1> %cond0, <4 x i32> %val0, <4 x i32> %val1
202 store volatile <4 x i32> %sel0, <4 x i32> addrspace(1)* %out0, align 4
217 %sel0 = select i1 %cond0, i32 %val0, i32 %val1
220 store volatile i32 %sel0, i32 addrspace(1)* %out0, align 4
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| D | sext-in-reg.ll | 374 %sel0 = select i1 %cmp_slt, i8 0, i8 %a
376 %xor = xor i8 %sel0, %sel1
386 %sel0 = select i1 %cmp_slt, i8 0, i8 %a
388 %xor = xor i8 %sel0, %sel1
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| /external/llvm-project/llvm/test/CodeGen/AArch64/ |
| D | dag-combine-select.ll | 16 %sel0 = select i1 %cmp1, i32 %v1, i32 %v2
17 %sel1 = select i1 %cmp2, i32 %v1, i32 %sel0
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| /external/llvm/test/CodeGen/AArch64/ |
| D | dag-combine-select.ll | 16 %sel0 = select i1 %cmp1, i32 %v1, i32 %v2
17 %sel1 = select i1 %cmp2, i32 %v1, i32 %sel0
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| /external/llvm/test/CodeGen/X86/ |
| D | cmovcmov.ll | 270 %sel0 = select i1 %c1, i8 20, i8 %trunc
271 %sel1 = select i1 %c2, i8 20, i8 %sel0
272 %sel2 = select i1 %c0, i8 %sel1, i8 %sel0
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| /external/llvm-project/llvm/test/CodeGen/X86/ |
| D | cmovcmov.ll | 357 %sel0 = select i1 %c1, i8 20, i8 %trunc
358 %sel1 = select i1 %c2, i8 20, i8 %sel0
359 %sel2 = select i1 %c0, i8 %sel1, i8 %sel0
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| /external/llvm/test/CodeGen/SystemZ/ |
| D | fp-cmp-02.ll | 146 %sel0 = select i1 %cmp0, double %ret, double 0.0
147 %sel1 = select i1 %cmp1, double %sel0, double 1.0
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| D | fp-cmp-01.ll | 137 %sel0 = select i1 %cmp0, float %ret, float 0.0
138 %sel1 = select i1 %cmp1, float %sel0, float 1.0
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| D | int-cmp-05.ll | 280 %sel0 = select i1 %cmp0, i64 %ret, i64 0
281 %sel1 = select i1 %cmp1, i64 %sel0, i64 1
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| D | int-cmp-06.ll | 330 %sel0 = select i1 %cmp0, i64 %ret, i64 0
331 %sel1 = select i1 %cmp1, i64 %sel0, i64 1
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| /external/llvm-project/llvm/test/Transforms/InstCombine/ |
| D | select-select.ll | 42 %sel0 = select <2 x i1> %vec_bool, <2 x i32> zeroinitializer, <2 x i32> %V
43 %sel1 = select i1 %bool, <2 x i32> %sel0, <2 x i32> %V
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| D | add2.ll | 470 %sel0 = select i1 %A, i32 0, i32 -2
472 %add = add i32 %sel0, %sel1
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