Searched refs:seqz (Results 1 – 23 of 23) sorted by relevance
/external/llvm-project/llvm/test/CodeGen/RISCV/ |
D | get-setcc-result-type.ll | 12 ; RV32I-NEXT: seqz a1, a1 13 ; RV32I-NEXT: seqz a2, a2 14 ; RV32I-NEXT: seqz a3, a3 15 ; RV32I-NEXT: seqz a4, a4
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D | i32-icmp.ll | 5 ; TODO: check the generated instructions for the equivalent of seqz, snez, 12 ; RV32I-NEXT: seqz a0, a0 23 ; RV32I-NEXT: seqz a0, a0 34 ; RV32I-NEXT: seqz a0, a0 46 ; RV32I-NEXT: seqz a0, a0 57 ; RV32I-NEXT: seqz a0, a0 67 ; RV32I-NEXT: seqz a0, a0
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D | float-isnan.ll | 11 ; RV32IF-NEXT: seqz a0, a0 17 ; RV64IF-NEXT: seqz a0, a0
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D | double-isnan.ll | 11 ; RV32IFD-NEXT: seqz a0, a0 17 ; RV64IFD-NEXT: seqz a0, a0
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D | setcc-logic.ll | 13 ; RV32I-NEXT: seqz a0, a0 23 ; RV64I-NEXT: seqz a0, a0 64 ; RV32I-NEXT: seqz a0, a0 71 ; RV64I-NEXT: seqz a0, a0
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D | half-isnan.ll | 11 ; RV32IZFH-NEXT: seqz a0, a0 17 ; RV64IZFH-NEXT: seqz a0, a0
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D | half-fcmp.ll | 148 ; RV32IZFH-NEXT: seqz a1, a1 158 ; RV64IZFH-NEXT: seqz a1, a1 257 ; RV32IZFH-NEXT: seqz a0, a0 265 ; RV64IZFH-NEXT: seqz a0, a0
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D | atomic-cmpxchg-flag.ll | 22 ; RV64IA-NEXT: seqz a0, a0
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D | float-fcmp.ll | 178 ; RV32IF-NEXT: seqz a1, a1 190 ; RV64IF-NEXT: seqz a1, a1 311 ; RV32IF-NEXT: seqz a0, a0 321 ; RV64IF-NEXT: seqz a0, a0
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D | half-select-fcmp.ll | 205 ; RV32IZFH-NEXT: seqz a1, a1 219 ; RV64IZFH-NEXT: seqz a1, a1 363 ; RV32IZFH-NEXT: seqz a0, a0 375 ; RV64IZFH-NEXT: seqz a0, a0
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D | sext-zext-trunc.ll | 527 ; RV32I-NEXT: seqz a0, a0 536 ; RV64I-NEXT: seqz a0, a0 550 ; RV32I-NEXT: seqz a1, a0 559 ; RV64I-NEXT: seqz a0, a0
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D | double-fcmp.ll | 225 ; RV32IFD-NEXT: seqz a1, a1 238 ; RV64IFD-NEXT: seqz a1, a1 394 ; RV32IFD-NEXT: seqz a0, a0 405 ; RV64IFD-NEXT: seqz a0, a0
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D | calling-conv-lp64-lp64f-lp64d-common.ll | 62 ; RV64I-NEXT: seqz a1, a1 125 ; RV64I-NEXT: seqz a0, a0 180 ; RV64I-NEXT: seqz a0, a0 249 ; RV64I-NEXT: seqz a0, a0 411 ; RV64I-NEXT: seqz a0, a0
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D | calling-conv-ilp32-ilp32f-ilp32d-common.ll | 96 ; RV32I-FPELIM-NEXT: seqz a1, a1 120 ; RV32I-WITHFP-NEXT: seqz a1, a1 210 ; RV32I-FPELIM-NEXT: seqz a0, a0 234 ; RV32I-WITHFP-NEXT: seqz a0, a0 317 ; RV32I-FPELIM-NEXT: seqz a0, a0 342 ; RV32I-WITHFP-NEXT: seqz a0, a0 469 ; RV32I-FPELIM-NEXT: seqz a0, a0 479 ; RV32I-WITHFP-NEXT: seqz a0, a0 798 ; RV32I-FPELIM-NEXT: seqz a0, a0 817 ; RV32I-WITHFP-NEXT: seqz a0, a0
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D | float-select-fcmp.ll | 249 ; RV32IF-NEXT: seqz a1, a1 266 ; RV64IF-NEXT: seqz a1, a1 443 ; RV32IF-NEXT: seqz a0, a0 458 ; RV64IF-NEXT: seqz a0, a0
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D | double-select-fcmp.ll | 311 ; RV32IFD-NEXT: seqz a1, a1 331 ; RV64IFD-NEXT: seqz a1, a1 553 ; RV32IFD-NEXT: seqz a0, a0 571 ; RV64IFD-NEXT: seqz a0, a0
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D | half-br-fcmp.ll | 355 ; RV32IZFH-NEXT: seqz a1, a1 373 ; RV64IZFH-NEXT: seqz a1, a1 585 ; RV32IZFH-NEXT: seqz a0, a0 601 ; RV64IZFH-NEXT: seqz a0, a0
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D | float-br-fcmp.ll | 389 ; RV32IF-NEXT: seqz a1, a1 409 ; RV64IF-NEXT: seqz a1, a1 643 ; RV32IF-NEXT: seqz a0, a0 661 ; RV64IF-NEXT: seqz a0, a0
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D | double-br-fcmp.ll | 424 ; RV32IFD-NEXT: seqz a1, a1 444 ; RV64IFD-NEXT: seqz a1, a1 702 ; RV32IFD-NEXT: seqz a0, a0 720 ; RV64IFD-NEXT: seqz a0, a0
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D | rv64i-single-softfloat.ll | 68 ; RV64I-NEXT: seqz a0, a0 148 ; RV64I-NEXT: seqz a0, a0
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/external/llvm-project/llvm/test/MC/RISCV/ |
D | rvi-aliases-valid.s | 53 # CHECK-S-OBJ: seqz t6, ra 54 seqz x31, x1 label
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/ |
D | RISCVInstrInfo.td | 599 def : InstAlias<"seqz $rd, $rs", (SLTIU GPR:$rd, GPR:$rs, 1)>;
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/external/llvm-project/llvm/lib/Target/RISCV/ |
D | RISCVInstrInfo.td | 661 def : InstAlias<"seqz $rd, $rs", (SLTIU GPR:$rd, GPR:$rs, 1)>;
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