| /external/llvm-project/llvm/test/CodeGen/X86/ |
| D | dagcombine-and-setcc.ll | 10 ; (and (setgt X, true), (setgt Y, true)) -> (setgt (or X, Y), true)
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| D | fmf-propagation.ll | 41 … t14: i8 = setcc nnan ninf nsz arcp contract afn reassoc t2, ConstantFP:f32<0.000000e+00>, setgt:ch
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| /external/llvm/test/CodeGen/X86/ |
| D | dagcombine-and-setcc.ll | 10 ; (and (setgt X, true), (setgt Y, true)) -> (setgt (or X, Y), true)
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| D | HexagonPatternsHVX.td | 253 defm: MinMax_pats<V6_vminb, V6_vmaxb, vselect, setgt, VecQ8, HVI8>;
257 defm: MinMax_pats<V6_vminh, V6_vmaxh, vselect, setgt, VecQ16, HVI16>;
261 defm: MinMax_pats<V6_vminw, V6_vmaxw, vselect, setgt, VecQ32, HVI32>;
465 def: OpR_RR_pat<V6_vgtb, setgt, VecQ8, HVI8>;
466 def: OpR_RR_pat<V6_vgth, setgt, VecQ16, HVI16>;
467 def: OpR_RR_pat<V6_vgtw, setgt, VecQ32, HVI32>;
482 def: AccRRR_pat<V6_vgtb_and, And, setgt, HQ8, HVI8, HVI8>;
483 def: AccRRR_pat<V6_vgtb_or, Or, setgt, HQ8, HVI8, HVI8>;
484 def: AccRRR_pat<V6_vgtb_xor, Xor, setgt, HQ8, HVI8, HVI8>;
485 def: AccRRR_pat<V6_vgth_and, And, setgt, HQ16, HVI16, HVI16>;
[all …]
|
| D | HexagonPatterns.td | 577 def: OpR_RI_pat<C2_cmpgti, setgt, i1, I32, anyimm>;
597 def: OpR_RR_pat<C2_cmpgt, setgt, i1, I32>;
602 def: OpR_RR_pat<C2_cmpgtp, setgt, i1, I64>;
610 def: OpR_RR_pat<A4_vcmpbgt, setgt, i1, V8I8>;
611 def: OpR_RR_pat<A4_vcmpbgt, setgt, v8i1, V8I8>;
620 def: OpR_RR_pat<A2_vcmphgt, setgt, i1, V4I16>;
621 def: OpR_RR_pat<A2_vcmphgt, setgt, v4i1, V4I16>;
630 def: OpR_RR_pat<A2_vcmpwgt, setgt, i1, V2I32>;
631 def: OpR_RR_pat<A2_vcmpwgt, setgt, v2i1, V2I32>;
638 def: OpR_RR_pat<F2_sfcmpgt, setgt, i1, F32>;
[all …]
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| /external/llvm-project/llvm/test/CodeGen/PowerPC/ |
| D | ppc64-P9-setb.ll | 35 ; select_cc lhs, rhs, -1, (zext (setcc rhs, lhs, setne)), setgt
87 ; select_cc lhs, rhs, -1, (zext (setcc lhs, rhs, setne)), setgt
113 ; select_cc lhs, rhs, -1, (zext (setcc lhs, rhs, setgt)), setlt
143 ; select_cc lhs, rhs, -1, (zext (setcc rhs, lhs, setgt)), setgt
203 ; select_cc lhs, rhs, -1, (zext (setcc lhs, rhs, setlt)), setgt
233 ; select_cc lhs, rhs, 1, (sext (setcc lhs, rhs, setne)), setgt
285 ; select_cc lhs, rhs, 1, (sext (setcc rhs, lhs, setne)), setgt
337 ; select_cc lhs, rhs, 1, (sext (setcc lhs, rhs, setlt)), setgt
401 ; select_cc lhs, rhs, 1, (sext (setcc rhs, lhs, setgt)), setgt
433 ; select_cc lhs, rhs, 1, (sext (setcc lhs, rhs, setgt)), setlt
[all …]
|
| D | add_cmp.ll | 28 ; CHECK: {{t[0-9]+}}: i1 = setcc [[REG2]], Constant:i32<30>, setgt:ch
54 ; CHECK: {{t[0-9]+}}: i1 = setcc [[REG2]], Constant:i16<-32767>, setgt:ch
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| /external/llvm-project/clang/test/CodeGen/ |
| D | BasicInstrs.c | 23 _Bool setgt(int X, int Y) { in setgt() function
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| /external/clang/test/CodeGen/ |
| D | BasicInstrs.c | 23 _Bool setgt(int X, int Y) { in setgt() function
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| /external/llvm-project/llvm/lib/Target/Hexagon/ |
| D | HexagonPatternsHVX.td | 549 def: OpR_RR_pat<V6_vgtb, setgt, VecQ8, HVI8>;
550 def: OpR_RR_pat<V6_vgth, setgt, VecQ16, HVI16>;
551 def: OpR_RR_pat<V6_vgtw, setgt, VecQ32, HVI32>;
566 def: AccRRR_pat<V6_vgtb_and, And, setgt, HQ8, HVI8, HVI8>;
567 def: AccRRR_pat<V6_vgtb_or, Or, setgt, HQ8, HVI8, HVI8>;
568 def: AccRRR_pat<V6_vgtb_xor, Xor, setgt, HQ8, HVI8, HVI8>;
569 def: AccRRR_pat<V6_vgth_and, And, setgt, HQ16, HVI16, HVI16>;
570 def: AccRRR_pat<V6_vgth_or, Or, setgt, HQ16, HVI16, HVI16>;
571 def: AccRRR_pat<V6_vgth_xor, Xor, setgt, HQ16, HVI16, HVI16>;
572 def: AccRRR_pat<V6_vgtw_and, And, setgt, HQ32, HVI32, HVI32>;
[all …]
|
| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonSelectCCInfo.td | 100 // setgt-64.
111 // setlt-64 -> setgt-64.
|
| D | HexagonInstrInfoV3.td | 146 defm: MinMax_pats_p<setgt, A2_maxp, A2_minp>;
174 //def : Pat <(brcond (i1 (setgt (i32 IntRegs:$src1), -1)), bb:$offset),
|
| D | HexagonInstrInfoVector.td | 228 def: vcmp_vi1_pat<A2_vcmpwgt, setgt, V2I32, v2i1>;
232 def: vcmp_vi1_pat<A2_vcmphgt, setgt, V4I16, v4i1>;
286 def: Pat<(i1 (setgt V4I8:$Rs, V4I8:$Rt)),
293 def: Pat<(i1 (setgt V2I16:$Rs, V2I16:$Rt)),
|
| /external/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyInstrFloat.td | 69 def : Pat<(setgt f32:$lhs, f32:$rhs), (GT_F32 f32:$lhs, f32:$rhs)>;
75 def : Pat<(setgt f64:$lhs, f64:$rhs), (GT_F64 f64:$lhs, f64:$rhs)>;
|
| /external/llvm-project/llvm/test/CodeGen/MSP430/ |
| D | shift-amount-threshold.ll | 57 ; sext i1 (setgt iN X, -1) --> sra (not X), (N - 1)
76 ; zext i1 (setgt iN X, -1) --> srl (not X), (N - 1)
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyInstrFloat.td | 93 def : Pat<(setgt f32:$lhs, f32:$rhs), (GT_F32 f32:$lhs, f32:$rhs)>;
99 def : Pat<(setgt f64:$lhs, f64:$rhs), (GT_F64 f64:$lhs, f64:$rhs)>;
|
| /external/llvm-project/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyInstrFloat.td | 93 def : Pat<(setgt f32:$lhs, f32:$rhs), (GT_F32 f32:$lhs, f32:$rhs)>;
99 def : Pat<(setgt f64:$lhs, f64:$rhs), (GT_F64 f64:$lhs, f64:$rhs)>;
|
| /external/clang/www/demo/ |
| D | index.cgi | 99 …$input =~ s@\b(add|sub|mul|div|rem|and|or|xor|setne|seteq|setlt|setgt|setle|setge|phi|tail|call|ca…
|
| /external/llvm-project/clang/www/demo/ |
| D | index.cgi | 99 …$input =~ s@\b(add|sub|mul|div|rem|and|or|xor|setne|seteq|setlt|setgt|setle|setge|phi|tail|call|ca…
|
| /external/llvm-project/llvm/lib/Target/Mips/ |
| D | Mips16InstrInfo.td | 1442 // bcond-setgt (do we need to have this pair of setlt, setgt??)
1445 <(brcond (i32 (setgt CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1575 def : Mips16Pat<(select (i32 (setgt CPU16Regs:$a, CPU16Regs:$b)),
1775 <(setgt CPU16Regs:$lhs, -32769),
1780 // setgt
1785 <(setgt CPU16Regs:$lhs, CPU16Regs:$rhs),
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| /external/llvm/lib/Target/Mips/ |
| D | Mips16InstrInfo.td | 1447 // bcond-setgt (do we need to have this pair of setlt, setgt??)
1450 <(brcond (i32 (setgt CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1580 def : Mips16Pat<(select (i32 (setgt CPU16Regs:$a, CPU16Regs:$b)),
1780 <(setgt CPU16Regs:$lhs, -32769),
1785 // setgt
1790 <(setgt CPU16Regs:$lhs, CPU16Regs:$rhs),
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| D | Mips16InstrInfo.td | 1442 // bcond-setgt (do we need to have this pair of setlt, setgt??)
1445 <(brcond (i32 (setgt CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1575 def : Mips16Pat<(select (i32 (setgt CPU16Regs:$a, CPU16Regs:$b)),
1775 <(setgt CPU16Regs:$lhs, -32769),
1780 // setgt
1785 <(setgt CPU16Regs:$lhs, CPU16Regs:$rhs),
|
| /external/llvm-project/llvm/lib/Target/XCore/ |
| D | XCoreInstrInfo.td | 1231 def : Pat<(setgt GRRegs:$lhs, GRRegs:$rhs),
1295 // setge X, 0 is canonicalized to setgt X, -1
1296 def : Pat<(brcond (setgt GRRegs:$lhs, -1), bb:$dst),
1302 def : Pat<(select (setgt GRRegs:$lhs, -1), GRRegs:$T, GRRegs:$F),
1305 def : Pat<(setgt GRRegs:$lhs, -1),
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/XCore/ |
| D | XCoreInstrInfo.td | 1228 def : Pat<(setgt GRRegs:$lhs, GRRegs:$rhs),
1292 // setge X, 0 is canonicalized to setgt X, -1
1293 def : Pat<(brcond (setgt GRRegs:$lhs, -1), bb:$dst),
1299 def : Pat<(select (setgt GRRegs:$lhs, -1), GRRegs:$T, GRRegs:$F),
1302 def : Pat<(setgt GRRegs:$lhs, -1),
|
| /external/llvm/lib/Target/XCore/ |
| D | XCoreInstrInfo.td | 1236 def : Pat<(setgt GRRegs:$lhs, GRRegs:$rhs),
1300 // setge X, 0 is canonicalized to setgt X, -1
1301 def : Pat<(brcond (setgt GRRegs:$lhs, -1), bb:$dst),
1307 def : Pat<(select (setgt GRRegs:$lhs, -1), GRRegs:$T, GRRegs:$F),
1310 def : Pat<(setgt GRRegs:$lhs, -1),
|