1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=msp430-- < %s | FileCheck %s 3 4; Check the following conversion in TargetLowering::SimplifySetCC 5; (X & 8) != 0 --> (X & 8) >> 3 6define i16 @testSimplifySetCC_0(i16 %x) { 7; CHECK-LABEL: testSimplifySetCC_0: 8; CHECK: ; %bb.0: ; %entry 9; CHECK-NEXT: bit #32, r12 10; CHECK-NEXT: mov r2, r12 11; CHECK-NEXT: and #1, r12 12; CHECK-NEXT: ret 13entry: 14 %and = and i16 %x, 32 15 %cmp = icmp ne i16 %and, 0 16 %conv = zext i1 %cmp to i16 17 ret i16 %conv 18} 19 20; Check the following conversion in TargetLowering::SimplifySetCC 21; (X & 8) == 8 --> (X & 8) >> 3 22define i16 @testSimplifySetCC_1(i16 %x) { 23; CHECK-LABEL: testSimplifySetCC_1: 24; CHECK: ; %bb.0: ; %entry 25; CHECK-NEXT: bit #32, r12 26; CHECK-NEXT: mov r2, r12 27; CHECK-NEXT: and #1, r12 28; CHECK-NEXT: ret 29entry: 30 %and = and i16 %x, 32 31 %cmp = icmp eq i16 %and, 32 32 %conv = zext i1 %cmp to i16 33 ret i16 %conv 34} 35 36; Check the following conversion in DAGCombiner::SimplifySelectCC 37; (select_cc seteq (and x, y), 0, 0, A) -> (and (shr (shl x)) A) 38define i16 @testSimplifySelectCC_0(i16 %x, i16 %a) { 39; CHECK-LABEL: testSimplifySelectCC_0: 40; CHECK: ; %bb.0: ; %entry 41; CHECK-NEXT: mov r12, r14 42; CHECK-NEXT: clr r12 43; CHECK-NEXT: bit #2048, r14 44; CHECK-NEXT: jeq .LBB2_2 45; CHECK-NEXT: ; %bb.1: ; %entry 46; CHECK-NEXT: mov r13, r12 47; CHECK-NEXT: .LBB2_2: ; %entry 48; CHECK-NEXT: ret 49entry: 50 %and = and i16 %x, 2048 51 %cmp = icmp eq i16 %and, 0 52 %cond = select i1 %cmp, i16 0, i16 %a 53 ret i16 %cond 54} 55 56; Check the following conversion in DAGCombiner foldExtendedSignBitTest 57; sext i1 (setgt iN X, -1) --> sra (not X), (N - 1) 58define i16 @testExtendSignBit_0(i16 %x) { 59; CHECK-LABEL: testExtendSignBit_0: 60; CHECK: ; %bb.0: ; %entry 61; CHECK-NEXT: mov r12, r13 62; CHECK-NEXT: mov #-1, r12 63; CHECK-NEXT: tst r13 64; CHECK-NEXT: jge .LBB3_2 65; CHECK-NEXT: ; %bb.1: ; %entry 66; CHECK-NEXT: clr r12 67; CHECK-NEXT: .LBB3_2: ; %entry 68; CHECK-NEXT: ret 69entry: 70 %cmp = icmp sgt i16 %x, -1 71 %cond = sext i1 %cmp to i16 72 ret i16 %cond 73} 74 75; Check the following conversion in DAGCombiner foldExtendedSignBitTest 76; zext i1 (setgt iN X, -1) --> srl (not X), (N - 1) 77define i16 @testExtendSignBit_1(i16 %x) { 78; CHECK-LABEL: testExtendSignBit_1: 79; CHECK: ; %bb.0: ; %entry 80; CHECK-NEXT: mov r12, r13 81; CHECK-NEXT: mov #1, r12 82; CHECK-NEXT: tst r13 83; CHECK-NEXT: jge .LBB4_2 84; CHECK-NEXT: ; %bb.1: ; %entry 85; CHECK-NEXT: clr r12 86; CHECK-NEXT: .LBB4_2: ; %entry 87; CHECK-NEXT: ret 88entry: 89 %cmp = icmp sgt i16 %x, -1 90 %cond = zext i1 %cmp to i16 91 ret i16 %cond 92} 93 94; Check the following conversion in DAGCombiner::foldSelectCCToShiftAnd 95; select_cc setlt X, 0, A, 0 -> and (sra X, size(X)-1), A 96define i16 @testShiftAnd_0(i16 %x, i16 %a) { 97; CHECK-LABEL: testShiftAnd_0: 98; CHECK: ; %bb.0: ; %entry 99; CHECK-NEXT: tst r12 100; CHECK-NEXT: jl .LBB5_2 101; CHECK-NEXT: ; %bb.1: ; %entry 102; CHECK-NEXT: clr r13 103; CHECK-NEXT: .LBB5_2: ; %entry 104; CHECK-NEXT: mov r13, r12 105; CHECK-NEXT: ret 106entry: 107 %cmp = icmp slt i16 %x, 0 108 %cond = select i1 %cmp, i16 %a, i16 0 109 ret i16 %cond 110} 111 112; Check the following conversion in DAGCombiner::foldSelectCCToShiftAnd 113; select_cc setlt X, 0, A, 0 -> "and (srl X, C2), A" iff A is a single-bit 114define i16 @testShiftAnd_1(i16 %x) { 115; CHECK-LABEL: testShiftAnd_1: 116; CHECK: ; %bb.0: ; %entry 117; CHECK-NEXT: mov r12, r13 118; CHECK-NEXT: mov #1, r12 119; CHECK-NEXT: tst r13 120; CHECK-NEXT: jl .LBB6_2 121; CHECK-NEXT: ; %bb.1: ; %entry 122; CHECK-NEXT: clr r12 123; CHECK-NEXT: .LBB6_2: ; %entry 124; CHECK-NEXT: add r12, r12 125; CHECK-NEXT: ret 126entry: 127 %cmp = icmp slt i16 %x, 0 128 %cond = select i1 %cmp, i16 2, i16 0 129 ret i16 %cond 130} 131 132; Check the following conversion in DAGCombiner::SimplifySelectCC 133; select C, 16, 0 -> shl C, 4 134define i16 @testSimplifySelectCC_1(i16 %a, i16 %b) { 135; CHECK-LABEL: testSimplifySelectCC_1: 136; CHECK: ; %bb.0: ; %entry 137; CHECK-NEXT: mov r12, r14 138; CHECK-NEXT: mov #32, r12 139; CHECK-NEXT: cmp r14, r13 140; CHECK-NEXT: jl .LBB7_2 141; CHECK-NEXT: ; %bb.1: ; %entry 142; CHECK-NEXT: clr r12 143; CHECK-NEXT: .LBB7_2: ; %entry 144; CHECK-NEXT: ret 145entry: 146 %cmp = icmp sgt i16 %a, %b 147 %cond = select i1 %cmp, i16 32, i16 0 148 ret i16 %cond 149} 150 151; Check the following conversion in TargetLowering::SimplifySetCC 152; (X & 8) != 0 --> (X & 8) >> 3 153define i16 @testSimplifySetCC_0_sh8(i16 %x) { 154; CHECK-LABEL: testSimplifySetCC_0_sh8: 155; CHECK: ; %bb.0: ; %entry 156; CHECK-NEXT: and #256, r12 157; CHECK-NEXT: swpb r12 158; CHECK-NEXT: ret 159entry: 160 %and = and i16 %x, 256 161 %cmp = icmp ne i16 %and, 0 162 %conv = zext i1 %cmp to i16 163 ret i16 %conv 164} 165 166; Check the following conversion in TargetLowering::SimplifySetCC 167; (X & 8) == 8 --> (X & 8) >> 3 168define i16 @testSimplifySetCC_1_sh8(i16 %x) { 169; CHECK-LABEL: testSimplifySetCC_1_sh8: 170; CHECK: ; %bb.0: ; %entry 171; CHECK-NEXT: and #256, r12 172; CHECK-NEXT: swpb r12 173; CHECK-NEXT: ret 174entry: 175 %and = and i16 %x, 256 176 %cmp = icmp eq i16 %and, 256 177 %conv = zext i1 %cmp to i16 178 ret i16 %conv 179} 180 181; Check the following conversion in DAGCombiner::foldSelectCCToShiftAnd 182; select_cc setlt X, 0, A, 0 -> "and (srl X, C2), A" iff A is a single-bit 183define i16 @testShiftAnd_1_sh8(i16 %x) { 184; CHECK-LABEL: testShiftAnd_1_sh8: 185; CHECK: ; %bb.0: ; %entry 186; CHECK-NEXT: swpb r12 187; CHECK-NEXT: and #128, r12 188; CHECK-NEXT: ret 189entry: 190 %cmp = icmp slt i16 %x, 0 191 %cond = select i1 %cmp, i16 128, i16 0 192 ret i16 %cond 193} 194 195; Check the following conversion in DAGCombiner::foldSelectCCToShiftAnd 196; select_cc setlt X, 0, A, 0 -> "and (srl X, C2), A" iff A is a single-bit 197define i16 @testShiftAnd_1_sh9(i16 %x) { 198; CHECK-LABEL: testShiftAnd_1_sh9: 199; CHECK: ; %bb.0: ; %entry 200; CHECK-NEXT: swpb r12 201; CHECK-NEXT: mov.b r12, r12 202; CHECK-NEXT: clrc 203; CHECK-NEXT: rrc r12 204; CHECK-NEXT: and #64, r12 205; CHECK-NEXT: ret 206entry: 207 %cmp = icmp slt i16 %x, 0 208 %cond = select i1 %cmp, i16 64, i16 0 209 ret i16 %cond 210} 211