Home
last modified time | relevance | path

Searched refs:setlt (Results 1 – 25 of 67) sorted by relevance

123

/external/llvm-project/llvm/test/CodeGen/PowerPC/
Dppc64-P9-setb.ll9 ; select_cc lhs, rhs, -1, (zext (setcc lhs, rhs, setne)), setlt
61 ; select_cc lhs, rhs, -1, (zext (setcc rhs, lhs, setne)), setlt
113 ; select_cc lhs, rhs, -1, (zext (setcc lhs, rhs, setgt)), setlt
173 ; select_cc lhs, rhs, -1, (zext (setcc rhs, lhs, setlt)), setlt
203 ; select_cc lhs, rhs, -1, (zext (setcc lhs, rhs, setlt)), setgt
259 ; select_cc lhs, rhs, 1, (sext (setcc rhs, lhs, setne)), setlt
311 ; select_cc lhs, rhs, 1, (sext (setcc lhs, rhs, setne)), setlt
337 ; select_cc lhs, rhs, 1, (sext (setcc lhs, rhs, setlt)), setgt
369 ; select_cc lhs, rhs, 1, (sext (setcc rhs, lhs, setlt)), setlt
433 ; select_cc lhs, rhs, 1, (sext (setcc lhs, rhs, setgt)), setlt
[all …]
Dppc-vaarg-agg.ll44 ; with an error like: Cannot select: ch = setlt [ID=6]
/external/llvm-project/llvm/test/CodeGen/MSP430/
Dshift-amount-threshold.ll95 ; select_cc setlt X, 0, A, 0 -> and (sra X, size(X)-1), A
113 ; select_cc setlt X, 0, A, 0 -> "and (srl X, C2), A" iff A is a single-bit
182 ; select_cc setlt X, 0, A, 0 -> "and (srl X, C2), A" iff A is a single-bit
196 ; select_cc setlt X, 0, A, 0 -> "and (srl X, C2), A" iff A is a single-bit
/external/llvm-project/clang/test/CodeGen/
DBasicInstrs.c19 _Bool setlt(int X, int Y) { in setlt() function
/external/clang/test/CodeGen/
DBasicInstrs.c19 _Bool setlt(int X, int Y) { in setlt() function
/external/llvm-project/llvm/test/Transforms/InstCombine/
Dsetcc-strength-reduce.ll2 ; working. Basically this boils down to converting setlt,gt,le,ge instructions
/external/llvm/test/Transforms/LoopStrengthReduce/
Ddont-hoist-simple-loop-constants.ll4 ; The setlt wants to use a value that is incremented one more than the dominant
/external/llvm/test/Transforms/InstCombine/
Dsetcc-strength-reduce.ll2 ; working. Basically this boils down to converting setlt,gt,le,ge instructions
/external/llvm-project/llvm/test/Transforms/LoopStrengthReduce/
Ddont-hoist-simple-loop-constants.ll4 ; The setlt wants to use a value that is incremented one more than the dominant
/external/llvm/test/CodeGen/PowerPC/
Dppc-vaarg-agg.ll44 ; with an error like: Cannot select: ch = setlt [ID=6]
/external/llvm/lib/Target/WebAssembly/
DWebAssemblyInstrFloat.td67 def : Pat<(setlt f32:$lhs, f32:$rhs), (LT_F32 f32:$lhs, f32:$rhs)>;
73 def : Pat<(setlt f64:$lhs, f64:$rhs), (LT_F64 f64:$lhs, f64:$rhs)>;
/external/llvm/lib/Target/Hexagon/
DHexagonInstrInfoVector.td306 def: InvertCmp_pat<A4_vcmpbgt, setlt, V8I8, i1>;
307 def: InvertCmp_pat<A4_vcmpbgt, setlt, V8I8, v8i1>;
308 def: InvertCmp_pat<A2_vcmphgt, setlt, V4I16, i1>;
309 def: InvertCmp_pat<A2_vcmphgt, setlt, V4I16, v4i1>;
310 def: InvertCmp_pat<A2_vcmpwgt, setlt, V2I32, i1>;
311 def: InvertCmp_pat<A2_vcmpwgt, setlt, V2I32, v2i1>;
DHexagonSelectCCInfo.td111 // setlt-64 -> setgt-64.
DHexagonInstrInfoV5.td494 def: Pat<(i1 (setlt F32:$src1, F32:$src2)),
496 def: Pat<(i1 (setlt F32:$src1, fpimm:$src2)),
498 def: Pat<(i1 (setlt F64:$src1, F64:$src2)),
500 def: Pat<(i1 (setlt F64:$src1, fpimm:$src2)),
DHexagonInstrInfoV3.td148 defm: MinMax_pats_p<setlt, A2_minp, A2_maxp>;
/external/llvm-project/llvm/test/CodeGen/Mips/msa/
Dcc_without_nan.ll5 ; setlt, seteq, setle, setne nodes.
/external/llvm-project/llvm/test/CodeGen/X86/
Dfmf-propagation.ll32 … t13: i8 = setcc nnan ninf nsz arcp contract afn reassoc t2, ConstantFP:f32<0.000000e+00>, setlt:ch
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/WebAssembly/
DWebAssemblyInstrFloat.td91 def : Pat<(setlt f32:$lhs, f32:$rhs), (LT_F32 f32:$lhs, f32:$rhs)>;
97 def : Pat<(setlt f64:$lhs, f64:$rhs), (LT_F64 f64:$lhs, f64:$rhs)>;
/external/llvm-project/llvm/lib/Target/WebAssembly/
DWebAssemblyInstrFloat.td91 def : Pat<(setlt f32:$lhs, f32:$rhs), (LT_F32 f32:$lhs, f32:$rhs)>;
97 def : Pat<(setlt f64:$lhs, f64:$rhs), (LT_F64 f64:$lhs, f64:$rhs)>;
/external/llvm-project/llvm/lib/Target/Mips/
DMips16InstrInfo.td1442 // bcond-setgt (do we need to have this pair of setlt, setgt??)
1465 // bcond-setlt
1468 <(brcond (i32 (setlt CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1473 <(brcond (i32 (setlt CPU16Regs:$rx, immSExt16:$imm)), bb:$imm16),
1626 (select (i32 (setlt CPU16Regs:$a, immSExt16:$b)),
1762 // x > (k - 1) and then reverses the operands to use setlt. So this pattern
1796 // setlt
1798 def: SetCC_R16<setlt, SltCCRxRy16>;
1800 def: SetCC_I16<setlt, immSExt16, SltiCCRxImmX16>;
/external/llvm/lib/Target/Mips/
DMips16InstrInfo.td1447 // bcond-setgt (do we need to have this pair of setlt, setgt??)
1470 // bcond-setlt
1473 <(brcond (i32 (setlt CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1478 <(brcond (i32 (setlt CPU16Regs:$rx, immSExt16:$imm)), bb:$imm16),
1631 (select (i32 (setlt CPU16Regs:$a, immSExt16:$b)),
1767 // x > (k - 1) and then reverses the operands to use setlt. So this pattern
1801 // setlt
1803 def: SetCC_R16<setlt, SltCCRxRy16>;
1805 def: SetCC_I16<setlt, immSExt16, SltiCCRxImmX16>;
DMips64InstrInfo.td104 def SLTi64 : SetCC_I<"slti", setlt, simm16_64, immSExt16, GPR64Opnd>,
130 def SLT64 : SetCC_R<"slt", setlt, GPR64Opnd>, ADD_FM<0, 0x2a>;
241 def BLTZ64 : CBranchZero<"bltz", brtarget, setlt, GPR64Opnd>, BGEZ_FM<1, 0>;
543 def : MipsPat<(brcond (i32 (setlt i64:$lhs, 1)), bb:$dst),
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/
DMips16InstrInfo.td1442 // bcond-setgt (do we need to have this pair of setlt, setgt??)
1465 // bcond-setlt
1468 <(brcond (i32 (setlt CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1473 <(brcond (i32 (setlt CPU16Regs:$rx, immSExt16:$imm)), bb:$imm16),
1626 (select (i32 (setlt CPU16Regs:$a, immSExt16:$b)),
1762 // x > (k - 1) and then reverses the operands to use setlt. So this pattern
1796 // setlt
1798 def: SetCC_R16<setlt, SltCCRxRy16>;
1800 def: SetCC_I16<setlt, immSExt16, SltiCCRxImmX16>;
/external/clang/www/demo/
Dindex.cgi99 …$input =~ s@\b(add|sub|mul|div|rem|and|or|xor|setne|seteq|setlt|setgt|setle|setge|phi|tail|call|ca…
/external/llvm-project/clang/www/demo/
Dindex.cgi99 …$input =~ s@\b(add|sub|mul|div|rem|and|or|xor|setne|seteq|setlt|setgt|setle|setge|phi|tail|call|ca…

123