| /external/libopus/m4/ |
| D | as-gcc-inline-assembly.m4 | 60 AC_COMPILE_IFELSE([AC_LANG_PROGRAM([],[__asm__("shadd8 r3,r3,r3")])],
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| /external/llvm-project/llvm/test/CodeGen/ARM/ |
| D | acle-intrinsics.ll | 100 define i32 @shadd8(i32 %a, i32 %b) nounwind {
101 ; CHECK-LABEL: shadd8
102 ; CHECK: shadd8 r0, r0, r1
103 %tmp = call i32 @llvm.arm.shadd8(i32 %a, i32 %b)
435 declare i32 @llvm.arm.shadd8(i32, i32) nounwind
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| /external/vixl/test/aarch32/ |
| D | test-assembler-cond-rd-rn-rm-t32.cc | 61 M(shadd8) \
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| D | test-assembler-cond-rd-rn-rm-a32.cc | 62 M(shadd8) \
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| /external/libopus/ |
| D | meson.build | 236 if cc.compiles(asm_tmpl.format('shadd8 r3,r3,r3'),
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| /external/llvm-project/llvm/test/tools/llvm-mca/ARM/ |
| D | m7-int.s | 254 shadd8 r0, r1, r2 label
685 # CHECK-NEXT: 1 1 1.00 shadd8 r0, r1, r2
1125 …50 - - - - 1.00 - - - - - - shadd8 r0, r1, r2
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| D | m4-int.s | 262 shadd8 r0, r1, r2 label
708 # CHECK-NEXT: 1 1 1.00 shadd8 r0, r1, r2
1146 # CHECK-NEXT: 1.00 shadd8 r0, r1, r2
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| D | cortex-a57-basic-instructions.s | 560 shadd8 r4, r8, r2
1430 # CHECK-NEXT: 1 2 1.00 shadd8 r4, r8, r2
2307 # CHECK-NEXT: - - - - 1.00 - - - shadd8 r4, r8, r2
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| /external/capstone/suite/MC/ARM/ |
| D | basic-arm-instructions.s.cs | 633 0x92,0x4f,0x38,0xe6 = shadd8 r4, r8, r2
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| /external/vixl/src/aarch32/ |
| D | assembler-aarch32.h | 3034 void shadd8(Condition cond, Register rd, Register rn, Register rm);
3035 void shadd8(Register rd, Register rn, Register rm) { shadd8(al, rd, rn, rm); } in shadd8() function
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| D | disasm-aarch32.h | 1075 void shadd8(Condition cond, Register rd, Register rn, Register rm);
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| D | disasm-aarch32.cc | 2495 void Disassembler::shadd8(Condition cond, in shadd8() function in vixl::aarch32::Disassembler
21175 shadd8(CurrentCond(), in DecodeT32()
62611 shadd8(condition, Register(rd), Register(rn), Register(rm)); in DecodeA32()
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| /external/llvm-project/llvm/test/MC/ARM/ |
| D | basic-arm-instructions.s | 2359 shadd8 r4, r8, r2
2364 @ CHECK: shadd8 r4, r8, r2 @ encoding: [0x92,0x4f,0x38,0xe6]
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| /external/llvm/test/MC/ARM/ |
| D | basic-arm-instructions.s | 2329 shadd8 r4, r8, r2
2334 @ CHECK: shadd8 r4, r8, r2 @ encoding: [0x92,0x4f,0x38,0xe6]
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| /external/llvm-project/llvm/test/MC/Disassembler/ARM/ |
| D | basic-arm-instructions.txt | 1537 # CHECK: shadd8 r4, r8, r2
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| /external/llvm/test/MC/Disassembler/ARM/ |
| D | basic-arm-instructions.txt | 1537 # CHECK: shadd8 r4, r8, r2
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| /external/capstone/arch/AArch64/ |
| D | ARMMappingInsnOp.inc | 721 { /* ARM_SHADD8, ARM_INS_SHADD8: shadd8${p} $rd, $rn, $rm */
5947 { /* ARM_t2SHADD8, ARM_INS_SHADD8: shadd8${p} $rd, $rn, $rm */
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| /external/capstone/arch/ARM/ |
| D | ARMMappingInsnOp.inc | 721 { /* ARM_SHADD8, ARM_INS_SHADD8: shadd8${p} $rd, $rn, $rm */
5947 { /* ARM_t2SHADD8, ARM_INS_SHADD8: shadd8${p} $rd, $rn, $rm */
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| /external/llvm/lib/Target/ARM/ |
| D | ARMInstrThumb2.td | 2177 def t2SHADD8 : T2I_pam<0b000, 0b0010, "shadd8">;
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| D | ARMInstrInfo.td | 3606 def SHADD8 : AAI<0b01100011, 0b11111001, "shadd8">;
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMInstrThumb2.td | 2480 def t2SHADD8 : T2I_pam_intrinsics<0b000, 0b0010, "shadd8", int_arm_shadd8>;
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| D | ARMInstrInfo.td | 3831 def SHADD8 : AAIIntrinsic<0b01100011, 0b11111001, "shadd8", int_arm_shadd8>;
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| /external/llvm-project/llvm/lib/Target/ARM/ |
| D | ARMInstrThumb2.td | 2529 def t2SHADD8 : T2I_pam_intrinsics<0b000, 0b0010, "shadd8", int_arm_shadd8>;
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| D | ARMInstrInfo.td | 3964 def SHADD8 : AAIIntrinsic<0b01100011, 0b11111001, "shadd8", int_arm_shadd8>;
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| /external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/ARM/ |
| D | ARMGenAsmMatcher.inc | 9900 "shadd16\006shadd8\005shasx\005shsax\007shsub16\006shsub8\003smc\006smla"
11093 …{ 1067 /* shadd8 */, ARM::t2SHADD8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_H…
11094 …{ 1067 /* shadd8 */, ARM::SHADD8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK…
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