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Searched refs:shiftval (Results 1 – 6 of 6) sorted by relevance

/external/llvm/test/CodeGen/X86/
Dpr15296.ll3 define <8 x i32> @shiftInput___vyuunu(<8 x i32> %input, i32 %shiftval, <8 x i32> %__mask) nounwind {
5 %smear.0 = insertelement <8 x i32> undef, i32 %shiftval, i32 0
6 %smear.1 = insertelement <8 x i32> %smear.0, i32 %shiftval, i32 1
7 %smear.2 = insertelement <8 x i32> %smear.1, i32 %shiftval, i32 2
8 %smear.3 = insertelement <8 x i32> %smear.2, i32 %shiftval, i32 3
9 %smear.4 = insertelement <8 x i32> %smear.3, i32 %shiftval, i32 4
10 %smear.5 = insertelement <8 x i32> %smear.4, i32 %shiftval, i32 5
11 %smear.6 = insertelement <8 x i32> %smear.5, i32 %shiftval, i32 6
12 %smear.7 = insertelement <8 x i32> %smear.6, i32 %shiftval, i32 7
22 define <8 x i32> @shiftInput___canonical(<8 x i32> %input, i32 %shiftval, <8 x i32> %__mask) nounwi…
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/external/llvm-project/llvm/test/CodeGen/X86/
Dpr15296.ll3 define <8 x i32> @shiftInput___vyuunu(<8 x i32> %input, i32 %shiftval, <8 x i32> %__mask) nounwind {
5 %smear.0 = insertelement <8 x i32> undef, i32 %shiftval, i32 0
6 %smear.1 = insertelement <8 x i32> %smear.0, i32 %shiftval, i32 1
7 %smear.2 = insertelement <8 x i32> %smear.1, i32 %shiftval, i32 2
8 %smear.3 = insertelement <8 x i32> %smear.2, i32 %shiftval, i32 3
9 %smear.4 = insertelement <8 x i32> %smear.3, i32 %shiftval, i32 4
10 %smear.5 = insertelement <8 x i32> %smear.4, i32 %shiftval, i32 5
11 %smear.6 = insertelement <8 x i32> %smear.5, i32 %shiftval, i32 6
12 %smear.7 = insertelement <8 x i32> %smear.6, i32 %shiftval, i32 7
22 define <8 x i32> @shiftInput___canonical(<8 x i32> %input, i32 %shiftval, <8 x i32> %__mask) nounwi…
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/external/llvm/test/Transforms/InstSimplify/
Dshr-nop.ll376 define i32 @exact_lshr_lowbit(i32 %shiftval) {
380 %shr = lshr exact i32 7, %shiftval
384 define i32 @exact_ashr_lowbit(i32 %shiftval) {
388 %shr = ashr exact i32 7, %shiftval
392 define i32 @ashr_zero(i32 %shiftval) {
396 %shr = ashr i32 0, %shiftval
400 define i257 @ashr_minus1(i257 %shiftval) {
404 %shr = ashr i257 -1, %shiftval
408 define <2 x i4097> @ashr_zero_vec(<2 x i4097> %shiftval) {
412 %shr = ashr <2 x i4097> zeroinitializer, %shiftval
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/external/llvm-project/llvm/test/Transforms/InstSimplify/
Dshr-nop.ll376 define i32 @exact_lshr_lowbit(i32 %shiftval) {
380 %shr = lshr exact i32 7, %shiftval
384 define i32 @exact_ashr_lowbit(i32 %shiftval) {
388 %shr = ashr exact i32 7, %shiftval
392 define i32 @ashr_zero(i32 %shiftval) {
396 %shr = ashr i32 0, %shiftval
400 define i257 @ashr_minus1(i257 %shiftval) {
404 %shr = ashr i257 -1, %shiftval
408 define <2 x i4097> @ashr_zero_vec(<2 x i4097> %shiftval) {
412 %shr = ashr <2 x i4097> zeroinitializer, %shiftval
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/external/webp/src/dsp/
Drescaler_msa.c271 const v4u32 shiftval = (v4u32)__msa_fill_w(WEBP_RESCALER_RFIX);
278 CALC_MULT_FIX1_16(src0, src1, src2, src3, y_scale, shiftval,
283 CALC_MULT_FIX_16(src0, src1, src2, src3, fxyscale, shiftval, out);
297 CALC_MULT_FIX1_4(src0, y_scale, shiftval, frac0);
298 CALC_MULT_FIX1_4(src1, y_scale, shiftval, frac1);
299 CALC_MULT_FIX1_4(src2, y_scale, shiftval, frac2);
302 CALC_MULT_FIX_4(src0, fxyscale, shiftval, val0_m);
303 CALC_MULT_FIX_4(src1, fxyscale, shiftval, val1_m);
304 CALC_MULT_FIX_4(src2, fxyscale, shiftval, val2_m);
315 CALC_MULT_FIX1_4(src0, y_scale, shiftval, frac0);
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/external/aac/libFDK/src/
DFDK_lpc.cpp358 INT shiftval, in CLpc_ParcorToLpc() local
384 shiftval = fMin(fNorm(maxVal), par2LpcShiftVal); in CLpc_ParcorToLpc()
387 LpcCoeff[i] = FX_DBL2FX_LPC_TNS(workBuffer[i] << shiftval); in CLpc_ParcorToLpc()
390 return (par2LpcShiftVal - shiftval); in CLpc_ParcorToLpc()
396 INT shiftval, in CLpc_ParcorToLpc() local
422 shiftval = fMin(fNorm(maxVal), par2LpcShiftVal); in CLpc_ParcorToLpc()
425 LpcCoeff[i] = FX_DBL2FX_LPC(workBuffer[i] << shiftval); in CLpc_ParcorToLpc()
428 return (par2LpcShiftVal - shiftval); in CLpc_ParcorToLpc()