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/external/llvm-project/llvm/test/MC/VE/
DSLD.s6 # CHECK-INST: sld %s11, %s11, %s11
8 sld %s11, %s11, %s11 label
10 # CHECK-INST: sld %s11, %s11, 63
12 sld %s11, %s11, 63 label
14 # CHECK-INST: sld %s11, %s11, 127
16 sld %s11, %s11, 127 label
18 # CHECK-INST: sld %s11, %s11, 64
20 sld %s11, %s11, 64 label
22 # CHECK-INST: sld %s11, (32)1, 64
24 sld %s11, (32)1, 64 label
[all …]
/external/llvm-project/llvm/test/CodeGen/PowerPC/
Dshift128.ll10 ; CHECK-DAG: sld [[R3:[0-9]+]], 4, [[R0]]
24 ; CHECK-DAG: sld [[R3:[0-9]+]], 4, [[R0]]
38 ; CHECK-DAG: sld [[R2:[0-9]+]], 4, 5
40 ; CHECK-DAG: sld [[R4:[0-9]+]], 3, [[R1]]
43 ; CHECK-DAG: sld 3, 3, 5
56 ; P9-NOT: {{\b}}sld
75 ; P9-NOT: {{\b}}sld
Duse-cr-result-of-dom-icmp-st.ll20 ; CHECK-NEXT: sld r5, r3, r4
49 ; CHECK-NEXT: sld r5, r3, r4
78 ; CHECK-NEXT: sld. r5, r3, r4
106 ; CHECK-NEXT: sld r5, r3, r4
135 ; CHECK-NEXT: sld r5, r3, r4
Dfunnel-shift.ll103 ; CHECK64-NEXT: sld 3, 3, 5
242 ; CHECK64-NEXT: sld 3, 3, 5
409 ; CHECK64-NEXT: sld 3, 3, 6
557 ; CHECK64-NEXT: sld 3, 3, 6
Doptcmp.ll203 ; CHECK-NEXT: sld 4, 3, 4
212 ; CHECK-NO-ISEL-NEXT: sld 4, 3, 4
/external/pdfium/fxbarcode/pdf417/
DBC_PDF417ErrorCorrection.cpp144 size_t sld = dataCodewords.GetLength(); in GenerateErrorCorrection() local
145 for (size_t i = 0; i < sld; i++) { in GenerateErrorCorrection()
/external/capstone/suite/MC/PowerPC/
Dppc64-encoding.s.cs189 0x7c,0x62,0x20,0x36 = sld 2, 3, 4
190 0x7c,0x62,0x20,0x37 = sld. 2, 3, 4
/external/llvm/test/CodeGen/PowerPC/
Dshift128.ll1 ; RUN: llc < %s -march=ppc64 | grep sld | count 5
Doptcmp.ll108 ; CHECK: sld. 4, 3, 4
/external/llvm/test/CodeGen/Mips/msa/
Dbasic_operations.ll748 ; ALL-DAG: sld.b [[R1]], [[R1]]{{\[}}[[IDX]]]
753 ; ALL-DAG: sld.b [[R1]], [[R1]]{{\[}}[[NIDX]]]
781 ; ALL-DAG: sld.b [[R1]], [[R1]]{{\[}}[[BIDX]]]
786 ; ALL-DAG: sld.b [[R1]], [[R1]]{{\[}}[[NIDX]]]
811 ; ALL-DAG: sld.b [[R1]], [[R1]]{{\[}}[[BIDX]]]
816 ; ALL-DAG: sld.b [[R1]], [[R1]]{{\[}}[[NIDX]]]
846 ; MIPS32-DAG: sld.b [[R1]], [[R1]]{{\[}}[[BIDX]]]
849 ; MIPS32-DAG: sld.b [[R1]], [[R1]]{{\[}}[[NIDX]]]
852 ; MIPS32-DAG: sld.b [[R1]], [[R1]]{{\[}}[[BIDX]]]
855 ; MIPS32-DAG: sld.b [[R1]], [[R1]]{{\[}}[[NIDX]]]
[all …]
Dbasic_operations_float.ll314 ; ALL-DAG: sld.b [[R1]], [[R1]]{{\[}}[[BIDX]]]
317 ; ALL-DAG: sld.b [[R1]], [[R1]]{{\[}}[[NIDX]]]
343 ; ALL-DAG: sld.b [[R1]], [[R1]]{{\[}}[[BIDX]]]
346 ; ALL-DAG: sld.b [[R1]], [[R1]]{{\[}}[[NIDX]]]
D3r-s.ll17 %3 = tail call <16 x i8> @llvm.mips.sld.b(<16 x i8> %0, <16 x i8> %1, i32 %2)
22 declare <16 x i8> @llvm.mips.sld.b(<16 x i8>, <16 x i8>, i32) nounwind
31 ; CHECK-DAG: sld.b [[WD]], [[WS]]{{\[}}[[RT]]{{\]}}
45 %3 = tail call <8 x i16> @llvm.mips.sld.h(<8 x i16> %0, <8 x i16> %1, i32 %2)
50 declare <8 x i16> @llvm.mips.sld.h(<8 x i16>, <8 x i16>, i32) nounwind
59 ; CHECK-DAG: sld.h [[WD]], [[WS]]{{\[}}[[RT]]{{\]}}
73 %3 = tail call <4 x i32> @llvm.mips.sld.w(<4 x i32> %0, <4 x i32> %1, i32 %2)
78 declare <4 x i32> @llvm.mips.sld.w(<4 x i32>, <4 x i32>, i32) nounwind
87 ; CHECK-DAG: sld.w [[WD]], [[WS]]{{\[}}[[RT]]{{\]}}
101 %3 = tail call <2 x i64> @llvm.mips.sld.d(<2 x i64> %0, <2 x i64> %1, i32 %2)
[all …]
/external/llvm-project/llvm/test/CodeGen/Mips/msa/
Dbasic_operations.ll781 ; ALL-DAG: sld.b [[R1]], [[R1]]{{\[}}[[IDX]]]
786 ; ALL-DAG: sld.b [[R1]], [[R1]]{{\[}}[[NIDX]]]
814 ; ALL-DAG: sld.b [[R1]], [[R1]]{{\[}}[[BIDX]]]
819 ; ALL-DAG: sld.b [[R1]], [[R1]]{{\[}}[[NIDX]]]
844 ; ALL-DAG: sld.b [[R1]], [[R1]]{{\[}}[[BIDX]]]
849 ; ALL-DAG: sld.b [[R1]], [[R1]]{{\[}}[[NIDX]]]
879 ; MIPS32-DAG: sld.b [[R1]], [[R1]]{{\[}}[[BIDX]]]
882 ; MIPS32-DAG: sld.b [[R1]], [[R1]]{{\[}}[[NIDX]]]
885 ; MIPS32-DAG: sld.b [[R1]], [[R1]]{{\[}}[[BIDX]]]
888 ; MIPS32-DAG: sld.b [[R1]], [[R1]]{{\[}}[[NIDX]]]
[all …]
Dbasic_operations_float.ll320 ; ALL-DAG: sld.b [[R1]], [[R1]]{{\[}}[[BIDX]]]
323 ; ALL-DAG: sld.b [[R1]], [[R1]]{{\[}}[[NIDX]]]
349 ; ALL-DAG: sld.b [[R1]], [[R1]]{{\[}}[[BIDX]]]
352 ; ALL-DAG: sld.b [[R1]], [[R1]]{{\[}}[[NIDX]]]
D3r-s.ll17 %3 = tail call <16 x i8> @llvm.mips.sld.b(<16 x i8> %0, <16 x i8> %1, i32 %2)
22 declare <16 x i8> @llvm.mips.sld.b(<16 x i8>, <16 x i8>, i32) nounwind
31 ; CHECK-DAG: sld.b [[WD]], [[WS]]{{\[}}[[RT]]{{\]}}
45 %3 = tail call <8 x i16> @llvm.mips.sld.h(<8 x i16> %0, <8 x i16> %1, i32 %2)
50 declare <8 x i16> @llvm.mips.sld.h(<8 x i16>, <8 x i16>, i32) nounwind
59 ; CHECK-DAG: sld.h [[WD]], [[WS]]{{\[}}[[RT]]{{\]}}
73 %3 = tail call <4 x i32> @llvm.mips.sld.w(<4 x i32> %0, <4 x i32> %1, i32 %2)
78 declare <4 x i32> @llvm.mips.sld.w(<4 x i32>, <4 x i32>, i32) nounwind
87 ; CHECK-DAG: sld.w [[WD]], [[WS]]{{\[}}[[RT]]{{\]}}
101 %3 = tail call <2 x i64> @llvm.mips.sld.d(<2 x i64> %0, <2 x i64> %1, i32 %2)
[all …]
/external/capstone/suite/MC/Mips/
Dtest_3r.s.cs192 0x78,0x0c,0xb9,0x54 = sld.b $w5, $w23[$t4]
193 0x78,0x23,0xb8,0x54 = sld.h $w1, $w23[$v1]
194 0x78,0x49,0x45,0x14 = sld.w $w20, $w8[$t1]
195 0x78,0x7e,0xb9,0xd4 = sld.d $w7, $w23[$fp]
/external/llvm/test/MC/Mips/msa/
Dtest_3r.s193 # CHECK: sld.b $w5, $w23[$12] # encoding: [0x78,0x0c,0xb9,0x54]
194 # CHECK: sld.h $w1, $w23[$3] # encoding: [0x78,0x23,0xb8,0x54]
195 # CHECK: sld.w $w20, $w8[$9] # encoding: [0x78,0x49,0x45,0x14]
196 # CHECK: sld.d $w7, $w23[$fp] # encoding: [0x78,0x7e,0xb9,0xd4]
436 sld.b $w5, $w23[$12]
437 sld.h $w1, $w23[$3]
438 sld.w $w20, $w8[$9]
439 sld.d $w7, $w23[$30]
/external/llvm-project/llvm/test/MC/Mips/msa/
Dtest_3r.s193 # CHECK: sld.b $w5, $w23[$12] # encoding: [0x78,0x0c,0xb9,0x54]
194 # CHECK: sld.h $w1, $w23[$3] # encoding: [0x78,0x23,0xb8,0x54]
195 # CHECK: sld.w $w20, $w8[$9] # encoding: [0x78,0x49,0x45,0x14]
196 # CHECK: sld.d $w7, $w23[$fp] # encoding: [0x78,0x7e,0xb9,0xd4]
436 sld.b $w5, $w23[$12]
437 sld.h $w1, $w23[$3]
438 sld.w $w20, $w8[$9]
439 sld.d $w7, $w23[$30]
/external/llvm/test/MC/PowerPC/
Dppc64-encoding.s810 # CHECK-BE: sld 2, 3, 4 # encoding: [0x7c,0x62,0x20,0x36]
811 # CHECK-LE: sld 2, 3, 4 # encoding: [0x36,0x20,0x62,0x7c]
812 sld 2, 3, 4
813 # CHECK-BE: sld. 2, 3, 4 # encoding: [0x7c,0x62,0x20,0x37]
814 # CHECK-LE: sld. 2, 3, 4 # encoding: [0x37,0x20,0x62,0x7c]
815 sld. 2, 3, 4
/external/llvm-project/llvm/test/MC/PowerPC/
Dppc64-encoding.s982 # CHECK-BE: sld 2, 3, 4 # encoding: [0x7c,0x62,0x20,0x36]
983 # CHECK-LE: sld 2, 3, 4 # encoding: [0x36,0x20,0x62,0x7c]
984 sld 2, 3, 4
985 # CHECK-BE: sld. 2, 3, 4 # encoding: [0x7c,0x62,0x20,0x37]
986 # CHECK-LE: sld. 2, 3, 4 # encoding: [0x37,0x20,0x62,0x7c]
987 sld. 2, 3, 4
/external/llvm/test/MC/Disassembler/Mips/msa/
Dtest_3r.txt193 0x78 0x0c 0xb9 0x54 # CHECK: sld.b $w5, $w23[$12]
194 0x78 0x23 0xb8 0x54 # CHECK: sld.h $w1, $w23[$3]
195 0x78 0x49 0x45 0x14 # CHECK: sld.w $w20, $w8[$9]
196 0x78 0x7e 0xb9 0xd4 # CHECK: sld.d $w7, $w23[$fp]
/external/llvm-project/llvm/test/MC/Disassembler/Mips/msa/
Dtest_3r.txt193 0x78 0x0c 0xb9 0x54 # CHECK: sld.b $w5, $w23[$12]
194 0x78 0x23 0xb8 0x54 # CHECK: sld.h $w1, $w23[$3]
195 0x78 0x49 0x45 0x14 # CHECK: sld.w $w20, $w8[$9]
196 0x78 0x7e 0xb9 0xd4 # CHECK: sld.d $w7, $w23[$fp]
/external/icu/icu4c/source/data/locales/
Dkab.txt155 "sld. T.Ɛ",
/external/llvm/test/MC/Disassembler/PowerPC/
Dppc64le-encoding.txt619 # CHECK: sld 2, 3, 4
622 # CHECK: sld. 2, 3, 4
Dppc64-encoding.txt640 # CHECK: sld 2, 3, 4
643 # CHECK: sld. 2, 3, 4

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