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Searched refs:sqincp (Results 1 – 12 of 12) sorted by relevance

/external/llvm-project/llvm/test/MC/AArch64/SVE/
Dsqincp.s10 sqincp x0, p0.b label
16 sqincp x0, p0.h label
22 sqincp x0, p0.s label
28 sqincp x0, p0.d label
34 sqincp xzr, p15.b, wzr label
40 sqincp xzr, p15.h, wzr label
46 sqincp xzr, p15.s, wzr label
52 sqincp xzr, p15.d, wzr label
58 sqincp z0.h, p0 label
64 sqincp z0.h, p0.h label
[all …]
Dsqincp-diagnostics.s50 sqincp z0.d, p0.b label
55 sqincp z0.d, p0.q label
65 sqincp z0.d, p0 label
/external/llvm-project/llvm/test/CodeGen/AArch64/
Dsve-intrinsics-sqinc.ll59 ; CHECK: sqincp z0.h, p0
61 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.sqincp.nxv8i16(<vscale x 8 x i16> %a,
68 ; CHECK: sqincp z0.s, p0
70 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.sqincp.nxv4i32(<vscale x 4 x i32> %a,
77 ; CHECK: sqincp z0.d, p0
79 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.sqincp.nxv2i64(<vscale x 2 x i64> %a,
210 ; CHECK: sqincp x0, p0.b, w0
212 %out = call i32 @llvm.aarch64.sve.sqincp.n32.nxv16i1(i32 %a, <vscale x 16 x i1> %b)
218 ; CHECK: sqincp x0, p0.b, w0
220 %out = call i32 @llvm.aarch64.sve.sqincp.n32.nxv16i1(i32 %a, <vscale x 16 x i1> %b)
[all …]
/external/vixl/test/aarch64/
Dtest-disasm-sve-aarch64.cc1951 COMPARE_PREFIX(sqincp(x26, p5.VnB(), w26), "sqincp x26, p5.b, w26"); in TEST()
1952 COMPARE_PREFIX(sqincp(x26, p5.VnH(), w26), "sqincp x26, p5.h, w26"); in TEST()
1953 COMPARE_PREFIX(sqincp(x26, p5.VnS(), w26), "sqincp x26, p5.s, w26"); in TEST()
1954 COMPARE_PREFIX(sqincp(x26, p5.VnD(), w26), "sqincp x26, p5.d, w26"); in TEST()
1955 COMPARE_PREFIX(sqincp(x5, p15.VnB()), "sqincp x5, p15.b"); in TEST()
1956 COMPARE_PREFIX(sqincp(x5, p15.VnH()), "sqincp x5, p15.h"); in TEST()
1957 COMPARE_PREFIX(sqincp(x5, p15.VnS()), "sqincp x5, p15.s"); in TEST()
1958 COMPARE_PREFIX(sqincp(x5, p15.VnD()), "sqincp x5, p15.d"); in TEST()
1959 COMPARE_PREFIX(sqincp(z14.VnH(), p4), "sqincp z14.h, p4"); in TEST()
1960 COMPARE_PREFIX(sqincp(z14.VnS(), p4), "sqincp z14.s, p4"); in TEST()
[all …]
Dtest-api-movprfx-aarch64.cc1148 __ sqincp(z4.VnD(), p7); in TEST() local
1516 __ sqincp(z7.VnS(), p6); in TEST() local
/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/AArch64/
DAArch64GenAsmMatcher.inc12571 "l2\010sqdmullb\010sqdmullt\006sqincb\006sqincd\006sqinch\006sqincp\006s"
17688 …{ 4778 /* sqincp */, AArch64::SQINCP_XP_H, Convert__Reg1_0__SVEPredicateHReg1_1__Tie0_1_1, AMFBS_H…
17689 …{ 4778 /* sqincp */, AArch64::SQINCP_XP_S, Convert__Reg1_0__SVEPredicateSReg1_1__Tie0_1_1, AMFBS_H…
17690 …{ 4778 /* sqincp */, AArch64::SQINCP_XP_D, Convert__Reg1_0__SVEPredicateDReg1_1__Tie0_1_1, AMFBS_H…
17691 …{ 4778 /* sqincp */, AArch64::SQINCP_XP_B, Convert__Reg1_0__SVEPredicateBReg1_1__Tie0_1_1, AMFBS_H…
17692 …{ 4778 /* sqincp */, AArch64::SQINCP_ZP_H, Convert__SVEVectorHReg1_0__Tie0_1_1__SVEPredicateHReg1_…
17693 …{ 4778 /* sqincp */, AArch64::SQINCP_ZP_H, Convert__SVEVectorHReg1_0__Tie0_1_1__SVEPredicateAnyReg…
17694 …{ 4778 /* sqincp */, AArch64::SQINCP_ZP_S, Convert__SVEVectorSReg1_0__Tie0_1_1__SVEPredicateSReg1_…
17695 …{ 4778 /* sqincp */, AArch64::SQINCP_ZP_S, Convert__SVEVectorSReg1_0__Tie0_1_1__SVEPredicateAnyReg…
17696 …{ 4778 /* sqincp */, AArch64::SQINCP_ZP_D, Convert__SVEVectorDReg1_0__Tie0_1_1__SVEPredicateDReg1_…
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64SVEInstrInfo.td913 defm SQINCP_XPWd : sve_int_count_r_s32<0b00000, "sqincp", int_aarch64_sve_sqincp_n32>;
914 defm SQINCP_XP : sve_int_count_r_x64<0b00010, "sqincp", int_aarch64_sve_sqincp_n64>;
924 defm SQINCP_ZP : sve_int_count_v<0b00000, "sqincp", int_aarch64_sve_sqincp>;
/external/vixl/src/aarch64/
Dassembler-aarch64.h5387 void sqincp(const Register& xd,
5392 void sqincp(const Register& xdn, const PRegisterWithLaneSize& pg);
5395 void sqincp(const ZRegister& zdn, const PRegister& pg);
Dassembler-sve-aarch64.cc2091 void Assembler::sqincp(const Register& xd, in sqincp() function in vixl::aarch64::Assembler
2106 void Assembler::sqincp(const Register& xdn, const PRegisterWithLaneSize& pg) { in sqincp() function in vixl::aarch64::Assembler
2118 void Assembler::sqincp(const ZRegister& zdn, const PRegister& pg) { in sqincp() function in vixl::aarch64::Assembler
Dmacro-assembler-aarch64.h5819 sqincp(xdn, pg, wdn); in Sqincp()
5824 sqincp(xdn, pg); in Sqincp()
5831 sqincp(zd, pg); in Sqincp()
/external/llvm-project/llvm/lib/Target/AArch64/
DAArch64SVEInstrInfo.td1359 defm SQINCP_XPWd : sve_int_count_r_s32<0b00000, "sqincp", int_aarch64_sve_sqincp_n32>;
1360 defm SQINCP_XP : sve_int_count_r_x64<0b00010, "sqincp", int_aarch64_sve_sqincp_n64>;
1370 defm SQINCP_ZP : sve_int_count_v<0b00000, "sqincp", int_aarch64_sve_sqincp>;
/external/swiftshader/third_party/llvm-10.0/configs/common/include/llvm/IR/
DIntrinsicImpl.inc747 "llvm.aarch64.sve.sqincp",
748 "llvm.aarch64.sve.sqincp.n32",
749 "llvm.aarch64.sve.sqincp.n64",
10880 1, // llvm.aarch64.sve.sqincp
10881 1, // llvm.aarch64.sve.sqincp.n32
10882 1, // llvm.aarch64.sve.sqincp.n64