1; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve -asm-verbose=0 < %s 2>%t | FileCheck %s 2; RUN: FileCheck --check-prefix=WARN --allow-empty %s <%t 3 4; If this check fails please read test/CodeGen/AArch64/README for instructions on how to resolve it. 5; WARN-NOT: warning 6 7; Since SQDEC{B|H|W|D|P} and SQINC{B|H|W|D|P} have identical semantics, the tests for 8; * @llvm.aarch64.sve.sqinc{b|h|w|d|p}, and 9; * @llvm.aarch64.sve.sqdec{b|h|w|d|p} 10; should also be identical (with the instruction name being adjusted). When 11; updating this file remember to make similar changes in the file testing the 12; other intrinsic. 13 14; 15; SQINCH (vector) 16; 17 18define <vscale x 8 x i16> @sqinch(<vscale x 8 x i16> %a) { 19; CHECK-LABEL: sqinch: 20; CHECK: sqinch z0.h, pow2 21; CHECK-NEXT: ret 22 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.sqinch.nxv8i16(<vscale x 8 x i16> %a, 23 i32 0, i32 1) 24 ret <vscale x 8 x i16> %out 25} 26 27; 28; SQINCW (vector) 29; 30 31define <vscale x 4 x i32> @sqincw(<vscale x 4 x i32> %a) { 32; CHECK-LABEL: sqincw: 33; CHECK: sqincw z0.s, vl1, mul #2 34; CHECK-NEXT: ret 35 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.sqincw.nxv4i32(<vscale x 4 x i32> %a, 36 i32 1, i32 2) 37 ret <vscale x 4 x i32> %out 38} 39 40; 41; SQINCD (vector) 42; 43 44define <vscale x 2 x i64> @sqincd(<vscale x 2 x i64> %a) { 45; CHECK-LABEL: sqincd: 46; CHECK: sqincd z0.d, vl2, mul #3 47; CHECK-NEXT: ret 48 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.sqincd.nxv2i64(<vscale x 2 x i64> %a, 49 i32 2, i32 3) 50 ret <vscale x 2 x i64> %out 51} 52 53; 54; SQINCP (vector) 55; 56 57define <vscale x 8 x i16> @sqincp_b16(<vscale x 8 x i16> %a, <vscale x 8 x i1> %b) { 58; CHECK-LABEL: sqincp_b16: 59; CHECK: sqincp z0.h, p0 60; CHECK-NEXT: ret 61 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.sqincp.nxv8i16(<vscale x 8 x i16> %a, 62 <vscale x 8 x i1> %b) 63 ret <vscale x 8 x i16> %out 64} 65 66define <vscale x 4 x i32> @sqincp_b32(<vscale x 4 x i32> %a, <vscale x 4 x i1> %b) { 67; CHECK-LABEL: sqincp_b32: 68; CHECK: sqincp z0.s, p0 69; CHECK-NEXT: ret 70 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.sqincp.nxv4i32(<vscale x 4 x i32> %a, 71 <vscale x 4 x i1> %b) 72 ret <vscale x 4 x i32> %out 73} 74 75define <vscale x 2 x i64> @sqincp_b64(<vscale x 2 x i64> %a, <vscale x 2 x i1> %b) { 76; CHECK-LABEL: sqincp_b64: 77; CHECK: sqincp z0.d, p0 78; CHECK-NEXT: ret 79 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.sqincp.nxv2i64(<vscale x 2 x i64> %a, 80 <vscale x 2 x i1> %b) 81 ret <vscale x 2 x i64> %out 82} 83 84; 85; SQINCB (scalar) 86; 87 88define i32 @sqincb_n32_i32(i32 %a) { 89; CHECK-LABEL: sqincb_n32_i32: 90; CHECK: sqincb x0, w0, vl3, mul #4 91; CHECK-NEXT: ret 92 %out = call i32 @llvm.aarch64.sve.sqincb.n32(i32 %a, i32 3, i32 4) 93 ret i32 %out 94} 95 96define i64 @sqincb_n32_i64(i32 %a) { 97; CHECK-LABEL: sqincb_n32_i64: 98; CHECK: sqincb x0, w0, vl3, mul #4 99; CHECK-NEXT: ret 100 %out = call i32 @llvm.aarch64.sve.sqincb.n32(i32 %a, i32 3, i32 4) 101 %out_sext = sext i32 %out to i64 102 103 ret i64 %out_sext 104} 105 106define i64 @sqincb_n64(i64 %a) { 107; CHECK-LABEL: sqincb_n64: 108; CHECK: sqincb x0, vl4, mul #5 109; CHECK-NEXT: ret 110 %out = call i64 @llvm.aarch64.sve.sqincb.n64(i64 %a, i32 4, i32 5) 111 ret i64 %out 112} 113 114; 115; SQINCH (scalar) 116; 117 118define i32 @sqinch_n32_i32(i32 %a) { 119; CHECK-LABEL: sqinch_n32_i32: 120; CHECK: sqinch x0, w0, vl5, mul #6 121; CHECK-NEXT: ret 122 %out = call i32 @llvm.aarch64.sve.sqinch.n32(i32 %a, i32 5, i32 6) 123 ret i32 %out 124} 125 126define i64 @sqinch_n32_i64(i32 %a) { 127; CHECK-LABEL: sqinch_n32_i64: 128; CHECK: sqinch x0, w0, vl3, mul #4 129; CHECK-NEXT: ret 130 %out = call i32 @llvm.aarch64.sve.sqinch.n32(i32 %a, i32 3, i32 4) 131 %out_sext = sext i32 %out to i64 132 133 ret i64 %out_sext 134} 135 136define i64 @sqinch_n64(i64 %a) { 137; CHECK-LABEL: sqinch_n64: 138; CHECK: sqinch x0, vl6, mul #7 139; CHECK-NEXT: ret 140 %out = call i64 @llvm.aarch64.sve.sqinch.n64(i64 %a, i32 6, i32 7) 141 ret i64 %out 142} 143 144; 145; SQINCW (scalar) 146; 147 148define i32 @sqincw_n32_i32(i32 %a) { 149; CHECK-LABEL: sqincw_n32_i32: 150; CHECK: sqincw x0, w0, vl7, mul #8 151; CHECK-NEXT: ret 152 %out = call i32 @llvm.aarch64.sve.sqincw.n32(i32 %a, i32 7, i32 8) 153 ret i32 %out 154} 155 156define i64 @sqincw_n32_i64(i32 %a) { 157; CHECK-LABEL: sqincw_n32_i64: 158; CHECK: sqincw x0, w0, vl3, mul #4 159; CHECK-NEXT: ret 160 %out = call i32 @llvm.aarch64.sve.sqincw.n32(i32 %a, i32 3, i32 4) 161 %out_sext = sext i32 %out to i64 162 163 ret i64 %out_sext 164} 165 166define i64 @sqincw_n64(i64 %a) { 167; CHECK-LABEL: sqincw_n64: 168; CHECK: sqincw x0, vl8, mul #9 169; CHECK-NEXT: ret 170 %out = call i64 @llvm.aarch64.sve.sqincw.n64(i64 %a, i32 8, i32 9) 171 ret i64 %out 172} 173 174; 175; SQINCD (scalar) 176; 177 178define i32 @sqincd_n32_i32(i32 %a) { 179; CHECK-LABEL: sqincd_n32_i32: 180; CHECK: sqincd x0, w0, vl16, mul #10 181; CHECK-NEXT: ret 182 %out = call i32 @llvm.aarch64.sve.sqincd.n32(i32 %a, i32 9, i32 10) 183 ret i32 %out 184} 185 186define i64 @sqincd_n32_i64(i32 %a) { 187; CHECK-LABEL: sqincd_n32_i64: 188; CHECK: sqincd x0, w0, vl3, mul #4 189; CHECK-NEXT: ret 190 %out = call i32 @llvm.aarch64.sve.sqincd.n32(i32 %a, i32 3, i32 4) 191 %out_sext = sext i32 %out to i64 192 193 ret i64 %out_sext 194} 195 196define i64 @sqincd_n64(i64 %a) { 197; CHECK-LABEL: sqincd_n64: 198; CHECK: sqincd x0, vl32, mul #11 199; CHECK-NEXT: ret 200 %out = call i64 @llvm.aarch64.sve.sqincd.n64(i64 %a, i32 10, i32 11) 201 ret i64 %out 202} 203 204; 205; SQINCP (scalar) 206; 207 208define i32 @sqincp_n32_b8_i32(i32 %a, <vscale x 16 x i1> %b) { 209; CHECK-LABEL: sqincp_n32_b8_i32: 210; CHECK: sqincp x0, p0.b, w0 211; CHECK-NEXT: ret 212 %out = call i32 @llvm.aarch64.sve.sqincp.n32.nxv16i1(i32 %a, <vscale x 16 x i1> %b) 213 ret i32 %out 214} 215 216define i64 @sqincp_n32_b8_i64(i32 %a, <vscale x 16 x i1> %b) { 217; CHECK-LABEL: sqincp_n32_b8_i64: 218; CHECK: sqincp x0, p0.b, w0 219; CHECK-NEXT: ret 220 %out = call i32 @llvm.aarch64.sve.sqincp.n32.nxv16i1(i32 %a, <vscale x 16 x i1> %b) 221 %out_sext = sext i32 %out to i64 222 223 ret i64 %out_sext 224} 225 226define i32 @sqincp_n32_b16_i32(i32 %a, <vscale x 8 x i1> %b) { 227; CHECK-LABEL: sqincp_n32_b16_i32: 228; CHECK: sqincp x0, p0.h, w0 229; CHECK-NEXT: ret 230 %out = call i32 @llvm.aarch64.sve.sqincp.n32.nxv8i1(i32 %a, <vscale x 8 x i1> %b) 231 ret i32 %out 232} 233 234define i64 @sqincp_n32_b16_i64(i32 %a, <vscale x 8 x i1> %b) { 235; CHECK-LABEL: sqincp_n32_b16_i64: 236; CHECK: sqincp x0, p0.h, w0 237; CHECK-NEXT: ret 238 %out = call i32 @llvm.aarch64.sve.sqincp.n32.nxv8i1(i32 %a, <vscale x 8 x i1> %b) 239 %out_sext = sext i32 %out to i64 240 241 ret i64 %out_sext 242} 243 244define i32 @sqincp_n32_b32_i32(i32 %a, <vscale x 4 x i1> %b) { 245; CHECK-LABEL: sqincp_n32_b32_i32: 246; CHECK: sqincp x0, p0.s, w0 247; CHECK-NEXT: ret 248 %out = call i32 @llvm.aarch64.sve.sqincp.n32.nxv4i1(i32 %a, <vscale x 4 x i1> %b) 249 ret i32 %out 250} 251 252define i64 @sqincp_n32_b32_i64(i32 %a, <vscale x 4 x i1> %b) { 253; CHECK-LABEL: sqincp_n32_b32_i64: 254; CHECK: sqincp x0, p0.s, w0 255; CHECK-NEXT: ret 256 %out = call i32 @llvm.aarch64.sve.sqincp.n32.nxv4i1(i32 %a, <vscale x 4 x i1> %b) 257 %out_sext = sext i32 %out to i64 258 259 ret i64 %out_sext 260} 261 262define i32 @sqincp_n32_b64_i32(i32 %a, <vscale x 2 x i1> %b) { 263; CHECK-LABEL: sqincp_n32_b64_i32: 264; CHECK: sqincp x0, p0.d, w0 265; CHECK-NEXT: ret 266 %out = call i32 @llvm.aarch64.sve.sqincp.n32.nxv2i1(i32 %a, <vscale x 2 x i1> %b) 267 ret i32 %out 268} 269 270define i64 @sqincp_n32_b64_i64(i32 %a, <vscale x 2 x i1> %b) { 271; CHECK-LABEL: sqincp_n32_b64_i64: 272; CHECK: sqincp x0, p0.d, w0 273; CHECK-NEXT: ret 274 %out = call i32 @llvm.aarch64.sve.sqincp.n32.nxv2i1(i32 %a, <vscale x 2 x i1> %b) 275 %out_sext = sext i32 %out to i64 276 277 ret i64 %out_sext 278} 279 280define i64 @sqincp_n64_b8(i64 %a, <vscale x 16 x i1> %b) { 281; CHECK-LABEL: sqincp_n64_b8: 282; CHECK: sqincp x0, p0.b 283; CHECK-NEXT: ret 284 %out = call i64 @llvm.aarch64.sve.sqincp.n64.nxv16i1(i64 %a, <vscale x 16 x i1> %b) 285 ret i64 %out 286} 287 288define i64 @sqincp_n64_b16(i64 %a, <vscale x 8 x i1> %b) { 289; CHECK-LABEL: sqincp_n64_b16: 290; CHECK: sqincp x0, p0.h 291; CHECK-NEXT: ret 292 %out = call i64 @llvm.aarch64.sve.sqincp.n64.nxv8i1(i64 %a, <vscale x 8 x i1> %b) 293 ret i64 %out 294} 295 296define i64 @sqincp_n64_b32(i64 %a, <vscale x 4 x i1> %b) { 297; CHECK-LABEL: sqincp_n64_b32: 298; CHECK: sqincp x0, p0.s 299; CHECK-NEXT: ret 300 %out = call i64 @llvm.aarch64.sve.sqincp.n64.nxv4i1(i64 %a, <vscale x 4 x i1> %b) 301 ret i64 %out 302} 303 304define i64 @sqincp_n64_b64(i64 %a, <vscale x 2 x i1> %b) { 305; CHECK-LABEL: sqincp_n64_b64: 306; CHECK: sqincp x0, p0.d 307; CHECK-NEXT: ret 308 %out = call i64 @llvm.aarch64.sve.sqincp.n64.nxv2i1(i64 %a, <vscale x 2 x i1> %b) 309 ret i64 %out 310} 311 312; sqinc{h|w|d}(vector, pattern, multiplier) 313declare <vscale x 8 x i16> @llvm.aarch64.sve.sqinch.nxv8i16(<vscale x 8 x i16>, i32, i32) 314declare <vscale x 4 x i32> @llvm.aarch64.sve.sqincw.nxv4i32(<vscale x 4 x i32>, i32, i32) 315declare <vscale x 2 x i64> @llvm.aarch64.sve.sqincd.nxv2i64(<vscale x 2 x i64>, i32, i32) 316 317; sqinc{b|h|w|d}(scalar, pattern, multiplier) 318declare i32 @llvm.aarch64.sve.sqincb.n32(i32, i32, i32) 319declare i64 @llvm.aarch64.sve.sqincb.n64(i64, i32, i32) 320declare i32 @llvm.aarch64.sve.sqinch.n32(i32, i32, i32) 321declare i64 @llvm.aarch64.sve.sqinch.n64(i64, i32, i32) 322declare i32 @llvm.aarch64.sve.sqincw.n32(i32, i32, i32) 323declare i64 @llvm.aarch64.sve.sqincw.n64(i64, i32, i32) 324declare i32 @llvm.aarch64.sve.sqincd.n32(i32, i32, i32) 325declare i64 @llvm.aarch64.sve.sqincd.n64(i64, i32, i32) 326 327; sqincp(scalar, predicate) 328declare i32 @llvm.aarch64.sve.sqincp.n32.nxv16i1(i32, <vscale x 16 x i1>) 329declare i32 @llvm.aarch64.sve.sqincp.n32.nxv8i1(i32, <vscale x 8 x i1>) 330declare i32 @llvm.aarch64.sve.sqincp.n32.nxv4i1(i32, <vscale x 4 x i1>) 331declare i32 @llvm.aarch64.sve.sqincp.n32.nxv2i1(i32, <vscale x 2 x i1>) 332 333declare i64 @llvm.aarch64.sve.sqincp.n64.nxv16i1(i64, <vscale x 16 x i1>) 334declare i64 @llvm.aarch64.sve.sqincp.n64.nxv8i1(i64, <vscale x 8 x i1>) 335declare i64 @llvm.aarch64.sve.sqincp.n64.nxv4i1(i64, <vscale x 4 x i1>) 336declare i64 @llvm.aarch64.sve.sqincp.n64.nxv2i1(i64, <vscale x 2 x i1>) 337 338; sqincp(vector, predicate) 339declare <vscale x 8 x i16> @llvm.aarch64.sve.sqincp.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i1>) 340declare <vscale x 4 x i32> @llvm.aarch64.sve.sqincp.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i1>) 341declare <vscale x 2 x i64> @llvm.aarch64.sve.sqincp.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i1>) 342