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Searched refs:sqincw (Results 1 – 13 of 13) sorted by relevance

/external/llvm-project/llvm/test/MC/AArch64/SVE/
Dsqincw.s14 sqincw x0 label
20 sqincw x0, all label
26 sqincw x0, all, mul #1 label
32 sqincw x0, all, mul #16 label
43 sqincw x0, w0 label
49 sqincw x0, w0, all label
55 sqincw x0, w0, all, mul #1 label
61 sqincw x0, w0, all, mul #16 label
67 sqincw x0, w0, pow2 label
73 sqincw x0, w0, pow2, mul #16 label
[all …]
Dsqincw-diagnostics.s6 sqincw w0 label
11 sqincw wsp label
16 sqincw sp label
21 sqincw z0.d label
30 sqincw x0, w1 label
35 sqincw x0, x0 label
44 sqincw x0, all, mul #-1 label
49 sqincw x0, all, mul #0 label
54 sqincw x0, all, mul #17 label
63 sqincw x0, vl512 label
[all …]
/external/llvm-project/llvm/test/CodeGen/AArch64/
Dsve-intrinsics-sqinc.ll31 define <vscale x 4 x i32> @sqincw(<vscale x 4 x i32> %a) {
32 ; CHECK-LABEL: sqincw:
33 ; CHECK: sqincw z0.s, vl1, mul #2
35 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.sqincw.nxv4i32(<vscale x 4 x i32> %a,
150 ; CHECK: sqincw x0, w0, vl7, mul #8
152 %out = call i32 @llvm.aarch64.sve.sqincw.n32(i32 %a, i32 7, i32 8)
158 ; CHECK: sqincw x0, w0, vl3, mul #4
160 %out = call i32 @llvm.aarch64.sve.sqincw.n32(i32 %a, i32 3, i32 4)
168 ; CHECK: sqincw x0, vl8, mul #9
170 %out = call i64 @llvm.aarch64.sve.sqincw.n64(i64 %a, i32 8, i32 9)
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64SVEInstrInfo.td876 defm SQINCW_XPiWdI : sve_int_pred_pattern_b_s32<0b10000, "sqincw", int_aarch64_sve_sqincw_n32>;
880 defm SQINCW_XPiI : sve_int_pred_pattern_b_x64<0b10100, "sqincw", int_aarch64_sve_sqincw_n64>;
900 defm SQINCW_ZPiI : sve_int_countvlv<0b10000, "sqincw", ZPR32, int_aarch64_sve_sqincw, nxv4i32>;
/external/vixl/src/aarch64/
Dassembler-aarch64.h5399 void sqincw(const Register& xd,
5406 void sqincw(const Register& rdn, int pattern = SVE_ALL, int multiplier = 1);
5410 void sqincw(const ZRegister& zdn, int pattern = SVE_ALL, int multiplier = 1);
Dassembler-sve-aarch64.cc465 V(sqincw, SQINCW_r_rs_x) \
504 V(sqincw, SQINCW) \ in VIXL_SVE_UQINC_UQDEC_LIST()
532 V(sqincw, SQINC, W) \
Dmacro-assembler-aarch64.h5842 sqincw(xd, wn, pattern, multiplier);
5847 sqincw(rdn, pattern, multiplier);
5852 sqincw(zdn, pattern, multiplier);
/external/vixl/test/aarch64/
Dtest-api-movprfx-aarch64.cc1151 __ sqincw(z29.VnS(), SVE_ALL); in TEST() local
1519 __ sqincw(z10.VnS(), SVE_ALL); in TEST() local
/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/AArch64/
DAArch64GenAsmMatcher.inc17702 …{ 4785 /* sqincw */, AArch64::SQINCW_XPiI, Convert__Reg1_0__Tie0_1_1__imm_95_31__imm_95_1, AMFBS_H…
17703 …{ 4785 /* sqincw */, AArch64::SQINCW_ZPiI, Convert__SVEVectorSReg1_0__Tie0_1_1__imm_95_31__imm_95_…
17704 …{ 4785 /* sqincw */, AArch64::SQINCW_XPiWdI, Convert__Reg1_0__Tie255_1_2__GPR64as321_1__imm_95_31_…
17705 …{ 4785 /* sqincw */, AArch64::SQINCW_XPiI, Convert__Reg1_0__Tie0_1_1__SVEPattern1_1__imm_95_1, AMF…
17706 …{ 4785 /* sqincw */, AArch64::SQINCW_ZPiI, Convert__SVEVectorSReg1_0__Tie0_1_1__SVEPattern1_1__imm…
17707 …{ 4785 /* sqincw */, AArch64::SQINCW_XPiWdI, Convert__Reg1_0__Tie255_1_2__GPR64as321_1__SVEPattern…
17708 …{ 4785 /* sqincw */, AArch64::SQINCW_XPiI, Convert__Reg1_0__Tie0_1_1__SVEPattern1_1__Imm1_161_3, A…
17709 …{ 4785 /* sqincw */, AArch64::SQINCW_ZPiI, Convert__SVEVectorSReg1_0__Tie0_1_1__SVEPattern1_1__Imm…
17710 …{ 4785 /* sqincw */, AArch64::SQINCW_XPiWdI, Convert__Reg1_0__Tie0_1_2__SVEPattern1_2__Imm1_161_4,…
25075 …{ 4785 /* sqincw */, AArch64::SQINCW_XPiI, Convert__Reg1_0__Tie0_1_1__imm_95_31__imm_95_1, AMFBS_H…
[all …]
DAArch64GenAsmWriter.inc22654 /* 10314 */ "sqincw $\x01\0"
22655 /* 10324 */ "sqincw $\x01, $\xFF\x03\x0E\0"
22656 /* 10340 */ "sqincw $\x01, $\xFF\x02\x35\0"
22657 /* 10356 */ "sqincw $\x01, $\xFF\x02\x35, $\xFF\x03\x0E\0"
22658 /* 10378 */ "sqincw $\xFF\x01\x0B\0"
22659 /* 10390 */ "sqincw $\xFF\x01\x0B, $\xFF\x03\x0E\0"
DAArch64GenAsmWriter1.inc23375 /* 10292 */ "sqincw $\x01\0"
23376 /* 10302 */ "sqincw $\x01, $\xFF\x03\x0E\0"
23377 /* 10318 */ "sqincw $\x01, $\xFF\x02\x35\0"
23378 /* 10334 */ "sqincw $\x01, $\xFF\x02\x35, $\xFF\x03\x0E\0"
23379 /* 10356 */ "sqincw $\xFF\x01\x0B\0"
23380 /* 10368 */ "sqincw $\xFF\x01\x0B, $\xFF\x03\x0E\0"
/external/llvm-project/llvm/lib/Target/AArch64/
DAArch64SVEInstrInfo.td1322 defm SQINCW_XPiWdI : sve_int_pred_pattern_b_s32<0b10000, "sqincw", int_aarch64_sve_sqincw_n32>;
1326 defm SQINCW_XPiI : sve_int_pred_pattern_b_x64<0b10100, "sqincw", int_aarch64_sve_sqincw_n64>;
1346 defm SQINCW_ZPiI : sve_int_countvlv<0b10000, "sqincw", ZPR32, int_aarch64_sve_sqincw, nxv4i32>;
/external/swiftshader/third_party/llvm-10.0/configs/common/include/llvm/IR/
DIntrinsicImpl.inc750 "llvm.aarch64.sve.sqincw",
751 "llvm.aarch64.sve.sqincw.n32",
752 "llvm.aarch64.sve.sqincw.n64",
10883 47, // llvm.aarch64.sve.sqincw
10884 47, // llvm.aarch64.sve.sqincw.n32
10885 47, // llvm.aarch64.sve.sqincw.n64