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Searched refs:sscreen (Results 1 – 25 of 42) sorted by relevance

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/external/mesa3d/src/gallium/drivers/radeonsi/
Dsi_pipe.c139 void si_init_compiler(struct si_screen *sscreen, struct ac_llvm_compiler *compiler) in si_init_compiler() argument
144 !sscreen->info.has_dedicated_vram && sscreen->info.chip_class <= GFX8; in si_init_compiler()
147 (sscreen->debug_flags & DBG(GISEL) ? AC_TM_ENABLE_GLOBAL_ISEL : 0) | in si_init_compiler()
148 (sscreen->info.chip_class <= GFX8 ? AC_TM_FORCE_DISABLE_XNACK : in si_init_compiler()
149 sscreen->info.chip_class <= GFX10 ? AC_TM_FORCE_ENABLE_XNACK : 0) | in si_init_compiler()
150 (!sscreen->llvm_has_working_vgpr_indexing ? AC_TM_PROMOTE_ALLOCA_TO_SCRATCH : 0) | in si_init_compiler()
151 (sscreen->debug_flags & DBG(CHECK_IR) ? AC_TM_CHECK_IR : 0) | in si_init_compiler()
155 ac_init_llvm_compiler(compiler, sscreen->info.family, tm_options); in si_init_compiler()
334 struct si_screen *sscreen = sctx->screen; in si_get_reset_status() local
346 simple_mtx_lock(&sscreen->aux_context_lock); in si_get_reset_status()
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Dsi_gpu_load.c80 static void si_update_mmio_counters(struct si_screen *sscreen, union si_mmio_counters *counters) in si_update_mmio_counters() argument
86 sscreen->ws->read_registers(sscreen->ws, GRBM_STATUS, 1, &value); in si_update_mmio_counters()
104 if (sscreen->info.chip_class == GFX7 || sscreen->info.chip_class == GFX8) { in si_update_mmio_counters()
106 sscreen->ws->read_registers(sscreen->ws, SRBM_STATUS2, 1, &value); in si_update_mmio_counters()
112 if (sscreen->info.chip_class >= GFX8) { in si_update_mmio_counters()
114 sscreen->ws->read_registers(sscreen->ws, CP_STAT, 1, &value); in si_update_mmio_counters()
132 struct si_screen *sscreen = (struct si_screen *)param; in si_gpu_load_thread() local
137 while (!p_atomic_read(&sscreen->gpu_load_stop_thread)) { in si_gpu_load_thread()
154 si_update_mmio_counters(sscreen, &sscreen->mmio_counters); in si_gpu_load_thread()
156 p_atomic_dec(&sscreen->gpu_load_stop_thread); in si_gpu_load_thread()
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Dsi_get.c48 struct si_screen *sscreen = (struct si_screen *)pscreen; in si_get_param() local
172 return !sscreen->use_ngg_streamout; in si_get_param()
175 return sscreen->info.chip_class >= GFX10; in si_get_param()
178 return sscreen->info.has_graphics; in si_get_param()
181 return !SI_BIG_ENDIAN && sscreen->info.has_userptr; in si_get_param()
184 return sscreen->info.has_gpu_reset_status_query; in si_get_param()
187 return sscreen->info.has_tmz_support; in si_get_param()
190 return sscreen->info.has_2d_tiling; in si_get_param()
206 if (!sscreen->info.has_indirect_compute_dispatch) in si_get_param()
220 return ROUND_DOWN_TO(MIN2(sscreen->info.max_alloc_size, INT_MAX), 256); in si_get_param()
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Dsi_texture.c45 static enum radeon_surf_mode si_choose_tiling(struct si_screen *sscreen,
181 static unsigned si_texture_get_offset(struct si_screen *sscreen, struct si_texture *tex, in si_texture_get_offset() argument
185 if (sscreen->info.chip_class >= GFX9) { in si_texture_get_offset()
217 static int si_init_surface(struct si_screen *sscreen, struct radeon_surf *surface, in si_init_surface() argument
240 if ((sscreen->debug_flags & DBG(NO_HYPERZ)) || in si_init_surface()
244 (sscreen->info.chip_class >= GFX9 || array_mode == RADEON_SURF_MODE_2D)) { in si_init_surface()
250 if (sscreen->info.chip_class == GFX8) in si_init_surface()
260 if (sscreen->info.chip_class >= GFX8 && in si_init_surface()
262 (sscreen->info.chip_class < GFX10_3 && in si_init_surface()
264 (ptex->nr_samples >= 2 && !sscreen->dcc_msaa_allowed))) in si_init_surface()
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Dsi_state_shaders.c218 void si_shader_cache_insert_shader(struct si_screen *sscreen, unsigned char ir_sha1_cache_key[20], in si_shader_cache_insert_shader() argument
225 entry = _mesa_hash_table_search(sscreen->shader_cache, ir_sha1_cache_key); in si_shader_cache_insert_shader()
233 if (_mesa_hash_table_insert(sscreen->shader_cache, mem_dup(ir_sha1_cache_key, 20), hw_binary) == in si_shader_cache_insert_shader()
239 if (sscreen->disk_shader_cache && insert_into_disk_cache) { in si_shader_cache_insert_shader()
240 disk_cache_compute_key(sscreen->disk_shader_cache, ir_sha1_cache_key, 20, key); in si_shader_cache_insert_shader()
241 disk_cache_put(sscreen->disk_shader_cache, key, hw_binary, *((uint32_t *)hw_binary), NULL); in si_shader_cache_insert_shader()
245 bool si_shader_cache_load_shader(struct si_screen *sscreen, unsigned char ir_sha1_cache_key[20], in si_shader_cache_load_shader() argument
248 struct hash_entry *entry = _mesa_hash_table_search(sscreen->shader_cache, ir_sha1_cache_key); in si_shader_cache_load_shader()
252 p_atomic_inc(&sscreen->num_memory_shader_cache_hits); in si_shader_cache_load_shader()
256 p_atomic_inc(&sscreen->num_memory_shader_cache_misses); in si_shader_cache_load_shader()
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Dsi_buffer.c100 void si_init_resource_fields(struct si_screen *sscreen, struct si_resource *res, uint64_t size, in si_init_resource_fields() argument
124 if (!sscreen->info.kernel_flushes_hdp_before_ib) { in si_init_resource_fields()
152 if (!sscreen->info.kernel_flushes_hdp_before_ib || !sscreen->info.is_amdgpu) in si_init_resource_fields()
171 (sscreen->debug_flags & DBG(TMZ) && in si_init_resource_fields()
178 if (sscreen->debug_flags & DBG(NO_WC)) in si_init_resource_fields()
194 if (sscreen->info.chip_class >= GFX9 && in si_init_resource_fields()
208 sscreen->info.has_dedicated_vram && size >= sscreen->info.vram_vis_size / 4 ? 1 : 0; in si_init_resource_fields()
214 bool si_alloc_resource(struct si_screen *sscreen, struct si_resource *res) in si_alloc_resource() argument
219 new_buf = sscreen->ws->buffer_create(sscreen->ws, res->bo_size, res->bo_alignment, res->domains, in si_alloc_resource()
231 res->gpu_address = sscreen->ws->buffer_get_virtual_address(res->buf); in si_alloc_resource()
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Dsi_shader.c871 bool si_shader_binary_upload(struct si_screen *sscreen, struct si_shader *shader, in si_shader_binary_upload() argument
875 if (!si_shader_binary_open(sscreen, shader, &binary)) in si_shader_binary_upload()
880 &sscreen->b, in si_shader_binary_upload()
881 (sscreen->info.cpdma_prefetch_writes_memory ? in si_shader_binary_upload()
893 u.rx_ptr = sscreen->ws->buffer_map( in si_shader_binary_upload()
901 sscreen->ws->buffer_unmap(shader->bo->buf); in si_shader_binary_upload()
969 struct si_screen *sscreen = shader->selector->screen; in si_calculate_max_simd_waves() local
972 unsigned lds_increment = sscreen->info.chip_class >= GFX7 ? 512 : 256; in si_calculate_max_simd_waves()
976 max_simd_waves = sscreen->info.max_wave64_per_simd; in si_calculate_max_simd_waves()
996 DIV_ROUND_UP(max_workgroup_size, sscreen->compute_wave_size); in si_calculate_max_simd_waves()
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Dsi_compute.c36 #define COMPUTE_DBG(sscreen, fmt, args...) \ argument
38 if ((sscreen->debug_flags & DBG(COMPUTE))) \
117 struct si_screen *sscreen = sel->screen; in si_create_compute_state_async() local
121 assert(thread_index < ARRAY_SIZE(sscreen->compiler)); in si_create_compute_state_async()
122 compiler = &sscreen->compiler[thread_index]; in si_create_compute_state_async()
125 si_init_compiler(sscreen, compiler); in si_create_compute_state_async()
172 simple_mtx_lock(&sscreen->shader_cache_mutex); in si_create_compute_state_async()
174 if (si_shader_cache_load_shader(sscreen, ir_sha1_cache_key, shader)) { in si_create_compute_state_async()
175 simple_mtx_unlock(&sscreen->shader_cache_mutex); in si_create_compute_state_async()
177 si_shader_dump_stats_for_shader_db(sscreen, shader, debug); in si_create_compute_state_async()
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Dsi_state_binning.c43 static struct uvec2 si_find_bin_size(struct si_screen *sscreen, const si_bin_size_subtable table[], in si_find_bin_size() argument
47 util_logbase2_ceil(sscreen->info.num_render_backends / sscreen->info.max_se); in si_find_bin_size()
48 unsigned log_num_se = util_logbase2_ceil(sscreen->info.max_se); in si_find_bin_size()
452 struct si_screen *sscreen = sctx->screen; in si_emit_dpbb_state() local
459 if (!sscreen->dpbb_allowed || sctx->dpbb_force_off) { in si_emit_dpbb_state()
473 if (sscreen->info.num_render_backends > 4 && ps_can_kill && db_can_reject_z_trivially && in si_emit_dpbb_state()
509 if (sscreen->dfsm_allowed && !zs_eqaa_dfsm_bug && cb_target_enabled_4bit && in si_emit_dpbb_state()
535 S_028C44_CONTEXT_STATES_PER_BIN(sscreen->pbb_context_states_per_bin - 1) | in si_emit_dpbb_state()
536 S_028C44_PERSISTENT_STATES_PER_BIN(sscreen->pbb_persistent_states_per_bin - 1) | in si_emit_dpbb_state()
Dsi_shader_nir.c416 struct si_screen *sscreen = (struct si_screen *)data; in si_alu_to_scalar_filter() local
418 if (sscreen->info.has_packed_math_16bit && in si_alu_to_scalar_filter()
431 void si_nir_opts(struct si_screen *sscreen, struct nir_shader *nir, bool first) in si_nir_opts() argument
436 NIR_PASS_V(nir, nir_lower_alu_to_scalar, si_alu_to_scalar_filter, sscreen); in si_nir_opts()
461 NIR_PASS_V(nir, nir_lower_alu_to_scalar, si_alu_to_scalar_filter, sscreen); in si_nir_opts()
498 if (sscreen->info.has_packed_math_16bit) in si_nir_opts()
644 static void si_lower_nir(struct si_screen *sscreen, struct nir_shader *nir) in si_lower_nir() argument
678 sscreen->info.has_packed_math_16bit && in si_lower_nir()
679 sscreen->b.get_shader_param(&sscreen->b, PIPE_SHADER_FRAGMENT, PIPE_SHADER_CAP_FP16)) in si_lower_nir()
682 si_nir_opts(sscreen, nir, true); in si_lower_nir()
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Dsi_pipe.h1316 void si_init_resource_fields(struct si_screen *sscreen, struct si_resource *res, uint64_t size,
1318 bool si_alloc_resource(struct si_screen *sscreen, struct si_resource *res);
1325 void si_init_screen_buffer_functions(struct si_screen *sscreen);
1330 bool vi_alpha_is_on_msb(struct si_screen *sscreen, enum pipe_format format);
1412 void si_screen_clear_buffer(struct si_screen *sscreen, struct pipe_resource *dst, uint64_t offset,
1429 void si_init_screen_get_functions(struct si_screen *sscreen);
1440 void si_gpu_load_kill_thread(struct si_screen *sscreen);
1441 uint64_t si_begin_counter(struct si_screen *sscreen, unsigned type);
1442 unsigned si_end_counter(struct si_screen *sscreen, unsigned type, uint64_t begin);
1469 void si_initialize_prim_discard_tunables(struct si_screen *sscreen, bool is_aux_context,
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Dsi_query.c578 void si_query_buffer_destroy(struct si_screen *sscreen, struct si_query_buffer *buffer) in si_query_buffer_destroy() argument
711 static void si_query_hw_add_result(struct si_screen *sscreen, struct si_query_hw *, void *buffer,
723 static struct pipe_query *si_query_hw_create(struct si_screen *sscreen, unsigned query_type, in si_query_hw_create() argument
738 query->result_size = 16 * sscreen->info.num_render_backends; in si_query_hw_create()
740 query->b.num_cs_dw_suspend = 6 + si_cp_write_fence_dwords(sscreen); in si_query_hw_create()
748 query->b.num_cs_dw_suspend = 8 + si_cp_write_fence_dwords(sscreen); in si_query_hw_create()
752 query->b.num_cs_dw_suspend = 8 + si_cp_write_fence_dwords(sscreen); in si_query_hw_create()
773 query->b.num_cs_dw_suspend = 6 + si_cp_write_fence_dwords(sscreen); in si_query_hw_create()
1097 struct si_screen *sscreen = (struct si_screen *)ctx->screen; in si_create_query() local
1103 if (sscreen->use_ngg_streamout && in si_create_query()
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Dsi_clear.c37 static void si_alloc_separate_cmask(struct si_screen *sscreen, struct si_texture *tex) in si_alloc_separate_cmask() argument
46 si_aligned_buffer_create(&sscreen->b, SI_RESOURCE_FLAG_UNMAPPABLE, PIPE_USAGE_DEFAULT, in si_alloc_separate_cmask()
54 p_atomic_inc(&sscreen->compressed_colortex_counter); in si_alloc_separate_cmask()
91 bool vi_alpha_is_on_msb(struct si_screen *sscreen, enum pipe_format format) in vi_alpha_is_on_msb() argument
100 if (sscreen->info.chip_class >= GFX10 && desc->nr_channels == 1) in vi_alpha_is_on_msb()
106 static bool vi_get_fast_clear_parameters(struct si_screen *sscreen, enum pipe_format base_format, in vi_get_fast_clear_parameters() argument
135 bool base_alpha_is_on_msb = vi_alpha_is_on_msb(sscreen, base_format); in vi_get_fast_clear_parameters()
136 bool surf_alpha_is_on_msb = vi_alpha_is_on_msb(sscreen, surface_format); in vi_get_fast_clear_parameters()
270 static void si_set_optimal_micro_tile_mode(struct si_screen *sscreen, struct si_texture *tex) in si_set_optimal_micro_tile_mode() argument
272 if (sscreen->info.chip_class >= GFX10 || tex->buffer.b.is_shared || in si_set_optimal_micro_tile_mode()
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Dsi_state.h487 void si_set_mutable_tex_desc_fields(struct si_screen *sscreen, struct si_texture *tex,
530 void si_init_screen_state_functions(struct si_screen *sscreen);
562 bool si_shader_cache_load_shader(struct si_screen *sscreen, unsigned char ir_sha1_cache_key[20],
564 void si_shader_cache_insert_shader(struct si_screen *sscreen, unsigned char ir_sha1_cache_key[20],
567 void si_init_screen_live_shader_cache(struct si_screen *sscreen);
569 bool si_init_shader_cache(struct si_screen *sscreen);
570 void si_destroy_shader_cache(struct si_screen *sscreen);
577 int si_shader_select_with_key(struct si_screen *sscreen, struct si_shader_ctx_state *state,
Dsi_shader.h829 bool si_compile_shader(struct si_screen *sscreen, struct ac_llvm_compiler *compiler,
831 bool si_create_shader_variant(struct si_screen *sscreen, struct ac_llvm_compiler *compiler,
836 bool si_shader_binary_upload(struct si_screen *sscreen, struct si_shader *shader,
838 void si_shader_dump(struct si_screen *sscreen, struct si_shader *shader,
842 void si_multiwave_lds_size_workaround(struct si_screen *sscreen, unsigned *lds_size);
847 struct si_shader *si_generate_gs_copy_shader(struct si_screen *sscreen,
854 void si_nir_opts(struct si_screen *sscreen, struct nir_shader *nir, bool first);
Dsi_dma_cs.c321 void si_screen_clear_buffer(struct si_screen *sscreen, struct pipe_resource *dst, uint64_t offset, in si_screen_clear_buffer() argument
324 struct si_context *ctx = (struct si_context *)sscreen->aux_context; in si_screen_clear_buffer()
326 simple_mtx_lock(&sscreen->aux_context_lock); in si_screen_clear_buffer()
328 sscreen->aux_context->flush(sscreen->aux_context, NULL, 0); in si_screen_clear_buffer()
329 simple_mtx_unlock(&sscreen->aux_context_lock); in si_screen_clear_buffer()
Dsi_state.c380 static void si_blend_check_commutativity(struct si_screen *sscreen, struct si_state_blend *blend, in si_blend_check_commutativity() argument
406 (func == PIPE_BLEND_ADD && sscreen->commutative_blend_add)) in si_blend_check_commutativity()
823 struct si_screen *sscreen = ((struct si_context *)ctx)->screen; in si_create_rs_state() local
915 S_028A48_ALTERNATE_RBS_PER_TILE(sscreen->info.chip_class >= GFX9)); in si_create_rs_state()
930 … S_028814_KEEP_TOGETHER_ENABLE(sscreen->info.chip_class >= GFX10 ? rs->polygon_mode_enabled : 0)); in si_create_rs_state()
1575 struct si_screen *sscreen = (struct si_screen *)screen; in si_translate_texformat() local
1579 assert(sscreen->info.chip_class <= GFX9); in si_translate_texformat()
1595 if (sscreen->info.chip_class <= GFX8) in si_translate_texformat()
1632 if (!sscreen->info.has_format_bc1_through_bc7) in si_translate_texformat()
1652 (sscreen->info.family == CHIP_STONEY || sscreen->info.family == CHIP_VEGA10 || in si_translate_texformat()
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Dsi_shader_llvm.c70 bool si_compile_llvm(struct si_screen *sscreen, struct si_shader_binary *binary, in si_compile_llvm() argument
75 unsigned count = p_atomic_inc_return(&sscreen->num_compilations); in si_compile_llvm()
77 if (si_can_dump_shader(sscreen, stage)) { in si_compile_llvm()
80 if (!(sscreen->debug_flags & (DBG(NO_IR) | DBG(PREOPT_IR)))) { in si_compile_llvm()
87 if (sscreen->record_llvm_ir) { in si_compile_llvm()
116 .info = &sscreen->info, in si_compile_llvm()
124 bool ok = ac_rtld_read_config(&sscreen->info, &rtld, conf); in si_compile_llvm()
129 void si_llvm_context_init(struct si_shader_context *ctx, struct si_screen *sscreen, in si_llvm_context_init() argument
133 ctx->screen = sscreen; in si_llvm_context_init()
136 ac_llvm_context_init(&ctx->ac, compiler, sscreen->info.chip_class, sscreen->info.family, in si_llvm_context_init()
Dsi_state_draw.c322 static unsigned si_get_init_multi_vgt_param(struct si_screen *sscreen, union si_vgt_param_key *key) in si_get_init_multi_vgt_param() argument
340 if ((sscreen->info.family == CHIP_TAHITI || sscreen->info.family == CHIP_PITCAIRN || in si_get_init_multi_vgt_param()
341 sscreen->info.family == CHIP_BONAIRE) && in si_get_init_multi_vgt_param()
346 if (sscreen->info.has_distributed_tess) { in si_get_init_multi_vgt_param()
348 if (sscreen->info.chip_class == GFX8) in si_get_init_multi_vgt_param()
357 if (key->u.line_stipple_enabled || (sscreen->debug_flags & DBG(SWITCH_ON_EOP))) { in si_get_init_multi_vgt_param()
362 if (sscreen->info.chip_class >= GFX7) { in si_get_init_multi_vgt_param()
370 if (sscreen->info.max_se <= 2 || key->u.prim == PIPE_PRIM_POLYGON || in si_get_init_multi_vgt_param()
374 (sscreen->info.family < CHIP_POLARIS10 || in si_get_init_multi_vgt_param()
383 if (sscreen->info.family == CHIP_HAWAII && key->u.uses_instancing) in si_get_init_multi_vgt_param()
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Dsi_test_dma.c121 static const char *array_mode_to_string(struct si_screen *sscreen, struct radeon_surf *surf) in array_mode_to_string() argument
123 if (sscreen->info.chip_class >= GFX9) { in array_mode_to_string()
169 void si_test_dma(struct si_screen *sscreen) in si_test_dma() argument
171 struct pipe_screen *screen = &sscreen->b; in si_test_dma()
284 array_mode_to_string(sscreen, &sdst->surface), tsrc.width0, tsrc.height0, in si_test_dma()
285 tsrc.array_size, array_mode_to_string(sscreen, &ssrc->surface), in si_test_dma()
Dsi_compute_prim_discard.c188 void si_initialize_prim_discard_tunables(struct si_screen *sscreen, bool is_aux_context, in si_initialize_prim_discard_tunables() argument
194 if (sscreen->info.chip_class == GFX6 || /* SI support is not implemented */ in si_initialize_prim_discard_tunables()
195 !sscreen->info.has_gds_ordered_append || sscreen->debug_flags & DBG(NO_PD) || is_aux_context) in si_initialize_prim_discard_tunables()
201 if (sscreen->debug_flags & DBG(ALWAYS_PD) || sscreen->debug_flags & DBG(PD) || in si_initialize_prim_discard_tunables()
202 (enable_on_pro_graphics_by_default && sscreen->info.is_pro_graphics && in si_initialize_prim_discard_tunables()
203 (sscreen->info.family == CHIP_BONAIRE || sscreen->info.family == CHIP_HAWAII || in si_initialize_prim_discard_tunables()
204 sscreen->info.family == CHIP_TONGA || sscreen->info.family == CHIP_FIJI || in si_initialize_prim_discard_tunables()
205 sscreen->info.family == CHIP_POLARIS10 || sscreen->info.family == CHIP_POLARIS11 || in si_initialize_prim_discard_tunables()
206 sscreen->info.family == CHIP_VEGA10 || sscreen->info.family == CHIP_VEGA20))) { in si_initialize_prim_discard_tunables()
209 if (sscreen->debug_flags & DBG(ALWAYS_PD)) in si_initialize_prim_discard_tunables()
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Dsi_fence.c377 struct si_screen *sscreen = (struct si_screen *)ctx->screen; in si_create_fence_fd() local
378 struct radeon_winsys *ws = sscreen->ws; in si_create_fence_fd()
389 if (!sscreen->info.has_fence_to_handle) in si_create_fence_fd()
396 if (!sscreen->info.has_syncobj) in si_create_fence_fd()
417 struct si_screen *sscreen = (struct si_screen *)screen; in si_fence_get_fd() local
418 struct radeon_winsys *ws = sscreen->ws; in si_fence_get_fd()
422 if (!sscreen->info.has_fence_to_handle) in si_fence_get_fd()
Dsi_shader_llvm_gs.c423 struct si_shader *si_generate_gs_copy_shader(struct si_screen *sscreen, in si_generate_gs_copy_shader() argument
446 si_llvm_context_init(&ctx, sscreen, compiler, in si_generate_gs_copy_shader()
447 si_get_wave_size(sscreen, MESA_SHADER_VERTEX, in si_generate_gs_copy_shader()
466 if (!sscreen->use_ngg_streamout && gs_selector->so.num_outputs) in si_generate_gs_copy_shader()
521 if (!sscreen->use_ngg_streamout && gs_selector->so.num_outputs) { in si_generate_gs_copy_shader()
539 if (si_compile_llvm(sscreen, &ctx.shader->binary, &ctx.shader->config, ctx.compiler, &ctx.ac, in si_generate_gs_copy_shader()
541 if (si_can_dump_shader(sscreen, MESA_SHADER_GEOMETRY)) in si_generate_gs_copy_shader()
543 si_shader_dump(sscreen, ctx.shader, debug, stderr, true); in si_generate_gs_copy_shader()
546 ok = si_shader_binary_upload(sscreen, ctx.shader, 0); in si_generate_gs_copy_shader()
557 si_fix_resource_usage(sscreen, shader); in si_generate_gs_copy_shader()
/external/mesa3d/src/gallium/drivers/radeon/
Dradeon_vce.c219 struct si_screen *sscreen = (struct si_screen *)enc->screen; in si_vce_frame_offset() local
222 if (sscreen->info.chip_class < GFX9) { in si_vce_frame_offset()
383 struct si_screen *sscreen = (struct si_screen *)context->screen; in si_vce_create_encoder() local
390 if (!sscreen->info.vce_fw_version) { in si_vce_create_encoder()
394 } else if (!si_vce_is_fw_version_supported(sscreen)) { in si_vce_create_encoder()
403 if (sscreen->info.is_amdgpu) in si_vce_create_encoder()
405 if ((!sscreen->info.is_amdgpu && sscreen->info.drm_minor >= 42) || sscreen->info.is_amdgpu) in si_vce_create_encoder()
407 if (sscreen->info.family >= CHIP_TONGA && sscreen->info.family != CHIP_STONEY && in si_vce_create_encoder()
408 sscreen->info.family != CHIP_POLARIS11 && sscreen->info.family != CHIP_POLARIS12 && in si_vce_create_encoder()
409 sscreen->info.family != CHIP_VEGAM) in si_vce_create_encoder()
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Dradeon_uvd_enc.c268 struct si_screen *sscreen = (struct si_screen *)context->screen; in radeon_uvd_create_encoder() local
275 if (!si_radeon_uvd_enc_supported(sscreen)) { in radeon_uvd_create_encoder()
325 cpb_size = (sscreen->info.chip_class < GFX9) in radeon_uvd_create_encoder()
354 bool si_radeon_uvd_enc_supported(struct si_screen *sscreen) in si_radeon_uvd_enc_supported() argument
356 return (sscreen->info.uvd_enc_supported); in si_radeon_uvd_enc_supported()

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