| /external/llvm-project/llvm/test/CodeGen/ARM/ |
| D | acle-intrinsics.ll | 114 define i32 @ssub8(i32 %a, i32 %b) nounwind {
115 ; CHECK-LABEL: ssub8
116 ; CHECK: ssub8 r0, r0, r1
117 %tmp = call i32 @llvm.arm.ssub8(i32 %a, i32 %b)
437 declare i32 @llvm.arm.ssub8(i32, i32) nounwind
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| /external/vixl/test/aarch32/ |
| D | test-assembler-cond-rd-rn-rm-t32.cc | 98 M(ssub8) \
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| D | test-assembler-cond-rd-rn-rm-a32.cc | 99 M(ssub8) \
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| /external/llvm-project/llvm/test/tools/llvm-mca/ARM/ |
| D | m7-int.s | 300 ssub8 r0, r1, r2 label
731 # CHECK-NEXT: 1 1 1.00 * * U ssub8 r0, r1, r2
1171 ….50 - - - - 1.00 - - - - - - ssub8 r0, r1, r2
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| D | m4-int.s | 309 ssub8 r0, r1, r2 label
755 # CHECK-NEXT: 1 1 1.00 * * U ssub8 r0, r1, r2
1193 # CHECK-NEXT: 1.00 ssub8 r0, r1, r2
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| D | cortex-a57-basic-instructions.s | 670 ssub8 r9, r2, r4
1540 # CHECK-NEXT: 2 2 1.00 * * U ssub8 r9, r2, r4
2417 # CHECK-NEXT: - 0.50 0.50 - 1.00 - - - ssub8 r9, r2, r4
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| /external/capstone/suite/MC/ARM/ |
| D | basic-thumb2-instructions.s.cs | 834 0xc2,0xfa,0x04,0xf9 = ssub8 r9, r2, r4
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| D | basic-arm-instructions.s.cs | 762 0xf4,0x9f,0x12,0xe6 = ssub8 r9, r2, r4
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| /external/vixl/src/aarch32/ |
| D | assembler-aarch32.h | 3259 void ssub8(Condition cond, Register rd, Register rn, Register rm);
3260 void ssub8(Register rd, Register rn, Register rm) { ssub8(al, rd, rn, rm); } in ssub8() function
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| D | disasm-aarch32.h | 1195 void ssub8(Condition cond, Register rd, Register rn, Register rm);
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| /external/llvm-project/llvm/test/MC/ARM/ |
| D | basic-arm-instructions.s | 2767 ssub8 r9, r2, r4
2772 @ CHECK: ssub8 r9, r2, r4 @ encoding: [0xf4,0x9f,0x12,0xe6]
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| D | basic-thumb2-instructions.s | 2843 ssub8 r9, r2, r4
2849 @ CHECK: ssub8 r9, r2, r4 @ encoding: [0xc2,0xfa,0x04,0xf9]
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| /external/llvm/test/MC/ARM/ |
| D | basic-arm-instructions.s | 2737 ssub8 r9, r2, r4
2742 @ CHECK: ssub8 r9, r2, r4 @ encoding: [0xf4,0x9f,0x12,0xe6]
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| D | basic-thumb2-instructions.s | 2634 ssub8 r9, r2, r4
2640 @ CHECK: ssub8 r9, r2, r4 @ encoding: [0xc2,0xfa,0x04,0xf9]
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| /external/llvm-project/llvm/test/MC/Disassembler/ARM/ |
| D | basic-arm-instructions.txt | 1900 # CHECK: ssub8 r9, r2, r4
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| /external/llvm/test/MC/Disassembler/ARM/ |
| D | basic-arm-instructions.txt | 1900 # CHECK: ssub8 r9, r2, r4
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| /external/capstone/arch/AArch64/ |
| D | ARMMappingInsnOp.inc | 883 { /* ARM_SSUB8, ARM_INS_SSUB8: ssub8${p} $rd, $rn, $rm */
6097 { /* ARM_t2SSUB8, ARM_INS_SSUB8: ssub8${p} $rd, $rn, $rm */
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| /external/capstone/arch/ARM/ |
| D | ARMMappingInsnOp.inc | 883 { /* ARM_SSUB8, ARM_INS_SSUB8: ssub8${p} $rd, $rn, $rm */
6097 { /* ARM_t2SSUB8, ARM_INS_SSUB8: ssub8${p} $rd, $rn, $rm */
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| /external/llvm/lib/Target/ARM/ |
| D | ARMInstrThumb2.td | 2165 def t2SSUB8 : T2I_pam<0b100, 0b0000, "ssub8">;
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| D | ARMInstrInfo.td | 3594 def SSUB8 : AAI<0b01100001, 0b11111111, "ssub8">;
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMInstrThumb2.td | 2468 def t2SSUB8 : T2I_pam_intrinsics<0b100, 0b0000, "ssub8", int_arm_ssub8>;
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| D | ARMInstrInfo.td | 3819 def SSUB8 : AAIIntrinsic<0b01100001, 0b11111111, "ssub8", int_arm_ssub8>;
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| /external/llvm-project/llvm/lib/Target/ARM/ |
| D | ARMInstrThumb2.td | 2517 def t2SSUB8 : T2I_pam_intrinsics<0b100, 0b0000, "ssub8", int_arm_ssub8>;
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| D | ARMInstrInfo.td | 3952 def SSUB8 : AAIIntrinsic<0b01100001, 0b11111111, "ssub8", int_arm_ssub8>;
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| /external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/ARM/ |
| D | ARMGenAsmMatcher.inc | 9907 "srsia\005srsib\004ssat\006ssat16\004ssax\004ssbb\006ssub16\005ssub8\003"
11221 …{ 1448 /* ssub8 */, ARM::t2SSUB8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_Has…
11222 …{ 1448 /* ssub8 */, ARM::SSUB8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_C…
|