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Searched refs:stcl (Results 1 – 25 of 28) sorted by relevance

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/external/llvm-project/llvm/test/CodeGen/ARM/
Dintrinsics-coprocessor.ll31 ; CHECK: stcl p7, c3, [r{{[0-9]+}}]
32 tail call void @llvm.arm.stcl(i32 7, i32 3, i8* %i) nounwind
54 declare void @llvm.arm.stcl(i32, i32, i8*) nounwind
/external/llvm/test/CodeGen/ARM/
Dintrinsics-coprocessor.ll32 ; CHECK: stcl p7, c3, [r{{[0-9]+}}]
33 tail call void @llvm.arm.stcl(i32 7, i32 3, i8* %i) nounwind
55 declare void @llvm.arm.stcl(i32, i32, i8*) nounwind
/external/llvm-project/llvm/test/CodeGen/Thumb2/
Dintrinsics-coprocessor.ll30 ; CHECK: stcl p7, c3, [r{{[0-9]+}}]
31 tail call void @llvm.arm.stcl(i32 7, i32 3, i8* %i) nounwind
69 declare void @llvm.arm.stcl(i32, i32, i8*) nounwind
/external/clang/test/CodeGen/
Dbuiltins-arm.c124 void stcl(void *i) { in stcl() function
/external/llvm-project/clang/test/CodeGen/
Dbuiltins-arm.c139 void stcl(void *i) { in stcl() function
/external/capstone/suite/MC/ARM/
Dbasic-thumb2-instructions.s.cs856 0xc6,0xed,0x01,0xa3 = stcl p3, c10, [r6, #4]
857 0xc7,0xed,0x00,0xb2 = stcl p2, c11, [r7]
858 0x48,0xed,0x38,0xc1 = stcl p1, c12, [r8, #-224]
859 0x69,0xed,0x1e,0xd0 = stcl p0, c13, [r9, #-120]!
860 0xea,0xec,0x04,0xe6 = stcl p6, c14, [r10], #16
861 0x6b,0xec,0x12,0xf7 = stcl p7, c15, [r11], #-72
Dbasic-arm-instructions.s.cs782 0x01,0xa3,0xc6,0xed = stcl p3, c10, [r6, #4]
783 0x00,0xb2,0xc7,0xed = stcl p2, c11, [r7]
784 0x38,0xc1,0x48,0xed = stcl p1, c12, [r8, #-224]
785 0x1e,0xd0,0x69,0xed = stcl p0, c13, [r9, #-120]!
786 0x04,0xe6,0xea,0xec = stcl p6, c14, [r10], #16
787 0x12,0xf7,0x6b,0xec = stcl p7, c15, [r11], #-72
/external/llvm-project/llvm/test/MC/ARM/
Dbasic-arm-instructions.s2797 stcl p3, c10, [r6, #4]
2798 stcl p2, c11, [r7]
2799 stcl p1, c12, [r8, #-224]
2800 stcl p0, c13, [r9, #-120]!
2801 stcl p6, c14, [r10], #16
2802 stcl p7, c15, [r11], #-72
2838 @ CHECK: stcl p3, c10, [r6, #4] @ encoding: [0x01,0xa3,0xc6,0xed]
2839 @ CHECK: stcl p2, c11, [r7] @ encoding: [0x00,0xb2,0xc7,0xed]
2840 @ CHECK: stcl p1, c12, [r8, #-224] @ encoding: [0x38,0xc1,0x48,0xed]
2841 @ CHECK: stcl p0, c13, [r9, #-120]! @ encoding: [0x1e,0xd0,0x69,0xed]
[all …]
Dbasic-thumb2-instructions.s2877 stcl p3, c10, [r6, #4]
2878 stcl p2, c11, [r7]
2879 stcl p1, c12, [r8, #-224]
2880 stcl p0, c13, [r9, #-120]!
2881 stcl p6, c14, [r10], #16
2882 stcl p7, c15, [r11], #-72
2905 @ CHECK: stcl p3, c10, [r6, #4] @ encoding: [0xc6,0xed,0x01,0xa3]
2906 @ CHECK: stcl p2, c11, [r7] @ encoding: [0xc7,0xed,0x00,0xb2]
2907 @ CHECK: stcl p1, c12, [r8, #-224] @ encoding: [0x48,0xed,0x38,0xc1]
2908 @ CHECK: stcl p0, c13, [r9, #-120]! @ encoding: [0x69,0xed,0x1e,0xd0]
[all …]
/external/llvm/test/MC/ARM/
Dbasic-arm-instructions.s2767 stcl p3, c10, [r6, #4]
2768 stcl p2, c11, [r7]
2769 stcl p1, c12, [r8, #-224]
2770 stcl p0, c13, [r9, #-120]!
2771 stcl p6, c14, [r10], #16
2772 stcl p7, c15, [r11], #-72
2808 @ CHECK: stcl p3, c10, [r6, #4] @ encoding: [0x01,0xa3,0xc6,0xed]
2809 @ CHECK: stcl p2, c11, [r7] @ encoding: [0x00,0xb2,0xc7,0xed]
2810 @ CHECK: stcl p1, c12, [r8, #-224] @ encoding: [0x38,0xc1,0x48,0xed]
2811 @ CHECK: stcl p0, c13, [r9, #-120]! @ encoding: [0x1e,0xd0,0x69,0xed]
[all …]
Dbasic-thumb2-instructions.s2668 stcl p3, c10, [r6, #4]
2669 stcl p2, c11, [r7]
2670 stcl p1, c12, [r8, #-224]
2671 stcl p0, c13, [r9, #-120]!
2672 stcl p6, c14, [r10], #16
2673 stcl p7, c15, [r11], #-72
2696 @ CHECK: stcl p3, c10, [r6, #4] @ encoding: [0xc6,0xed,0x01,0xa3]
2697 @ CHECK: stcl p2, c11, [r7] @ encoding: [0xc7,0xed,0x00,0xb2]
2698 @ CHECK: stcl p1, c12, [r8, #-224] @ encoding: [0x48,0xed,0x38,0xc1]
2699 @ CHECK: stcl p0, c13, [r9, #-120]! @ encoding: [0x69,0xed,0x1e,0xd0]
[all …]
/external/llvm-project/llvm/test/MC/Disassembler/ARM/
Darm-tests.txt278 # CHECK: stcl p13, c12, [r9, #0]!
/external/llvm/test/MC/Disassembler/ARM/
Darm-tests.txt278 # CHECK: stcl p13, c12, [r9, #0]!
/external/capstone/arch/AArch64/
DARMMappingInsnOp.inc910 { /* ARM_STCL_OFFSET, ARM_INS_STCL: stcl${p} $cop, $crd, $addr */
913 { /* ARM_STCL_OPTION, ARM_INS_STCL: stcl${p} $cop, $crd, $addr, $option */
916 { /* ARM_STCL_POST, ARM_INS_STCL: stcl${p} $cop, $crd, $addr, $offset */
919 { /* ARM_STCL_PRE, ARM_INS_STCL: stcl${p} $cop, $crd, $addr! */
6124 { /* ARM_t2STCL_OFFSET, ARM_INS_STCL: stcl${p} $cop, $crd, $addr */
6127 { /* ARM_t2STCL_OPTION, ARM_INS_STCL: stcl${p} $cop, $crd, $addr, $option */
6130 { /* ARM_t2STCL_POST, ARM_INS_STCL: stcl${p} $cop, $crd, $addr, $offset */
6133 { /* ARM_t2STCL_PRE, ARM_INS_STCL: stcl${p} $cop, $crd, $addr! */
/external/capstone/arch/ARM/
DARMMappingInsnOp.inc910 { /* ARM_STCL_OFFSET, ARM_INS_STCL: stcl${p} $cop, $crd, $addr */
913 { /* ARM_STCL_OPTION, ARM_INS_STCL: stcl${p} $cop, $crd, $addr, $option */
916 { /* ARM_STCL_POST, ARM_INS_STCL: stcl${p} $cop, $crd, $addr, $offset */
919 { /* ARM_STCL_PRE, ARM_INS_STCL: stcl${p} $cop, $crd, $addr! */
6124 { /* ARM_t2STCL_OFFSET, ARM_INS_STCL: stcl${p} $cop, $crd, $addr */
6127 { /* ARM_t2STCL_OPTION, ARM_INS_STCL: stcl${p} $cop, $crd, $addr, $option */
6130 { /* ARM_t2STCL_POST, ARM_INS_STCL: stcl${p} $cop, $crd, $addr, $offset */
6133 { /* ARM_t2STCL_PRE, ARM_INS_STCL: stcl${p} $cop, $crd, $addr! */
/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/ARM/
DARMGenAsmMatcher.inc9908 "stc\004stc2\005stc2l\004stcl\003stl\004stlb\005stlex\006stlexb\006stlex"
11247 …{ 1469 /* stcl */, ARM::STCL_OFFSET, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_…
11248 …{ 1469 /* stcl */, ARM::t2STCL_OFFSET, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode…
11249 …{ 1469 /* stcl */, ARM::STCL_PRE, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, …
11250 …{ 1469 /* stcl */, ARM::t2STCL_PRE, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0…
11251 …{ 1469 /* stcl */, ARM::STCL_OPTION, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__CoprocOp…
11252 …{ 1469 /* stcl */, ARM::t2STCL_OPTION, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__Coproc…
11253 …{ 1469 /* stcl */, ARM::STCL_POST, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__PostIdxImm…
11254 …{ 1469 /* stcl */, ARM::t2STCL_POST, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__PostIdxI…
15637 { 1469 /* stcl */, 2 /* 1 */, MCK_CoprocNum, AMFBS_IsARM },
[all …]
/external/llvm/lib/Target/ARM/
DARMInstrThumb2.td4015 defm t2STCL : t2LdStCop<0b1110, 0, 1, "stcl", [(int_arm_stcl imm:$cop, imm:$CRd, addrmode5:$addr)]…
DARMInstrInfo.td5019 defm STCL : LdStCop <0, 1, "stcl", [(int_arm_stcl imm:$cop, imm:$CRd, addrmode5:$addr)]>;
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DARMInstrThumb2.td4248 defm t2STCL : t2LdStCop<0b1110, 0, 1, "stcl", [(int_arm_stcl timm:$cop, timm:$CRd, addrmode5:$addr…
DARMInstrInfo.td5370 defm STCL : LdStCop <0, 1, "stcl", [(int_arm_stcl timm:$cop, timm:$CRd, addrmode5:$addr)]>;
/external/llvm-project/llvm/lib/Target/ARM/
DARMInstrThumb2.td4317 defm t2STCL : t2LdStCop<0b1110, 0, 1, "stcl", [(int_arm_stcl timm:$cop, timm:$CRd, addrmode5:$addr…
DARMInstrInfo.td5520 defm STCL : LdStCop <0, 1, "stcl", [(int_arm_stcl timm:$cop, timm:$CRd, addrmode5:$addr)]>;
/external/swiftshader/third_party/llvm-subzero/build/Android/include/llvm/IR/
DIntrinsics.gen689 arm_stcl, // llvm.arm.stcl
6747 "llvm.arm.stcl",
14687 3, // llvm.arm.stcl
/external/swiftshader/third_party/llvm-subzero/build/Linux/include/llvm/IR/
DIntrinsics.gen689 arm_stcl, // llvm.arm.stcl
6747 "llvm.arm.stcl",
14687 3, // llvm.arm.stcl
/external/swiftshader/third_party/llvm-subzero/build/Windows/include/llvm/IR/
DIntrinsics.gen689 arm_stcl, // llvm.arm.stcl
6747 "llvm.arm.stcl",
14687 3, // llvm.arm.stcl

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