| /external/llvm/test/MC/ARM/ |
| D | load-store-acquire-release-v8-thumb.s | 41 stlb r2, [r1]
44 @ CHECK: stlb r2, [r1] @ encoding: [0xc1,0xe8,0x8f,0x2f]
|
| D | load-store-acquire-release-v8.s | 41 stlb r2, [r1]
44 @ CHECK: stlb r2, [r1] @ encoding: [0x92,0xfc,0xc1,0xe1]
|
| D | thumbv8m.s | 112 stlb r1, [r3] label
|
| /external/llvm-project/llvm/test/MC/ARM/ |
| D | load-store-acquire-release-v8-thumb.s | 41 stlb r2, [r1]
44 @ CHECK: stlb r2, [r1] @ encoding: [0xc1,0xe8,0x8f,0x2f]
|
| D | load-store-acquire-release-v8.s | 41 stlb r2, [r1]
44 @ CHECK: stlb r2, [r1] @ encoding: [0x92,0xfc,0xc1,0xe1]
|
| D | thumbv8m.s | 112 stlb r1, [r3] label
|
| /external/capstone/suite/MC/ARM/ |
| D | load-store-acquire-release-v8.s.cs | 14 0x92,0xfc,0xc1,0xe1 = stlb r2, [r1]
|
| D | load-store-acquire-release-v8-thumb.s.cs | 14 0xc1,0xe8,0x8f,0x2f = stlb r2, [r1]
|
| /external/llvm-project/llvm/test/MC/Disassembler/ARM/ |
| D | load-store-acquire-release-v8.txt | 31 # CHECK: stlb r2, [r1] @ encoding: [0x92,0xfc,0xc1,0xe1]
|
| D | load-store-acquire-release-v8-thumb.txt | 32 # CHECK: stlb r2, [r1] @ encoding: [0xc1,0xe8,0x8f,0x2f]
|
| /external/llvm/test/MC/Disassembler/ARM/ |
| D | load-store-acquire-release-v8-thumb.txt | 32 # CHECK: stlb r2, [r1] @ encoding: [0xc1,0xe8,0x8f,0x2f]
|
| D | load-store-acquire-release-v8.txt | 31 # CHECK: stlb r2, [r1] @ encoding: [0x92,0xfc,0xc1,0xe1]
|
| /external/llvm-project/llvm/test/CodeGen/ARM/ |
| D | atomic-ops-m33.ll | 110 ; CHECK: stlb r0, [r1]
|
| D | atomic-ops-v8.ll | 1323 ; CHECK: stlb r0, [r[[ADDR]]]
1340 ; CHECK: stlb r0, [r[[ADDR]]]
|
| /external/llvm/test/CodeGen/ARM/ |
| D | atomic-ops-v8.ll | 1320 ; CHECK: stlb r0, [r[[ADDR]]]
1337 ; CHECK: stlb r0, [r[[ADDR]]]
|
| /external/vixl/src/aarch32/ |
| D | assembler-aarch32.h | 3265 void stlb(Condition cond, Register rt, const MemOperand& operand);
3266 void stlb(Register rt, const MemOperand& operand) { stlb(al, rt, operand); } in stlb() function
|
| D | disasm-aarch32.h | 1199 void stlb(Condition cond, Register rt, const MemOperand& operand);
|
| /external/capstone/arch/AArch64/ |
| D | ARMMappingInsnOp.inc | 937 { /* ARM_STLB, ARM_INS_STLB: stlb${p} $rt, $addr */
6151 { /* ARM_t2STLB, ARM_INS_STLB: stlb${p} $rt, $addr */
|
| /external/capstone/arch/ARM/ |
| D | ARMMappingInsnOp.inc | 937 { /* ARM_STLB, ARM_INS_STLB: stlb${p} $rt, $addr */
6151 { /* ARM_t2STLB, ARM_INS_STLB: stlb${p} $rt, $addr */
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMInstrThumb2.td | 1605 "stlb", "\t$Rt, $addr", []>;
|
| D | ARMInstrInfo.td | 3118 NoItinerary, "stlb", "\t$Rt, $addr", []>;
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMInstrThumb2.td | 1799 "stlb", "\t$Rt, $addr", []>;
|
| /external/llvm-project/llvm/lib/Target/ARM/ |
| D | ARMInstrThumb2.td | 1802 "stlb", "\t$Rt, $addr", []>;
|
| D | ARMInstrInfo.td | 3409 NoItinerary, "stlb", "\t$Rt, $addr", []>;
|
| /external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/ARM/ |
| D | ARMGenAsmMatcher.inc | 9908 "stc\004stc2\005stc2l\004stcl\003stl\004stlb\005stlex\006stlexb\006stlex"
11257 …{ 1478 /* stlb */, ARM::t2STLB, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, AMFBS_IsThumb_HasAcq…
11258 …{ 1478 /* stlb */, ARM::STLB, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, AMFBS_IsARM_HasAcquire…
|