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Searched refs:sxtb (Results 1 – 25 of 213) sorted by relevance

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/external/llvm-project/llvm/test/MC/AArch64/SVE/
Dsxtb.s10 sxtb z0.h, p0/m, z0.h label
16 sxtb z0.s, p0/m, z0.s label
22 sxtb z0.d, p0/m, z0.d label
28 sxtb z31.h, p7/m, z31.h label
34 sxtb z31.s, p7/m, z31.s label
40 sxtb z31.d, p7/m, z31.d label
56 sxtb z4.d, p7/m, z31.d label
68 sxtb z4.d, p7/m, z31.d label
Dsxtb-diagnostics.s4 sxtb z0.d, p0/m, z0.s label
10 sxtb z29.d, p7, z29.d label
19 sxtb z0.b, p0/m, z0.b label
28 sxtb z0.h, p8/m, z0.h label
33 sxtb z0.s, p8/m, z0.s label
38 sxtb z0.d, p8/m, z0.d label
/external/llvm-project/llvm/test/CodeGen/Thumb2/
Dmve-div-expand.ll422 ; CHECK-NEXT: sxtb r0, r0
423 ; CHECK-NEXT: sxtb r1, r1
427 ; CHECK-NEXT: sxtb r2, r2
428 ; CHECK-NEXT: sxtb r1, r1
438 ; CHECK-NEXT: sxtb r1, r1
439 ; CHECK-NEXT: sxtb r0, r0
441 ; CHECK-NEXT: sxtb.w r12, r2
442 ; CHECK-NEXT: sxtb.w lr, r3
445 ; CHECK-NEXT: sxtb r4, r4
446 ; CHECK-NEXT: sxtb r5, r5
[all …]
Dmve-vecreduce-mla.ll648 ; CHECK-NEXT: sxtb r0, r0
649 ; CHECK-NEXT: sxtb r1, r1
655 ; CHECK-NEXT: sxtb r0, r0
656 ; CHECK-NEXT: sxtb r1, r1
667 ; CHECK-NEXT: sxtb r1, r1
668 ; CHECK-NEXT: sxtb r3, r3
674 ; CHECK-NEXT: sxtb r1, r1
675 ; CHECK-NEXT: sxtb r3, r3
688 ; CHECK-NEXT: sxtb r2, r2
689 ; CHECK-NEXT: sxtb r3, r3
[all …]
Dmve-vecreduce-add.ll503 ; CHECK-NEXT: sxtb r0, r0
508 ; CHECK-NEXT: sxtb r0, r0
518 ; CHECK-NEXT: sxtb r1, r1
523 ; CHECK-NEXT: sxtb r1, r1
535 ; CHECK-NEXT: sxtb r2, r2
540 ; CHECK-NEXT: sxtb r2, r2
552 ; CHECK-NEXT: sxtb r2, r2
557 ; CHECK-NEXT: sxtb r2, r2
569 ; CHECK-NEXT: sxtb r2, r2
574 ; CHECK-NEXT: sxtb r2, r2
[all …]
Dmve-vecreduce-mlapred.ll1027 ; CHECK-NEXT: sxtb r2, r2
1065 ; CHECK-NEXT: sxtb r1, r1
1071 ; CHECK-NEXT: sxtb r1, r1
1072 ; CHECK-NEXT: sxtb r2, r2
1091 ; CHECK-NEXT: sxtb r3, r3
1094 ; CHECK-NEXT: sxtb r0, r0
1100 ; CHECK-NEXT: sxtb r0, r0
1101 ; CHECK-NEXT: sxtb r3, r3
1123 ; CHECK-NEXT: sxtb r0, r0
1135 ; CHECK-NEXT: sxtb r3, r3
[all …]
/external/llvm-project/llvm/test/CodeGen/Hexagon/
Dsignext-inreg.ll11 ; CHECK-NEXT: r0 = sxtb(r0)
20 ; CHECK-64B-NEXT: r0 = sxtb(r0)
29 ; CHECK-128B-NEXT: r0 = sxtb(r0)
45 ; CHECK-NEXT: r2 = sxtb(r2)
46 ; CHECK-NEXT: r4 = sxtb(r4)
55 ; CHECK-NEXT: r12 = sxtb(r12)
61 ; CHECK-NEXT: r8 = sxtb(r8)
67 ; CHECK-NEXT: r10 = sxtb(r10)
68 ; CHECK-NEXT: r14 = sxtb(r14)
74 ; CHECK-NEXT: r16 = sxtb(r16)
[all …]
Dbit-ext-sat.ll17 ; CHECK-NOT: sxtb
21 %1 = tail call i32 @llvm.hexagon.A2.sxtb(i32 %0)
46 declare i32 @llvm.hexagon.A2.sxtb(i32) #1
/external/llvm-project/llvm/test/CodeGen/ARM/
Dfast-isel-icmp.ll38 ; ARM: sxtb r0, r0
39 ; ARM: sxtb r1, r1
42 ; THUMB: sxtb r0, r0
43 ; THUMB: sxtb r1, r1
Dsxt_rot.ll6 ; CHECK-V6: sxtb r0, r0
7 ; CHECK-V7: sxtb r0, r0
15 ; CHECK-V6: sxtb r0, r0
/external/llvm/test/CodeGen/ARM/
Dfast-isel-icmp.ll38 ; ARM: sxtb r0, r0
39 ; ARM: sxtb r1, r1
42 ; THUMB: sxtb r0, r0
43 ; THUMB: sxtb r1, r1
Dsxt_rot.ll5 ; CHECK: sxtb r0, r0
13 ; CHECK: sxtb r0, r0
/external/llvm-project/llvm/test/CodeGen/AArch64/
Dsve-intrinsics-conversion.ll13 ; CHECK: sxtb z0.h, p0/m, z1.h
15 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.sxtb.nxv8i16(<vscale x 8 x i16> %a,
23 ; CHECK: sxtb z0.s, p0/m, z1.s
25 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.sxtb.nxv4i32(<vscale x 4 x i32> %a,
33 ; CHECK: sxtb z0.d, p0/m, z1.d
35 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.sxtb.nxv2i64(<vscale x 2 x i64> %a,
151 declare <vscale x 8 x i16> @llvm.aarch64.sve.sxtb.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i1>, <v…
152 declare <vscale x 4 x i32> @llvm.aarch64.sve.sxtb.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i1>, <v…
153 declare <vscale x 2 x i64> @llvm.aarch64.sve.sxtb.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i1>, <v…
Dsigned-truncation-check.ll24 ; CHECK-NEXT: sxtb w8, w0
50 ; CHECK-NEXT: cmp w0, w0, sxtb
86 ; CHECK-NEXT: cmp x0, w0, sxtb
102 ; CHECK-NEXT: sxtb w8, w0
126 ; CHECK-NEXT: cmp w0, w0, sxtb
159 ; CHECK-NEXT: cmp x0, w0, sxtb
171 ; CHECK-NEXT: sxtb w8, w0
188 ; CHECK-NEXT: sxtb w8, w0
212 ; CHECK-NEXT: cmp w0, w0, sxtb
245 ; CHECK-NEXT: cmp x0, w0, sxtb
[all …]
Dlack-of-signed-truncation-check.ll24 ; CHECK-NEXT: sxtb w8, w0
50 ; CHECK-NEXT: cmp w0, w0, sxtb
86 ; CHECK-NEXT: cmp x0, w0, sxtb
102 ; CHECK-NEXT: sxtb w8, w0
126 ; CHECK-NEXT: cmp w0, w0, sxtb
159 ; CHECK-NEXT: cmp x0, w0, sxtb
171 ; CHECK-NEXT: sxtb w8, w0
188 ; CHECK-NEXT: sxtb w8, w0
212 ; CHECK-NEXT: cmp w0, w0, sxtb
245 ; CHECK-NEXT: cmp x0, w0, sxtb
[all …]
Dshift-by-signext.ll10 ; CHECK-NEXT: sxtb w8, w1
20 ; CHECK-NEXT: sxtb w8, w1
30 ; CHECK-NEXT: sxtb w8, w1
112 ; CHECK-NEXT: sxtb w8, w1
Dfast-isel-int-ext2.ll81 ; CHECK-NOT: sxtb
109 ; CHECK-NOT: sxtb
222 ; CHECK-NOT: sxtb
250 ; CHECK-NOT: sxtb
368 ; CHECK-NOT: sxtb
398 ; CHECK-NOT: sxtb
/external/llvm-project/llvm/test/tools/llvm-mca/AArch64/Exynos/
Dextended-register.s6 sub w0, w1, w2, sxtb #0
49 # EM3-NEXT: 1 1 0.25 sub w0, w1, w2, sxtb
58 # EM4-NEXT: 1 1 0.25 sub w0, w1, w2, sxtb
67 # EM5-NEXT: 1 1 0.17 sub w0, w1, w2, sxtb
/external/llvm-project/llvm/test/MC/AArch64/
Darm64-arithmetic-encoding.s174 add w1, w2, w3, sxtb
183 ; CHECK: add w1, w2, w3, sxtb ; encoding: [0x41,0x80,0x23,0x0b]
191 add x1, x2, w3, sxtb
198 ; CHECK: add x1, x2, w3, sxtb ; encoding: [0x41,0x80,0x23,0x8b]
218 sub w1, w2, w3, sxtb
227 ; CHECK: sub w1, w2, w3, sxtb ; encoding: [0x41,0x80,0x23,0x4b]
235 sub x1, x2, w3, sxtb
242 ; CHECK: sub x1, x2, w3, sxtb ; encoding: [0x41,0x80,0x23,0xcb]
262 adds w1, w2, w3, sxtb
271 ; CHECK: adds w1, w2, w3, sxtb ; encoding: [0x41,0x80,0x23,0x2b]
[all …]
/external/llvm/test/MC/AArch64/
Darm64-arithmetic-encoding.s174 add w1, w2, w3, sxtb
183 ; CHECK: add w1, w2, w3, sxtb ; encoding: [0x41,0x80,0x23,0x0b]
191 add x1, x2, w3, sxtb
198 ; CHECK: add x1, x2, w3, sxtb ; encoding: [0x41,0x80,0x23,0x8b]
218 sub w1, w2, w3, sxtb
227 ; CHECK: sub w1, w2, w3, sxtb ; encoding: [0x41,0x80,0x23,0x4b]
235 sub x1, x2, w3, sxtb
242 ; CHECK: sub x1, x2, w3, sxtb ; encoding: [0x41,0x80,0x23,0xcb]
262 adds w1, w2, w3, sxtb
271 ; CHECK: adds w1, w2, w3, sxtb ; encoding: [0x41,0x80,0x23,0x2b]
[all …]
/external/llvm/test/CodeGen/AArch64/
Daddsub_ext.ll45 ; CHECK: add {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, sxtb
50 ; CHECK: add {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, sxtb #1
56 ; CHECK: add {{x[0-9]+}}, {{x[0-9]+}}, {{w[0-9]+}}, sxtb
61 ; CHECK: add {{x[0-9]+}}, {{x[0-9]+}}, {{w[0-9]+}}, sxtb #4
73 ; CHECK: cmp {{x[0-9]+}}, {{w[0-9]+}}, sxtb
120 ; CHECK: sub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, sxtb
125 ; CHECK: sub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, sxtb #1
131 ; CHECK: sub {{x[0-9]+}}, {{x[0-9]+}}, {{w[0-9]+}}, sxtb
136 ; CHECK: sub {{x[0-9]+}}, {{x[0-9]+}}, {{w[0-9]+}}, sxtb #4
Darm64-fast-isel-icmp.ll166 ; CHECK: sxtb w0, w0
167 ; CHECK-NEXT: cmp w0, w1, sxtb
187 ; CHECK: sxtb w0, w0
188 ; CHECK-NEXT: cmp w0, w1, sxtb
222 ; CHECK: sxtb w0, w0
Dfast-isel-int-ext2.ll81 ; CHECK-NOT: sxtb
109 ; CHECK-NOT: sxtb
222 ; CHECK-NOT: sxtb
250 ; CHECK-NOT: sxtb
368 ; CHECK-NOT: sxtb
398 ; CHECK-NOT: sxtb
/external/llvm/test/MC/ARM/
Dthumb.s25 sxtb r2, r3
27 @ CHECK: sxtb r2, r3 @ encoding: [0x5a,0xb2]
/external/llvm-project/llvm/test/MC/ARM/
Dthumb.s25 sxtb r2, r3
27 @ CHECK: sxtb r2, r3 @ encoding: [0x5a,0xb2]

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