Searched refs:sxth (Results 1 – 25 of 225) sorted by relevance
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4 sxth z0.d, p0/m, z0.s label10 sxth z29.d, p7, z29.d label19 sxth z0.b, p0/m, z0.b label24 sxth z0.h, p0/m, z0.h label33 sxth z0.s, p8/m, z0.s label38 sxth z0.d, p8/m, z0.d label
10 sxth z0.s, p0/m, z0.s label16 sxth z0.d, p0/m, z0.d label22 sxth z31.s, p7/m, z31.s label28 sxth z31.d, p7/m, z31.d label44 sxth z4.d, p7/m, z31.d label56 sxth z4.d, p7/m, z31.d label
9 ; CHECK-NOT: sxth30 ; CHECK-NOT: sxth53 ; CHECK-NOT: sxth65 ; CHECK-NOT: sxth92 ; CHECK-NOT: sxth134 ; CHECK-NOT: sxth160 ; CHECK-NOT: sxth171 ; CHECK-NOT: sxth183 ; CHECK-NOT: sxth195 ; CHECK-NOT: sxth[all …]
8 ; ARM: sxth r0, r09 ; ARM: sxth r1, r112 ; THUMB: sxth r0, r013 ; THUMB: sxth r1, r1
16 ; ARM-NEXT: sxth r2, r228 ; THUMBV6M-NEXT: sxth r2, r249 ; THUMBV8M-BASE-NEXT: sxth r2, r268 ; THUMB-NEXT: sxth r2, r2
106 ; THUMB: sxth110 ; ARM: sxth126 ; THUMB: sxth132 ; ARM: sxth
19 ; CHECK-NEXT: sxth r0, r071 ; T2-NEXT: sxth r0, r079 ; T1-NEXT: sxth r0, r0
38 ; CHECK: sxth r0, r055 ; CHECK-NOT: sxth
70 ; CHECKELF: sxth r0, {{r[0-9]+}}76 ; CHECKT2D: sxth r0, {{r[0-9]+}}164 ; CHECKELF: sxth r0, [[SAVEX]]171 ; CHECKT2D: sxth r0, [[SAVEX]]
17 %v13 = tail call i32 @llvm.hexagon.A2.sxth(i32 %v12)18 %v14 = tail call i32 @llvm.hexagon.A2.sxth(i32 2)19 %v15 = tail call i32 @llvm.hexagon.A2.sxth(i32 undef)21 %v17 = tail call i32 @llvm.hexagon.A2.sxth(i32 %v16)25 %v21 = tail call i32 @llvm.hexagon.A2.sxth(i32 %v20)29 %v25 = tail call i32 @llvm.hexagon.A2.sxth(i32 %v24)32 %v28 = tail call i32 @llvm.hexagon.A2.sxth(i32 %v27)45 %v40 = call i32 @llvm.hexagon.A2.sxth(i32 %v39)61 %v52 = call i32 @llvm.hexagon.A2.sxth(i32 %v51)68 %v57 = call i32 @llvm.hexagon.A2.sxth(i32 %v56)[all …]
7 ; CHECK-NOT: sxth11 %1 = tail call i32 @llvm.hexagon.A2.sxth(i32 %0)47 declare i32 @llvm.hexagon.A2.sxth(i32) #1
6 ; epilog stage. We check this by counting the number of sxth instructions.8 ; CHECK: r{{[0-9]+}} = sxth(r{{[0-9]+}})9 ; CHECK: r{{[0-9]+}} = sxth(r{{[0-9]+}})10 ; CHECK: r{{[0-9]+}} = sxth(r{{[0-9]+}})11 ; CHECK: r{{[0-9]+}} = sxth(r{{[0-9]+}})
30 ; CHECK: cmn x0, w1, sxth77 ; CHECK: cmn w0, w1, sxth101 ; CHECK: cmn x1, w0, sxth113 ; CHECK: cmn w1, w0, sxth125 ; CHECK: sxth w8, w1126 ; CHECK-NEXT: cmn w8, w0, sxth140 ; CHECK-NEXT: cmn w8, w0, sxth177 ; CHECK: sxth w8, w1228 ; CHECK: cmn x0, w1, sxth275 ; CHECK: cmn w0, w1, sxth[all …]
47 ; CHECK: sxth z0.s, p0/m, z1.s49 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.sxth.nxv4i32(<vscale x 4 x i32> %a,57 ; CHECK: sxth z0.d, p0/m, z1.d59 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.sxth.nxv2i64(<vscale x 2 x i64> %a,154 declare <vscale x 4 x i32> @llvm.aarch64.sve.sxth.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i1>, <v…155 declare <vscale x 2 x i64> @llvm.aarch64.sve.sxth.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i1>, <v…
7 add x3, x4, w5, sxth #150 # EM3-NEXT: 1 2 0.50 add x3, x4, w5, sxth #159 # EM4-NEXT: 1 2 0.50 add x3, x4, w5, sxth #168 # EM5-NEXT: 1 2 0.50 add x3, x4, w5, sxth #1
175 add w1, w2, w3, sxth184 ; CHECK: add w1, w2, w3, sxth ; encoding: [0x41,0xa0,0x23,0x0b]192 add x1, x2, w3, sxth199 ; CHECK: add x1, x2, w3, sxth ; encoding: [0x41,0xa0,0x23,0x8b]219 sub w1, w2, w3, sxth228 ; CHECK: sub w1, w2, w3, sxth ; encoding: [0x41,0xa0,0x23,0x4b]236 sub x1, x2, w3, sxth243 ; CHECK: sub x1, x2, w3, sxth ; encoding: [0x41,0xa0,0x23,0xcb]263 adds w1, w2, w3, sxth272 ; CHECK: adds w1, w2, w3, sxth ; encoding: [0x41,0xa0,0x23,0x2b][all …]
178 ; CHECK: add {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, sxth183 ; CHECK: add {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, sxth #1189 ; CHECK: add {{x[0-9]+}}, {{x[0-9]+}}, {{w[0-9]+}}, sxth194 ; CHECK: add {{x[0-9]+}}, {{x[0-9]+}}, {{w[0-9]+}}, sxth #4206 ; CHECK: cmp {{x[0-9]+}}, {{w[0-9]+}}, sxth253 ; CHECK: sub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, sxth258 ; CHECK: sub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, sxth #1264 ; CHECK: sub {{x[0-9]+}}, {{x[0-9]+}}, {{w[0-9]+}}, sxth269 ; CHECK: sub {{x[0-9]+}}, {{x[0-9]+}}, {{w[0-9]+}}, sxth #4
169 ; CHECK-NEXT: sxth r0, r0170 ; CHECK-NEXT: sxth r1, r1174 ; CHECK-NEXT: sxth r2, r2175 ; CHECK-NEXT: sxth r1, r1180 ; CHECK-NEXT: sxth r1, r1181 ; CHECK-NEXT: sxth r2, r2186 ; CHECK-NEXT: sxth r1, r1187 ; CHECK-NEXT: sxth r2, r2188 ; CHECK-NEXT: sxth r4, r4192 ; CHECK-NEXT: sxth.w lr, r2[all …]
12 ; CHECK-NEXT: sxth r1, r113 ; CHECK-NEXT: sxth r2, r2
26 sxth r2, r328 @ CHECK: sxth r2, r3 @ encoding: [0x1a,0xb2]