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Searched refs:sxtl2 (Results 1 – 21 of 21) sorted by relevance

/external/llvm/test/MC/AArch64/
Dneon-sxtl.s20 sxtl2 v0.8h, v1.16b
21 sxtl2 v0.4s, v1.8h
22 sxtl2 v0.2d, v1.4s
/external/llvm-project/llvm/test/MC/AArch64/
Dneon-sxtl.s20 sxtl2 v0.8h, v1.16b
21 sxtl2 v0.4s, v1.8h
22 sxtl2 v0.2d, v1.4s
/external/vixl/src/aarch64/
Dlogic-aarch64.cc1716 LogicVRegister extendedreg = sxtl2(vform, temp2, src); in sshll2()
3118 LogicVRegister Simulator::sxtl2(VectorFormat vform, in sxtl2() function in vixl::aarch64::Simulator
3521 sxtl2(vform, temp1, src1); in saddl2()
3522 sxtl2(vform, temp2, src2); in saddl2()
3544 sxtl2(vform, temp, src2); in saddw2()
3613 sxtl2(vform, temp1, src1); in ssubl2()
3614 sxtl2(vform, temp2, src2); in ssubl2()
3636 sxtl2(vform, temp, src2); in ssubw2()
3683 sxtl2(vform, temp1, src1); in sabal2()
3684 sxtl2(vform, temp2, src2); in sabal2()
[all …]
Dsimulator-aarch64.h3475 LogicVRegister sxtl2(VectorFormat vform,
Dassembler-aarch64.h2977 void sxtl2(const VRegister& vd, const VRegister& vn);
Dassembler-aarch64.cc5021 void Assembler::sxtl2(const VRegister& vd, const VRegister& vn) { in sxtl2() function in vixl::aarch64::Assembler
Dmacro-assembler-aarch64.h2896 V(sxtl2, Sxtl2) \
/external/libhevc/common/arm64/
Dihevc_intra_pred_luma_vert.s206 sxtl2 v28.8h, v26.16b
/external/llvm/lib/Target/AArch64/
DAArch64InstrInfo.td4877 // Vector shift sxtl2 aliases
4878 def : InstAlias<"sxtl2.8h $dst, $src1",
4880 def : InstAlias<"sxtl2 $dst.8h, $src1.16b",
4882 def : InstAlias<"sxtl2.4s $dst, $src1",
4884 def : InstAlias<"sxtl2 $dst.4s, $src1.8h",
4886 def : InstAlias<"sxtl2.2d $dst, $src1",
4888 def : InstAlias<"sxtl2 $dst.2d, $src1.4s",
/external/llvm-project/llvm/lib/Target/AArch64/
DAArch64InstrInfo.td6151 // Vector shift sxtl2 aliases
6152 def : InstAlias<"sxtl2.8h $dst, $src1",
6154 def : InstAlias<"sxtl2 $dst.8h, $src1.16b",
6156 def : InstAlias<"sxtl2.4s $dst, $src1",
6158 def : InstAlias<"sxtl2 $dst.4s, $src1.8h",
6160 def : InstAlias<"sxtl2.2d $dst, $src1",
6162 def : InstAlias<"sxtl2 $dst.2d, $src1.4s",
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64InstrInfo.td5906 // Vector shift sxtl2 aliases
5907 def : InstAlias<"sxtl2.8h $dst, $src1",
5909 def : InstAlias<"sxtl2 $dst.8h, $src1.16b",
5911 def : InstAlias<"sxtl2.4s $dst, $src1",
5913 def : InstAlias<"sxtl2 $dst.4s, $src1.8h",
5915 def : InstAlias<"sxtl2.2d $dst, $src1",
5917 def : InstAlias<"sxtl2 $dst.2d, $src1.4s",
/external/vixl/test/aarch64/
Dtest-trace-aarch64.cc2135 __ sxtl2(v6.V2D(), v7.V4S()); in GenerateTestSequenceNEON() local
2136 __ sxtl2(v9.V4S(), v27.V8H()); in GenerateTestSequenceNEON() local
2137 __ sxtl2(v16.V8H(), v16.V16B()); in GenerateTestSequenceNEON() local
Dtest-cpu-features-aarch64.cc2405 TEST_NEON(sxtl2_0, sxtl2(v0.V8H(), v1.V16B()))
2406 TEST_NEON(sxtl2_1, sxtl2(v0.V4S(), v1.V8H()))
2407 TEST_NEON(sxtl2_2, sxtl2(v0.V2D(), v1.V4S()))
/external/vixl/test/test-trace-reference/
Dlog-disasm-colour1795 0x~~~~~~~~~~~~~~~~ 4f20a4e6 sxtl2 v6.2d, v7.4s
1796 0x~~~~~~~~~~~~~~~~ 4f10a769 sxtl2 v9.4s, v27.8h
1797 0x~~~~~~~~~~~~~~~~ 4f08a610 sxtl2 v16.8h, v16.16b
Dlog-disasm1795 0x~~~~~~~~~~~~~~~~ 4f20a4e6 sxtl2 v6.2d, v7.4s
1796 0x~~~~~~~~~~~~~~~~ 4f10a769 sxtl2 v9.4s, v27.8h
1797 0x~~~~~~~~~~~~~~~~ 4f08a610 sxtl2 v16.8h, v16.16b
Dlog-cpufeatures-custom1794 0x~~~~~~~~~~~~~~~~ 4f20a4e6 sxtl2 v6.2d, v7.4s ### {NEON} ###
1795 0x~~~~~~~~~~~~~~~~ 4f10a769 sxtl2 v9.4s, v27.8h ### {NEON} ###
1796 0x~~~~~~~~~~~~~~~~ 4f08a610 sxtl2 v16.8h, v16.16b ### {NEON} ###
Dlog-cpufeatures-colour1794 0x~~~~~~~~~~~~~~~~ 4f20a4e6 sxtl2 v6.2d, v7.4s NEON
1795 0x~~~~~~~~~~~~~~~~ 4f10a769 sxtl2 v9.4s, v27.8h NEON
1796 0x~~~~~~~~~~~~~~~~ 4f08a610 sxtl2 v16.8h, v16.16b NEON
Dlog-cpufeatures1794 0x~~~~~~~~~~~~~~~~ 4f20a4e6 sxtl2 v6.2d, v7.4s // Needs: NEON
1795 0x~~~~~~~~~~~~~~~~ 4f10a769 sxtl2 v9.4s, v27.8h // Needs: NEON
1796 0x~~~~~~~~~~~~~~~~ 4f08a610 sxtl2 v16.8h, v16.16b // Needs: NEON
Dlog-all8844 0x~~~~~~~~~~~~~~~~ 4f20a4e6 sxtl2 v6.2d, v7.4s
8846 0x~~~~~~~~~~~~~~~~ 4f10a769 sxtl2 v9.4s, v27.8h
8848 0x~~~~~~~~~~~~~~~~ 4f08a610 sxtl2 v16.8h, v16.16b
/external/vixl/doc/aarch64/
Dsupported-instructions-aarch64.md5567 void sxtl2(const VRegister& vd, const VRegister& vn)
/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/AArch64/
DAArch64GenAsmMatcher.inc12598 "lh\004sxtb\004sxth\004sxtl\005sxtl2\004sxtw\003sys\004sysl\003tbl\004tb"
19129 …{ 6091 /* sxtl2 */, AArch64::SSHLLv4i32_shift, Convert__VectorReg1281_1__VectorReg1281_2__imm_95_0…
19130 …{ 6091 /* sxtl2 */, AArch64::SSHLLv8i16_shift, Convert__VectorReg1281_1__VectorReg1281_2__imm_95_0…
19131 …{ 6091 /* sxtl2 */, AArch64::SSHLLv16i8_shift, Convert__VectorReg1281_1__VectorReg1281_2__imm_95_0…
19132 …{ 6091 /* sxtl2 */, AArch64::SSHLLv4i32_shift, Convert__VectorReg1281_0__VectorReg1281_2__imm_95_0…
19133 …{ 6091 /* sxtl2 */, AArch64::SSHLLv8i16_shift, Convert__VectorReg1281_0__VectorReg1281_2__imm_95_0…
19134 …{ 6091 /* sxtl2 */, AArch64::SSHLLv16i8_shift, Convert__VectorReg1281_0__VectorReg1281_2__imm_95_0…
26502 …{ 6091 /* sxtl2 */, AArch64::SSHLLv4i32_shift, Convert__VectorReg1281_1__VectorReg1281_2__imm_95_0…
26503 …{ 6091 /* sxtl2 */, AArch64::SSHLLv8i16_shift, Convert__VectorReg1281_1__VectorReg1281_2__imm_95_0…
26504 …{ 6091 /* sxtl2 */, AArch64::SSHLLv16i8_shift, Convert__VectorReg1281_1__VectorReg1281_2__imm_95_0…
[all …]