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/external/arm-trusted-firmware/lib/libc/aarch64/
Dmemset.S49 less_64:tbz w2, #5, less_32 /* < 32 bytes */
52 less_32:tbz w2, #4, less_16 /* < 16 bytes */
54 less_16:tbz w2, #3, less_8 /* < 8 bytes */
56 less_8: tbz w2, #2, less_4 /* < 4 bytes */
58 less_4: tbz w2, #1, less_2 /* < 2 bytes */
60 less_2: tbz w2, #0, exit
/external/llvm-project/llvm/test/CodeGen/AArch64/
Daarch64-tbz.ll5 ; CHECK: tbz {{w[0-9]}}, #3, {{.LBB0_3}}
6 ; CHECK: tbz w[[REG1:[0-9]+]], #2, {{.LBB0_3}}
30 ; CHECK: tbz w[[REG1:[0-9]+]], #3, {{.LBB1_3}}
53 ; CHECK: tbz {{w[0-9]}}, #3, {{.LBB2_3}}
54 ; CHECK: tbz w[[REG1:[0-9]+]], #28, {{.LBB2_3}}
76 ; CHECK: tbz {{w[0-9]}}, #3, {{.LBB3_3}}
77 ; CHECK: tbz [[REG1:x[0-9]+]], #35, {{.LBB3_3}}
Dfast-isel-tbz.ll6 ; CHECK: tbz {{w[0-9]+}}, #0, {{LBB.+_2}}
18 ; CHECK: tbz w0, #1, {{LBB.+_2}}
30 ; CHECK: tbz w0, #2, {{LBB.+_2}}
42 ; CHECK: tbz w0, #3, {{LBB.+_2}}
54 ; CHECK: tbz x0, #32, {{LBB.+_2}}
170 ; FAST: tbz w0, #7, {{LBB.+_2}}
181 ; FAST: tbz w0, #15, {{LBB.+_2}}
236 ; FAST: tbz w0, #7, {{LBB.+_2}}
247 ; FAST: tbz w0, #15, {{LBB.+_2}}
258 ; CHECK: tbz w0, #31, {{LBB.+_2}}
[all …]
Dtst-br.ll18 ; CHECK: tbz {{w[0-9]+}}, #15, [[LBL_end1:.?LBB0_[0-9]+]]
24 ; CHECK: tbz {{w[0-9]+}}, #12, [[LBL_end1]]
30 ; CHECK: tbz {{[wx][0-9]+}}, #15, [[LBL_end1]]
36 ; CHECK: tbz {{[wx][0-9]+}}, #12, [[LBL_end1]]
Dand-sink.ll8 ; Test that and is sunk into cmp block to form tbz.
11 ; CHECK: tbz w1, #0
34 ; Test that both 'and' and cmp get sunk to form tbz.
38 ; CHECK: tbz w1, #0
40 ; CHECK: tbz w2, #0
Dbranch-relax-asm.ll1 ; RUN: llc -mtriple=aarch64-apple-ios7.0 -disable-block-placement -aarch64-tbz-offset-bits=4 -o - %…
7 ; of the limited range we gave tbz. So branch relaxation has to invert the
9 ; CHECK: tbz w0, #0, [[TRUE:LBB[0-9]+_[0-9]+]]
/external/llvm/test/CodeGen/AArch64/
Daarch64-tbz.ll4 ; CHECK: tbz {{w[0-9]}}, #3, {{.LBB0_3}}
5 ; CHECK: tbz w[[REG1:[0-9]+]], #2, {{.LBB0_3}}
29 ; CHECK: tbz w[[REG1:[0-9]+]], #3, {{.LBB1_3}}
52 ; CHECK: tbz {{w[0-9]}}, #3, {{.LBB2_3}}
53 ; CHECK: tbz w[[REG1:[0-9]+]], #28, {{.LBB2_3}}
75 ; CHECK: tbz {{w[0-9]}}, #3, {{.LBB3_3}}
76 ; CHECK: tbz [[REG1:x[0-9]+]], #35, {{.LBB3_3}}
Dfast-isel-tbz.ll6 ; CHECK: tbz {{w[0-9]+}}, #0, {{LBB.+_2}}
18 ; CHECK: tbz w0, #1, {{LBB.+_2}}
30 ; CHECK: tbz w0, #2, {{LBB.+_2}}
42 ; CHECK: tbz w0, #3, {{LBB.+_2}}
54 ; CHECK: tbz x0, #32, {{LBB.+_2}}
170 ; FAST: tbz w0, #7, {{LBB.+_2}}
181 ; FAST: tbz w0, #15, {{LBB.+_2}}
236 ; FAST: tbz w0, #7, {{LBB.+_2}}
247 ; FAST: tbz w0, #15, {{LBB.+_2}}
258 ; CHECK: tbz w0, #31, {{LBB.+_2}}
[all …]
Dtst-br.ll18 ; CHECK: tbz {{w[0-9]+}}, #15, [[LBL_end1:.?LBB0_[0-9]+]]
24 ; CHECK: tbz {{w[0-9]+}}, #12, [[LBL_end1]]
30 ; CHECK: tbz {{[wx][0-9]+}}, #15, [[LBL_end1]]
36 ; CHECK: tbz {{[wx][0-9]+}}, #12, [[LBL_end1]]
Dbranch-relax-asm.ll1 ; RUN: llc -mtriple=aarch64-apple-ios7.0 -disable-block-placement -aarch64-tbz-offset-bits=4 -o - %…
7 ; of the limited range we gave tbz. So branch relaxation has to invert the
9 ; CHECK: tbz w0, #0, [[TRUE:LBB[0-9]+_[0-9]+]]
Dtbz-tbnz.ll13 ; CHECK: tbz [[CMP]], #31
31 ; CHECK: tbz [[CMP]], #63
121 ; CHECK: tbz [[CMP]], #31
181 ; CHECK: tbz x0, #63
197 ; CHECK: tbz x0, #63
212 ; CHECK: tbz [[CMP]], #63
232 ; CHECK: tbz x0, #63
250 ; CHECK: tbz [[CMP]], #63
Darm64-fast-isel-br.ll97 ; CHECK: tbz w0, #0, LBB4_2
107 ; CHECK: tbz w{{[0-9]+}}, #0, LBB4_4
117 ; CHECK: tbz w{{[0-9]+}}, #0, LBB4_6
137 ; CHECK: tbz w[[REG2]], #0, LBB5_2
/external/llvm-project/lld/test/ELF/
Daarch64-tstbr14-reloc.s22 # CHECK-NEXT: 210144: tbz x6, #45, 0x210120 <_foo>
23 # CHECK-NEXT: 210148: tbz x6, #45, 0x210130 <_bar>
62 #DSO-NEXT: 1031c: tbz x6, #45, 0x10350 <_foo@plt>
63 #DSO-NEXT: 10320: tbz x6, #45, 0x10360 <_bar@plt>
93 tbz x6, #45, _foo
94 tbz x6, #45, _bar
/external/arm-trusted-firmware/plat/socionext/uniphier/
Duniphier_console.S24 tbz w2, #UNIPHIER_UART_LSR_THRE_BIT, 0b
42 tbz w1, #UNIPHIER_UART_LSR_DR_BIT, 0f
62 tbz w1, #UNIPHIER_UART_LSR_TEMT_BIT, 0b
/external/arm-optimized-routines/string/aarch64/
Dmemset.S38 tbz count, 3, 1f
43 1: tbz count, 2, 2f
49 tbz count, 1, 3f
58 tbz count, 5, 1f
/external/llvm-project/libc/AOR_v20.02/string/aarch64/
Dmemset.S37 tbz count, 3, 1f
42 1: tbz count, 2, 2f
48 tbz count, 1, 3f
57 tbz count, 5, 1f
/external/llvm/test/MC/AArch64/
Darm64-branch-encoding.s113 tbz x1, #3, foo
118 tbz w1, #3, foo
123 tbz w1, #3, #28
124 ; CHECK: tbz w1, #3, #28
125 tbz w3, #5, #32764
126 ; CHECK: tbz w3, #5, #32764 ; encoding: [0xe3,0xff,0x2b,0x36]
Dfixup-out-of-range.s46 tbz x0, #1, distant
49 tbz x0, #1, unaligned
/external/llvm-project/llvm/test/MC/AArch64/
Darm64-branch-encoding.s113 tbz x1, #3, foo
118 tbz w1, #3, foo
123 tbz w1, #3, #28
124 ; CHECK: tbz w1, #3, #28
125 tbz w3, #5, #32764
126 ; CHECK: tbz w3, #5, #32764 ; encoding: [0xe3,0xff,0x2b,0x36]
Dfixup-out-of-range.s47 tbz x0, #1, distant
50 tbz x0, #1, unaligned
/external/llvm-project/lldb/tools/lldb-vscode/syntaxes/
Darm64.disasm11 liblog.so[0x6034] <+32>: tbz w8, #0x0, 0x6168 ; <+340> at config_read.cpp:65:1
27 liblog.so[0x6074] <+96>: tbz w0, #0x1f, 0x608c ; <+120> [inlined] __android_log_add_tra…
32 liblog.so[0x6088] <+116>: tbz w0, #0x1f, 0x60c0 ; <+172> [inlined] __android_log_add_tra…
41 liblog.so[0x60ac] <+152>: tbz w0, #0x1f, 0x60c0 ; <+172> [inlined] __android_log_add_tra…
65 liblog.so[0x610c] <+248>: tbz w0, #0x1f, 0x6124 ; <+272> [inlined] __android_log_add_tra…
70 liblog.so[0x6120] <+268>: tbz w0, #0x1f, 0x6158 ; <+324> [inlined] __android_log_add_tra…
79 liblog.so[0x6144] <+304>: tbz w0, #0x1f, 0x6158 ; <+324> [inlined] __android_log_add_tra…
/external/llvm-project/lld/test/COFF/
Darm64-thunks.s13 tbz w0, #0, func1
19 tbz w0, #0, func2
/external/llvm/test/MC/Disassembler/AArch64/
Darm64-branch.txt54 # CHECK: tbz w0, #1, #16
56 # CHECK: tbz w1, #30, #-4
70 # CHECK: tbz w0, #1, #-12
/external/llvm-project/llvm/test/MC/Disassembler/AArch64/
Darm64-branch.txt54 # CHECK: tbz w0, #1, #16
56 # CHECK: tbz w1, #30, #-4
70 # CHECK: tbz w0, #1, #-12
/external/python/cpython2/Modules/_ctypes/libffi/src/aarch64/
Dsysv.S145 tbz x23, #AARCH64_FFI_WITH_V_BIT, 1f
174 tbz x23, #AARCH64_FFI_WITH_V_BIT, 1f
282 tbz x0, #AARCH64_FFI_WITH_V_BIT, 1f
301 tbz x0, #AARCH64_FFI_WITH_V_BIT, 1f

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