| /external/llvm-project/llvm/test/CodeGen/ARM/ |
| D | acle-intrinsics.ll | 263 define i32 @uasx(i32 %a, i32 %b) nounwind {
264 ; CHECK-LABEL: uasx
265 ; CHECK: uasx r0, r0, r1
266 %tmp = call i32 @llvm.arm.uasx(i32 %a, i32 %b)
459 declare i32 @llvm.arm.uasx(i32, i32) nounwind
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| /external/vixl/test/aarch32/ |
| D | test-assembler-cond-rd-rn-rm-t32.cc | 101 M(uasx) \
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| D | test-assembler-cond-rd-rn-rm-a32.cc | 102 M(uasx) \
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| /external/llvm-project/llvm/test/tools/llvm-mca/ARM/ |
| D | cortex-a57-thumb.s | 789 uasx r9, r12, r0
792 uasx r9, r12, r0
1696 # CHECK-NEXT: 2 3 1.00 * * U uasx r9, r12, r0
1699 # CHECK-NEXT: 2 3 1.00 * * U uasx r9, r12, r0
2610 # CHECK-NEXT: - 0.50 0.50 - 1.00 - - - uasx r9, r12, r0
2613 # CHECK-NEXT: - 0.50 0.50 - 1.00 - - - uasx r9, r12, r0
|
| D | m7-int.s | 388 uasx r0, r1, r2 label
817 # CHECK-NEXT: 1 1 1.00 * * U uasx r0, r1, r2
1257 …0.50 - - - - 1.00 - - - - - - uasx r0, r1, r2
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| D | m4-int.s | 401 uasx r0, r1, r2 label
841 # CHECK-NEXT: 1 1 1.00 * * U uasx r0, r1, r2
1279 # CHECK-NEXT: 1.00 uasx r0, r1, r2
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| D | cortex-a57-basic-instructions.s | 776 uasx r9, r12, r0
1646 # CHECK-NEXT: 2 3 1.00 * * U uasx r9, r12, r0
2523 # CHECK-NEXT: - 0.50 0.50 - 1.00 - - - uasx r9, r12, r0
|
| /external/llvm/test/MC/Disassembler/ARM/ |
| D | thumb2.txt | 2341 # CHECK: uasx r9, r12, r0
2344 # CHECK: uasx r9, r12, r0
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| D | basic-arm-instructions.txt | 2222 # CHECK: uasx r9, r12, r0
|
| /external/llvm-project/llvm/test/MC/Disassembler/ARM/ |
| D | thumb2.txt | 2341 # CHECK: uasx r9, r12, r0
2344 # CHECK: uasx r9, r12, r0
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| D | basic-arm-instructions.txt | 2222 # CHECK: uasx r9, r12, r0
|
| /external/capstone/suite/MC/ARM/ |
| D | basic-arm-instructions.s.cs | 903 0x30,0x9f,0x5c,0xe6 = uasx r9, r12, r0
|
| /external/llvm/test/MC/ARM/ |
| D | basic-thumb2-instructions.s | 3317 uasx r9, r12, r0
3324 @ CHECK: uasx r9, r12, r0 @ encoding: [0xac,0xfa,0x40,0xf9]
3327 @ CHECK: uasx r9, r12, r0 @ encoding: [0xac,0xfa,0x40,0xf9]
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| D | basic-arm-instructions.s | 3229 uasx r9, r12, r0
3232 @ CHECK: uasx r9, r12, r0 @ encoding: [0x30,0x9f,0x5c,0xe6]
|
| /external/llvm-project/llvm/test/MC/ARM/ |
| D | basic-thumb2-instructions.s | 3576 uasx r9, r12, r0
3583 @ CHECK: uasx r9, r12, r0 @ encoding: [0xac,0xfa,0x40,0xf9]
3586 @ CHECK: uasx r9, r12, r0 @ encoding: [0xac,0xfa,0x40,0xf9]
|
| D | basic-arm-instructions.s | 3259 uasx r9, r12, r0
3262 @ CHECK: uasx r9, r12, r0 @ encoding: [0x30,0x9f,0x5c,0xe6]
|
| /external/vixl/src/aarch32/ |
| D | assembler-aarch32.h | 3621 void uasx(Condition cond, Register rd, Register rn, Register rm);
3622 void uasx(Register rd, Register rn, Register rm) { uasx(al, rd, rn, rm); } in uasx() function
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| D | disasm-aarch32.h | 1364 void uasx(Condition cond, Register rd, Register rn, Register rm);
|
| /external/capstone/arch/AArch64/ |
| D | ARMMappingInsnOp.inc | 1138 { /* ARM_UASX, ARM_INS_UASX: uasx${p} $rd, $rn, $rm */
6319 { /* ARM_t2UASX, ARM_INS_UASX: uasx${p} $rd, $rn, $rm */
|
| /external/capstone/arch/ARM/ |
| D | ARMMappingInsnOp.inc | 1138 { /* ARM_UASX, ARM_INS_UASX: uasx${p} $rd, $rn, $rm */
6319 { /* ARM_t2UASX, ARM_INS_UASX: uasx${p} $rd, $rn, $rm */
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMInstrInfo.td | 3595 def UASX : AAI<0b01100101, 0b11110011, "uasx">;
5693 def : MnemonicAlias<"uaddsubx", "uasx">;
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| D | ARMInstrThumb2.td | 2166 def t2UASX : T2I_pam<0b010, 0b0100, "uasx">;
|
| /external/llvm-project/llvm/lib/Target/ARM/ |
| D | ARMInstrInfo.td | 3953 def UASX : AAIIntrinsic<0b01100101, 0b11110011, "uasx", int_arm_uasx>;
6232 def : MnemonicAlias<"uaddsubx", "uasx">;
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMInstrInfo.td | 3820 def UASX : AAIIntrinsic<0b01100101, 0b11110011, "uasx", int_arm_uasx>;
6075 def : MnemonicAlias<"uaddsubx", "uasx">;
|
| /external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/ARM/ |
| D | ARMGenAsmMatcher.inc | 1417 Mnemonic = "uasx"; // "uaddsubx"
9913 "tst\002tt\003tta\004ttat\003ttt\006uadd16\005uadd8\004uasx\004ubfx\003u"
11483 …{ 1718 /* uasx */, ARM::t2UASX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDS…
11484 …{ 1718 /* uasx */, ARM::UASX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_Con…
|