| /external/llvm-project/llvm/test/MC/AArch64/SVE/ |
| D | udivr-diagnostics.s | 7 udivr z0.b, p7/m, z0.b, z1.b label
12 udivr z0.h, p7/m, z0.h, z1.h label
21 udivr z0.s, p7/m, z1.s, z2.s label
30 udivr z0.s, p8/m, z0.s, z1.s label
|
| D | udivr.s | 10 udivr z0.s, p7/m, z0.s, z31.s label
16 udivr z0.d, p7/m, z0.d, z31.d label
32 udivr z0.d, p7/m, z0.d, z31.d label
44 udivr z0.d, p7/m, z0.d, z31.d label
|
| /external/llvm-project/llvm/test/CodeGen/AArch64/ |
| D | sve-int-div-pred.ll | 69 ; CHECK: udivr z0.s, p0/m, z0.s, z1.s
71 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.udivr.nxv4i32(<vscale x 4 x i1> %pg,
79 ; CHECK: udivr z0.d, p0/m, z0.d, z1.d
81 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.udivr.nxv2i64(<vscale x 2 x i1> %pg,
93 declare <vscale x 4 x i32> @llvm.aarch64.sve.udivr.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>…
94 declare <vscale x 2 x i64> @llvm.aarch64.sve.udivr.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>…
|
| D | sve-fixed-length-int-div.ll | 513 ; CHECK-NEXT: udivr [[RES_HI_HI:z[0-9]+]].s, [[PG]]/m, [[OP2_HI_HI]].s, [[OP1_HI_HI]].s
515 ; CHECK-NEXT: udivr [[RES_HI_LO:z[0-9]+]].s, [[PG]]/m, [[OP2_HI_LO]].s, [[OP1_HI_LO]].s
540 ; CHECK-NEXT: udivr [[RES_HI_HI:z[0-9]+]].s, [[PG]]/m, [[OP2_HI_HI]].s, [[OP1_HI_HI]].s
542 ; CHECK-NEXT: udivr [[RES_HI_LO:z[0-9]+]].s, [[PG]]/m, [[OP2_HI_LO]].s, [[OP1_HI_LO]].s
570 ; CHECK-NEXT: udivr [[RES_HI_HI:z[0-9]+]].s, [[PG1]]/m, [[OP2_HI_HI]].s, [[OP1_HI_HI]].s
572 ; CHECK-NEXT: udivr [[RES_HI_LO:z[0-9]+]].s, [[PG1]]/m, [[OP2_HI_LO]].s, [[OP1_HI_LO]].s
604 ; VBITS_GE_512-NEXT: udivr [[RES_HI_HI:z[0-9]+]].s, [[PG1]]/m, [[OP2_HI_HI]].s, [[OP1_HI_HI]].s
606 ; VBITS_GE_512-NEXT: udivr [[RES_HI_LO:z[0-9]+]].s, [[PG1]]/m, [[OP2_HI_LO]].s, [[OP1_HI_LO]].s
638 ; VBITS_GE_1024-NEXT: udivr [[RES_HI_HI:z[0-9]+]].s, [[PG1]]/m, [[OP2_HI_HI]].s, [[OP1_HI_HI]].s
640 ; VBITS_GE_1024-NEXT: udivr [[RES_HI_LO:z[0-9]+]].s, [[PG1]]/m, [[OP2_HI_LO]].s, [[OP1_HI_LO]].s
[all …]
|
| D | llvm-ir-to-intrinsic.ll | 199 ; CHECK-NEXT: udivr z4.s, p0/m, z4.s, z5.s
201 ; CHECK-NEXT: udivr z2.s, p0/m, z2.s, z3.s
223 ; CHECK-NEXT: udivr z2.s, p0/m, z2.s, z3.s
302 ; CHECK-NEXT: udivr z6.s, p0/m, z6.s, z7.s
304 ; CHECK-NEXT: udivr z2.s, p0/m, z2.s, z3.s
309 ; CHECK-NEXT: udivr z4.s, p0/m, z4.s, z5.s
326 ; CHECK-NEXT: udivr z2.s, p0/m, z2.s, z3.s
|
| /external/vixl/test/aarch64/ |
| D | test-api-movprfx-aarch64.cc | 266 __ udivr(z19.VnD(), p4.Merging(), z19.VnD(), z19.VnD()); in TEST() local
800 __ udivr(z19.VnS(), p5.Merging(), z19.VnS(), z9.VnS()); in TEST() local
1552 __ udivr(z22.VnD(), p7.Merging(), z22.VnD(), z27.VnD()); in TEST() local
|
| D | test-disasm-sve-aarch64.cc | 2261 COMPARE_PREFIX(udivr(z27.VnS(), p5.Merging(), z27.VnS(), z31.VnS()), in TEST()
|
| /external/vixl/src/aarch64/ |
| D | macro-assembler-sve-aarch64.cc | 1088 &Assembler::udivr)); in Udiv()
|
| D | assembler-aarch64.h | 5623 void udivr(const ZRegister& zd,
|
| D | assembler-sve-aarch64.cc | 2573 void Assembler::udivr(const ZRegister& zd, in udivr() function in vixl::aarch64::Assembler
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64SVEInstrInfo.td | 149 defm UDIVR_ZPmZ : sve_int_bin_pred_arit_2_div<0b111, "udivr", int_aarch64_sve_udivr>;
|
| /external/llvm-project/llvm/lib/Target/AArch64/ |
| D | AArch64SVEInstrInfo.td | 352 …defm UDIVR_ZPmZ : sve_int_bin_pred_arit_2_div<0b111, "udivr", "UDIVR_ZPZZ", int_aarch64_sve_udivr,…
|
| /external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/AArch64/ |
| D | AArch64GenAsmMatcher.inc | 12603 "\006uaddwt\004ubfm\005ucvtf\003udf\004udiv\005udivr\004udot\005uhadd\005"
19369 …{ 6340 /* udivr */, AArch64::UDIVR_ZPmZ_S, Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Tie…
19370 …{ 6340 /* udivr */, AArch64::UDIVR_ZPmZ_D, Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Tie…
26742 …{ 6340 /* udivr */, AArch64::UDIVR_ZPmZ_S, Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Tie…
26743 …{ 6340 /* udivr */, AArch64::UDIVR_ZPmZ_D, Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Tie…
39457 { 6340 /* udivr */, 2 /* 1 */, MCK_SVEPredicate3bAnyReg, AMFBS_HasSVE },
39458 { 6340 /* udivr */, 49 /* 0, 4, 5 */, MCK_SVEVectorSReg, AMFBS_HasSVE },
39459 { 6340 /* udivr */, 2 /* 1 */, MCK_SVEPredicate3bAnyReg, AMFBS_HasSVE },
39460 { 6340 /* udivr */, 49 /* 0, 4, 5 */, MCK_SVEVectorSReg, AMFBS_HasSVE },
39461 { 6340 /* udivr */, 2 /* 1 */, MCK_SVEPredicate3bAnyReg, AMFBS_HasSVE },
[all …]
|
| /external/swiftshader/third_party/llvm-10.0/configs/common/include/llvm/IR/ |
| D | IntrinsicImpl.inc | 793 "llvm.aarch64.sve.udivr",
10926 1, // llvm.aarch64.sve.udivr
|