1// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s 2 3 4// ------------------------------------------------------------------------- // 5// Invalid element size 6 7udivr z0.b, p7/m, z0.b, z1.b 8// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width 9// CHECK-NEXT: udivr z0.b, p7/m, z0.b, z1.b 10// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 11 12udivr z0.h, p7/m, z0.h, z1.h 13// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width 14// CHECK-NEXT: udivr z0.h, p7/m, z0.h, z1.h 15// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 16 17 18// ------------------------------------------------------------------------- // 19// Tied operands must match 20 21udivr z0.s, p7/m, z1.s, z2.s 22// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register 23// CHECK-NEXT: udivr z0.s, p7/m, z1.s, z2.s 24// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 25 26 27// ------------------------------------------------------------------------- // 28// Invalid predicate 29 30udivr z0.s, p8/m, z0.s, z1.s 31// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix) 32// CHECK-NEXT: udivr z0.s, p8/m, z0.s, z1.s 33// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 34