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/external/llvm-project/llvm/test/CodeGen/ARM/
Dacle-intrinsics.ll277 define i32 @uhasx(i32 %a, i32 %b) nounwind {
278 ; CHECK-LABEL: uhasx
279 ; CHECK: uhasx r0, r0, r1
280 %tmp = call i32 @llvm.arm.uhasx(i32 %a, i32 %b)
462 declare i32 @llvm.arm.uhasx(i32, i32) nounwind
/external/capstone/suite/MC/ARM/
Dbasic-thumb2-instructions.s.cs1090 0xa1,0xfa,0x65,0xf4 = uhasx r4, r1, r5
1095 0xa1,0xfa,0x65,0xf4 = uhasx r4, r1, r5
Dbasic-arm-instructions.s.cs911 0x32,0x4f,0x78,0xe6 = uhasx r4, r8, r2
/external/vixl/test/aarch32/
Dtest-assembler-cond-rd-rn-rm-t32.cc81 M(uhasx) \
Dtest-assembler-cond-rd-rn-rm-a32.cc82 M(uhasx) \
/external/llvm-project/llvm/test/tools/llvm-mca/ARM/
Dm7-int.s394 uhasx r0, r1, r2 label
822 # CHECK-NEXT: 1 1 1.00 uhasx r0, r1, r2
1262 ….50 - - - - 1.00 - - - - - - uhasx r0, r1, r2
Dm4-int.s407 uhasx r0, r1, r2 label
846 # CHECK-NEXT: 1 1 1.00 uhasx r0, r1, r2
1284 # CHECK-NEXT: 1.00 uhasx r0, r1, r2
Dcortex-a57-basic-instructions.s784 uhasx r4, r8, r2
1654 # CHECK-NEXT: 2 3 1.00 uhasx r4, r8, r2
2531 # CHECK-NEXT: - 0.50 0.50 - 1.00 - - - uhasx r4, r8, r2
Dcortex-a57-thumb.s803 uhasx r4, r1, r5
1710 # CHECK-NEXT: 2 3 1.00 uhasx r4, r1, r5
2624 # CHECK-NEXT: - 0.50 0.50 - 1.00 - - - uhasx r4, r1, r5
/external/llvm/test/MC/ARM/
Dbasic-thumb2-instructions.s3363 uhasx r4, r1, r5
3374 @ CHECK: uhasx r4, r1, r5 @ encoding: [0xa1,0xfa,0x65,0xf4]
3379 @ CHECK: uhasx r4, r1, r5 @ encoding: [0xa1,0xfa,0x65,0xf4]
Dbasic-arm-instructions.s3263 uhasx r4, r8, r2
3266 @ CHECK: uhasx r4, r8, r2 @ encoding: [0x32,0x4f,0x78,0xe6]
/external/llvm-project/llvm/test/MC/ARM/
Dbasic-thumb2-instructions.s3622 uhasx r4, r1, r5
3633 @ CHECK: uhasx r4, r1, r5 @ encoding: [0xa1,0xfa,0x65,0xf4]
3638 @ CHECK: uhasx r4, r1, r5 @ encoding: [0xa1,0xfa,0x65,0xf4]
Dbasic-arm-instructions.s3293 uhasx r4, r8, r2
3296 @ CHECK: uhasx r4, r8, r2 @ encoding: [0x32,0x4f,0x78,0xe6]
/external/vixl/src/aarch32/
Dassembler-aarch32.h3646 void uhasx(Condition cond, Register rd, Register rn, Register rm);
3647 void uhasx(Register rd, Register rn, Register rm) { uhasx(al, rd, rn, rm); } in uhasx() function
Ddisasm-aarch32.h1377 void uhasx(Condition cond, Register rd, Register rn, Register rm);
/external/llvm-project/llvm/test/MC/Disassembler/ARM/
Dbasic-arm-instructions.txt2256 # CHECK: uhasx r4, r8, r2
Dthumb2.txt2387 # CHECK: uhasx r4, r1, r5
/external/llvm/test/MC/Disassembler/ARM/
Dthumb2.txt2387 # CHECK: uhasx r4, r1, r5
Dbasic-arm-instructions.txt2256 # CHECK: uhasx r4, r8, r2
/external/capstone/arch/AArch64/
DARMMappingInsnOp.inc1156 { /* ARM_UHASX, ARM_INS_UHASX: uhasx${p} $rd, $rn, $rm */
6337 { /* ARM_t2UHASX, ARM_INS_UHASX: uhasx${p} $rd, $rn, $rm */
/external/capstone/arch/ARM/
DARMMappingInsnOp.inc1156 { /* ARM_UHASX, ARM_INS_UHASX: uhasx${p} $rd, $rn, $rm */
6337 { /* ARM_t2UHASX, ARM_INS_UHASX: uhasx${p} $rd, $rn, $rm */
/external/llvm/lib/Target/ARM/
DARMInstrInfo.td3610 def UHASX : AAI<0b01100111, 0b11110011, "uhasx">;
5695 def : MnemonicAlias<"uhaddsubx", "uhasx">;
/external/llvm-project/llvm/lib/Target/ARM/
DARMInstrInfo.td3968 def UHASX : AAIIntrinsic<0b01100111, 0b11110011, "uhasx", int_arm_uhasx>;
6234 def : MnemonicAlias<"uhaddsubx", "uhasx">;
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DARMInstrInfo.td3835 def UHASX : AAIIntrinsic<0b01100111, 0b11110011, "uhasx", int_arm_uhasx>;
6077 def : MnemonicAlias<"uhaddsubx", "uhasx">;
/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/ARM/
DARMGenAsmMatcher.inc1521 Mnemonic = "uhasx"; // "uhaddsubx"
9914 "df\004udiv\007uhadd16\006uhadd8\005uhasx\005uhsax\007uhsub16\006uhsub8\005"
11496 …{ 1752 /* uhasx */, ARM::t2UHASX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_Has…
11497 …{ 1752 /* uhasx */, ARM::UHASX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_C…

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