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/external/mesa3d/src/intel/tools/tests/gen9/
Dsends.asm8 …dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD8, or) mlen 1 ex_mlen 1 rlen 1 { align…
10 …dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD16, or) mlen 2 ex_mlen 2 rlen 2 { alig…
12 …dp data 1 MsgDesc: ( DC untyped surface write, Surface = 254, SIMD16, Mask = 0xe) mlen 2 ex_mlen 2…
14 …dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 254, SIMD16, add) mlen 2 ex_mlen 2 rlen 0 { a…
20 …dp data 1 MsgDesc: ( DC untyped surface write, Surface = 1, SIMD8, Mask = 0x0) mlen 1 ex_mlen 4 rl…
22 …dp data 1 MsgDesc: ( DC untyped surface write, Surface = 1, SIMD16, Mask = 0x0) mlen 2 ex_mlen 8 r…
24 …dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 0, SIMD8, imin) mlen 1 ex_mlen 1 rlen 0 { ali…
42 …dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 254, SIMD16, umin) mlen 2 ex_mlen 2 rlen 0 { …
44 …dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 254, SIMD16, imin) mlen 2 ex_mlen 2 rlen 0 { …
46 …dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 254, SIMD16, umax) mlen 2 ex_mlen 2 rlen 0 { …
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DSIInstrInfo.td1271 def VOP3Mods0 : ComplexPattern<untyped, 4, "SelectVOP3Mods0">;
1272 def VOP3Mods0Clamp : ComplexPattern<untyped, 3, "SelectVOP3Mods0Clamp">;
1273 def VOP3Mods : ComplexPattern<untyped, 2, "SelectVOP3Mods">;
1274 def VOP3NoMods : ComplexPattern<untyped, 1, "SelectVOP3NoMods">;
1280 def VOP3OMods : ComplexPattern<untyped, 3, "SelectVOP3OMods">;
1282 def VOP3PMods : ComplexPattern<untyped, 2, "SelectVOP3PMods">;
1283 def VOP3PMods0 : ComplexPattern<untyped, 3, "SelectVOP3PMods0">;
1285 def VOP3OpSel : ComplexPattern<untyped, 2, "SelectVOP3OpSel">;
1286 def VOP3OpSel0 : ComplexPattern<untyped, 3, "SelectVOP3OpSel0">;
1288 def VOP3OpSelMods : ComplexPattern<untyped, 2, "SelectVOP3OpSelMods">;
[all …]
DVOP1Instructions.td127 VOPProfile<[dstVt, srcVt, untyped, untyped]> {
263 def VOP_MOVRELS : VOPProfile<[i32, i32, untyped, untyped]> {
272 class VOP_MOVREL<RegisterOperand Src1RC> : VOPProfile<[untyped, i32, untyped, untyped]> {
400 def VOP_SWAP_I32 : VOPProfile<[i32, i32, i32, untyped]> {
/external/llvm-project/llvm/lib/Target/AMDGPU/
DSIInstrInfo.td1318 def VOP3Mods0 : ComplexPattern<untyped, 4, "SelectVOP3Mods0">;
1319 def VOP3Mods0Clamp : ComplexPattern<untyped, 3, "SelectVOP3Mods0Clamp">;
1320 def VOP3Mods : ComplexPattern<untyped, 2, "SelectVOP3Mods">;
1321 def VOP3NoMods : ComplexPattern<untyped, 1, "SelectVOP3NoMods">;
1325 def VOP3OMods : ComplexPattern<untyped, 3, "SelectVOP3OMods">;
1327 def VOP3PMods : ComplexPattern<untyped, 2, "SelectVOP3PMods">;
1329 def VOP3OpSel : ComplexPattern<untyped, 2, "SelectVOP3OpSel">;
1331 def VOP3OpSelMods : ComplexPattern<untyped, 2, "SelectVOP3OpSelMods">;
1333 def VOP3PMadMixMods : ComplexPattern<untyped, 2, "SelectVOP3PMadMixMods">;
1336 def Hi16Elt : ComplexPattern<untyped, 1, "SelectHi16Elt">;
[all …]
DVOP1Instructions.td134 VOPProfile<[dstVt, srcVt, untyped, untyped]> {
287 def VOP_MOVRELS : VOPProfile<[i32, i32, untyped, untyped]> {
296 class VOP_MOVREL<RegisterOperand Src1RC> : VOPProfile<[untyped, i32, untyped, untyped]> {
422 def VOP_SWAP_I32 : VOPProfile<[i32, i32, i32, untyped]> {
/external/llvm-project/lld/test/ELF/
Dmips-jalr-non-functions.s31 .reloc .Ltmp3, R_MIPS_JALR, untyped
36 ## However, we do perform the optimization for untyped symbols:
37 untyped: label
57 # CHECK-NEXT: b 8 <untyped>
/external/mesa3d/src/freedreno/computerator/examples/
Dtest-opcodes.sh143 stib.untyped.1d.u32.1 g[0] + r3.x, r2.x ; control: full->full
144 stib.untyped.1d.u32.1 g[0] + r3.y, r2.y ; test: half->full
145 stib.untyped.1d.u32.1 g[0] + r3.z, r2.z ; control: half->half
146 stib.untyped.1d.u32.1 g[0] + r3.w, r2.w ; test: full->half
Dinvocationid.asm10 stib.untyped.1d.u32.1 g[0] + r0.y, r0.x
Dsimple.asm25 stib.untyped.1d.u32.1 g[0] + r0.y, r0.x
/external/mesa3d/src/intel/tools/tests/gen7/
Dsend.asm244 … data MsgDesc: ( DC untyped atomic, 0, imin) mlen 2 rlen 1 { align16 1Q };
296 … data MsgDesc: ( DC untyped surface write, 1, 32) mlen 5 rlen 0 { align1 1Q };
298 … data MsgDesc: ( DC untyped surface write, 1, 16) mlen 10 rlen 0 { align1 1H };
460 … data MsgDesc: ( DC untyped surface read, 1, 32) mlen 1 rlen 4 { align1 1Q };
462 … data MsgDesc: ( DC untyped surface read, 1, 16) mlen 2 rlen 8 { align1 1H };
570 … data MsgDesc: ( DC untyped atomic, 0, inc) mlen 1 rlen 1 { align16 1Q };
634 data MsgDesc: ( DC untyped atomic, 1, inc) mlen 1 rlen 1 { align1 1Q };
636 data MsgDesc: ( DC untyped atomic, 1, inc) mlen 2 rlen 2 { align1 1H };
638 data MsgDesc: ( DC untyped atomic, 1, inc) mlen 1 rlen 0 { align1 1Q };
640 data MsgDesc: ( DC untyped atomic, 1, inc) mlen 2 rlen 0 { align1 1H };
[all …]
/external/mesa3d/src/intel/tools/tests/gen7.5/
Dsend.asm336 … dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD8, or) mlen 2 rlen 1 { align1 1Q };
338 … dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD8, inc) mlen 1 rlen 0 { align1 1Q };
340 … dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD16, or) mlen 4 rlen 2 { align1 1H };
342 … dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD16, inc) mlen 2 rlen 0 { align1 1H };
462 … dp data 1 MsgDesc: ( DC untyped 4x2 atomic op, Surface = 0, imin) mlen 2 rlen 1 { align16 1Q };
570 …dp data 1 MsgDesc: ( DC untyped surface write, Surface = 1, SIMD8, Mask = 0x0) mlen 5 rlen 0 { ali…
572 …dp data 1 MsgDesc: ( DC untyped surface write, Surface = 1, SIMD16, Mask = 0x0) mlen 10 rlen 0 { a…
786 …dp data 1 MsgDesc: ( untyped surface read, Surface = 1, SIMD8, Mask = 0x0) mlen 1 rlen 4 { align1 …
788 …dp data 1 MsgDesc: ( untyped surface read, Surface = 1, SIMD16, Mask = 0x0) mlen 2 rlen 8 { align1…
974 …dp data 1 MsgDesc: ( untyped surface read, Surface = 1, SIMD8, Mask = 0xe) mlen 1 rlen 1 { align1 …
[all …]
/external/llvm/lib/Target/AMDGPU/
DSIInstrInfo.td629 def VOP3Mods0 : ComplexPattern<untyped, 4, "SelectVOP3Mods0">;
630 def VOP3NoMods0 : ComplexPattern<untyped, 4, "SelectVOP3NoMods0">;
631 def VOP3Mods0Clamp : ComplexPattern<untyped, 3, "SelectVOP3Mods0Clamp">;
632 def VOP3Mods0Clamp0OMod : ComplexPattern<untyped, 4, "SelectVOP3Mods0Clamp0OMod">;
633 def VOP3Mods : ComplexPattern<untyped, 2, "SelectVOP3Mods">;
634 def VOP3NoMods : ComplexPattern<untyped, 2, "SelectVOP3NoMods">;
1139 !if (!eq(Src0.Value, untyped.Value), 0,
1140 !if (!eq(Src1.Value, untyped.Value), 1, // VOP1
1141 !if (!eq(Src2.Value, untyped.Value), 2, // VOP2
1438 field bit HasDst = !if(!eq(DstVT.Value, untyped.Value), 0, 1);
[all …]
/external/llvm-project/llvm/test/TableGen/
DDefaultOpsGlobalISel.td7 def SelectClamp : ComplexPattern<untyped, 2, "SelectClamp">;
8 def SelectOMod : ComplexPattern<untyped, 2, "SelectOMod">;
9 def SelectClampOMod : ComplexPattern<untyped, 3, "SelectClampOMod">;
10 def SelectSrcMods : ComplexPattern<untyped, 2, "SelectSrcMods">;
DConcatenatedSubregs.td64 def Dtup2 : MyClass<64, [untyped], (add Dtup2regs)>;
69 def Stup2 : MyClass<32, [untyped], (interleave DRegs, Stup2_odds_regs)>;
/external/mesa3d/src/intel/tools/tests/gen8/
Dsend.asm84 … dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD16, inc) mlen 2 rlen 2 { align1 1H };
94 … dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD8, inc) mlen 1 rlen 1 { align1 1Q };
324 … dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 2, SIMD16, inc) mlen 2 rlen 0 { align1 1H };
516 … dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD16, inc) mlen 2 rlen 0 { align1 1H };
524 … dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD8, or) mlen 2 rlen 1 { align1 1Q };
526 … dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD8, inc) mlen 1 rlen 0 { align1 1Q };
528 … dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD16, or) mlen 4 rlen 2 { align1 1H };
540 …dp data 1 MsgDesc: ( DC untyped surface write, Surface = 254, SIMD16, Mask = 0xe) mlen 4 rlen 0 { …
544 …dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 254, SIMD16, add) mlen 4 rlen 0 { align1 1H };
546 …dp data 1 MsgDesc: ( untyped surface read, Surface = 254, SIMD16, Mask = 0xe) mlen 2 rlen 2 { alig…
[all …]
/external/llvm/lib/Target/SystemZ/
DSystemZRegisterInfo.td111 // register pairs as untyped instead.
112 defm GR128 : SystemZRegClass<"GR128", [untyped], 128,
122 defm ADDR128 : SystemZRegClass<"ADDR128", [untyped], 128, (sub GR128Bit, R0Q)>;
276 def v128any : TypedReg<untyped, VR128>;
/external/llvm/lib/Target/AArch64/
DAArch64RegisterInfo.td389 def FPR8 : RegisterClass<"AArch64", [untyped], 8, (sequence "B%u", 0, 31)> {
421 def DD : RegisterClass<"AArch64", [untyped], 64, (add DSeqPairs)> {
424 def DDD : RegisterClass<"AArch64", [untyped], 64, (add DSeqTriples)> {
427 def DDDD : RegisterClass<"AArch64", [untyped], 64, (add DSeqQuads)> {
439 def QQ : RegisterClass<"AArch64", [untyped], 128, (add QSeqPairs)> {
442 def QQQ : RegisterClass<"AArch64", [untyped], 128, (add QSeqTriples)> {
445 def QQQQ : RegisterClass<"AArch64", [untyped], 128, (add QSeqQuads)> {
610 def WSeqPairsClass : RegisterClass<"AArch64", [untyped], 32,
614 def XSeqPairsClass : RegisterClass<"AArch64", [untyped], 64,
/external/llvm-project/llvm/lib/Target/SystemZ/
DSystemZRegisterInfo.td110 // register pairs as untyped instead.
111 defm GR128 : SystemZRegClass<"GR128", [untyped], 128,
121 defm ADDR128 : SystemZRegClass<"ADDR128", [untyped], 128, (sub GR128Bit, R0Q)>;
286 def v128any : TypedReg<untyped, VR128>;
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/
DSystemZRegisterInfo.td110 // register pairs as untyped instead.
111 defm GR128 : SystemZRegClass<"GR128", [untyped], 128,
121 defm ADDR128 : SystemZRegClass<"ADDR128", [untyped], 128, (sub GR128Bit, R0Q)>;
286 def v128any : TypedReg<untyped, VR128>;
/external/llvm-project/llvm/lib/Target/AArch64/
DAArch64RegisterInfo.td425 def FPR8 : RegisterClass<"AArch64", [untyped], 8, (sequence "B%u", 0, 31)> {
467 def DD : RegisterClass<"AArch64", [untyped], 64, (add DSeqPairs)> {
470 def DDD : RegisterClass<"AArch64", [untyped], 64, (add DSeqTriples)> {
473 def DDDD : RegisterClass<"AArch64", [untyped], 64, (add DSeqQuads)> {
485 def QQ : RegisterClass<"AArch64", [untyped], 128, (add QSeqPairs)> {
488 def QQQ : RegisterClass<"AArch64", [untyped], 128, (add QSeqTriples)> {
491 def QQQQ : RegisterClass<"AArch64", [untyped], 128, (add QSeqQuads)> {
687 def WSeqPairsClass : RegisterClass<"AArch64", [untyped], 32,
691 def XSeqPairsClass : RegisterClass<"AArch64", [untyped], 64,
967 def ZPR2 : RegisterClass<"AArch64", [untyped], 128, (add ZSeqPairs)> {
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64RegisterInfo.td422 def FPR8 : RegisterClass<"AArch64", [untyped], 8, (sequence "B%u", 0, 31)> {
454 def DD : RegisterClass<"AArch64", [untyped], 64, (add DSeqPairs)> {
457 def DDD : RegisterClass<"AArch64", [untyped], 64, (add DSeqTriples)> {
460 def DDDD : RegisterClass<"AArch64", [untyped], 64, (add DSeqQuads)> {
472 def QQ : RegisterClass<"AArch64", [untyped], 128, (add QSeqPairs)> {
475 def QQQ : RegisterClass<"AArch64", [untyped], 128, (add QSeqTriples)> {
478 def QQQQ : RegisterClass<"AArch64", [untyped], 128, (add QSeqQuads)> {
667 def WSeqPairsClass : RegisterClass<"AArch64", [untyped], 32,
671 def XSeqPairsClass : RegisterClass<"AArch64", [untyped], 64,
946 def ZPR2 : RegisterClass<"AArch64", [untyped], 128, (add ZSeqPairs)> {
[all …]
/external/llvm/include/llvm/CodeGen/
DValueTypes.td98 def untyped: ValueType<8 , 67>; // Produces an untyped value
/external/protobuf/src/google/protobuf/compiler/js/
Djs_generator.cc2710 bool untyped = in GenerateClassField() local
2728 if (untyped) { in GenerateClassField()
2749 if (untyped) { in GenerateClassField()
2759 if (untyped && !field->has_default_value()) { in GenerateClassField()
2771 if (untyped) { in GenerateClassField()
2785 if (field->type() == FieldDescriptor::TYPE_BYTES && !untyped) { in GenerateClassField()
2790 if (untyped) { in GenerateClassField()
2839 untyped ? "/** @type{string|number|boolean|Array|undefined} */(" : "", in GenerateClassField()
2840 "typeclose", untyped ? ")" : "", "oneofgroup", in GenerateClassField()
2847 if (untyped) { in GenerateClassField()
[all …]
/external/mesa3d/src/freedreno/computerator/
DREADME.rst43 stib.untyped.1d.u32.1 g[0] + r0.y, r0.x
/external/llvm-project/llvm/lib/Target/X86/
DX86RegisterInfo.td618 def VK1PAIR : RegisterClass<"X86", [untyped], 16, (add KPAIRS)> {let Size = 32;}
619 def VK2PAIR : RegisterClass<"X86", [untyped], 16, (add KPAIRS)> {let Size = 32;}
620 def VK4PAIR : RegisterClass<"X86", [untyped], 16, (add KPAIRS)> {let Size = 32;}
621 def VK8PAIR : RegisterClass<"X86", [untyped], 16, (add KPAIRS)> {let Size = 32;}
622 def VK16PAIR : RegisterClass<"X86", [untyped], 16, (add KPAIRS)> {let Size = 32;}
637 def TILE : RegisterClass<"X86", [untyped], 0,

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