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Searched refs:uqdech (Results 1 – 13 of 13) sorted by relevance

/external/llvm-project/llvm/test/MC/AArch64/SVE/
Duqdech.s14 uqdech x0 label
20 uqdech x0, all label
26 uqdech x0, all, mul #1 label
32 uqdech x0, all, mul #16 label
43 uqdech w0 label
49 uqdech w0, all label
55 uqdech w0, all, mul #1 label
61 uqdech w0, all, mul #16 label
67 uqdech w0, pow2 label
73 uqdech w0, pow2, mul #16 label
[all …]
Duqdech-diagnostics.s6 uqdech wsp label
11 uqdech sp label
16 uqdech z0.s label
25 uqdech x0, w0 label
30 uqdech w0, w0 label
35 uqdech x0, x0 label
44 uqdech x0, all, mul #-1 label
49 uqdech x0, all, mul #0 label
54 uqdech x0, all, mul #17 label
63 uqdech x0, vl512 label
[all …]
/external/llvm-project/llvm/test/CodeGen/AArch64/
Dsve-intrinsics-uqdec.ll18 define <vscale x 8 x i16> @uqdech(<vscale x 8 x i16> %a) {
19 ; CHECK-LABEL: uqdech:
20 ; CHECK: uqdech z0.h, pow2
22 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.uqdech.nxv8i16(<vscale x 8 x i16> %a,
110 ; CHECK: uqdech w0, vl5, mul #6
112 %out = call i32 @llvm.aarch64.sve.uqdech.n32(i32 %a, i32 5, i32 6)
118 ; CHECK: uqdech x0, vl6, mul #7
120 %out = call i64 @llvm.aarch64.sve.uqdech.n64(i64 %a, i32 6, i32 7)
233 declare <vscale x 8 x i16> @llvm.aarch64.sve.uqdech.nxv8i16(<vscale x 8 x i16>, i32, i32)
240 declare i32 @llvm.aarch64.sve.uqdech.n32(i32, i32, i32)
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64SVEInstrInfo.td870 defm UQDECH_WPiI : sve_int_pred_pattern_b_u32<0b01011, "uqdech", int_aarch64_sve_uqdech_n32>;
874 defm UQDECH_XPiI : sve_int_pred_pattern_b_x64<0b01111, "uqdech", int_aarch64_sve_uqdech_n64>;
897 defm UQDECH_ZPiI : sve_int_countvlv<0b01011, "uqdech", ZPR16, int_aarch64_sve_uqdech, nxv8i16>;
/external/vixl/test/aarch64/
Dtest-api-movprfx-aarch64.cc1184 __ uqdech(z24.VnH(), SVE_VL2); in TEST() local
1585 __ uqdech(z20.VnH(), SVE_VL2); in TEST() local
/external/llvm-project/llvm/lib/Target/AArch64/
DAArch64SVEInstrInfo.td1316 defm UQDECH_WPiI : sve_int_pred_pattern_b_u32<0b01011, "uqdech", int_aarch64_sve_uqdech_n32>;
1320 defm UQDECH_XPiI : sve_int_pred_pattern_b_x64<0b01111, "uqdech", int_aarch64_sve_uqdech_n64>;
1343 defm UQDECH_ZPiI : sve_int_countvlv<0b01011, "uqdech", ZPR16, int_aarch64_sve_uqdech, nxv8i16>;
/external/vixl/src/aarch64/
Dassembler-aarch64.h5690 void uqdech(const Register& rdn, int pattern = SVE_ALL, int multiplier = 1);
5694 void uqdech(const ZRegister& zdn, int pattern = SVE_ALL, int multiplier = 1);
Dassembler-sve-aarch64.cc480 V(uqdech, (rdn.IsX() ? UQDECH_r_rs_x : UQDECH_r_rs_uw)) \
534 V(uqdech, UQDEC, H) \
Dmacro-assembler-aarch64.h6135 uqdech(rdn, pattern, multiplier);
6140 uqdech(zdn, pattern, multiplier);
/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/AArch64/
DAArch64GenAsmMatcher.inc12607 "umullb\006umullt\005uqadd\006uqdecb\006uqdecd\006uqdech\006uqdecp\006uq"
19584 …{ 6537 /* uqdech */, AArch64::UQDECH_WPiI, Convert__Reg1_0__Tie0_1_1__imm_95_31__imm_95_1, AMFBS_H…
19585 …{ 6537 /* uqdech */, AArch64::UQDECH_XPiI, Convert__Reg1_0__Tie0_1_1__imm_95_31__imm_95_1, AMFBS_H…
19586 …{ 6537 /* uqdech */, AArch64::UQDECH_ZPiI, Convert__SVEVectorHReg1_0__Tie0_1_1__imm_95_31__imm_95_…
19587 …{ 6537 /* uqdech */, AArch64::UQDECH_WPiI, Convert__Reg1_0__Tie0_1_1__SVEPattern1_1__imm_95_1, AMF…
19588 …{ 6537 /* uqdech */, AArch64::UQDECH_XPiI, Convert__Reg1_0__Tie0_1_1__SVEPattern1_1__imm_95_1, AMF…
19589 …{ 6537 /* uqdech */, AArch64::UQDECH_ZPiI, Convert__SVEVectorHReg1_0__Tie0_1_1__SVEPattern1_1__imm…
19590 …{ 6537 /* uqdech */, AArch64::UQDECH_WPiI, Convert__Reg1_0__Tie0_1_1__SVEPattern1_1__Imm1_161_3, A…
19591 …{ 6537 /* uqdech */, AArch64::UQDECH_XPiI, Convert__Reg1_0__Tie0_1_1__SVEPattern1_1__Imm1_161_3, A…
19592 …{ 6537 /* uqdech */, AArch64::UQDECH_ZPiI, Convert__SVEVectorHReg1_0__Tie0_1_1__SVEPattern1_1__Imm…
[all …]
DAArch64GenAsmWriter.inc22817 /* 13488 */ "uqdech $\x01\0"
22818 /* 13498 */ "uqdech $\x01, $\xFF\x03\x0E\0"
22819 /* 13514 */ "uqdech $\xFF\x01\x09\0"
22820 /* 13526 */ "uqdech $\xFF\x01\x09, $\xFF\x03\x0E\0"
DAArch64GenAsmWriter1.inc23538 /* 13466 */ "uqdech $\x01\0"
23539 /* 13476 */ "uqdech $\x01, $\xFF\x03\x0E\0"
23540 /* 13492 */ "uqdech $\xFF\x01\x09\0"
23541 /* 13504 */ "uqdech $\xFF\x01\x09, $\xFF\x03\x0E\0"
/external/swiftshader/third_party/llvm-10.0/configs/common/include/llvm/IR/
DIntrinsicImpl.inc806 "llvm.aarch64.sve.uqdech",
807 "llvm.aarch64.sve.uqdech.n32",
808 "llvm.aarch64.sve.uqdech.n64",
10939 47, // llvm.aarch64.sve.uqdech
10940 47, // llvm.aarch64.sve.uqdech.n32
10941 47, // llvm.aarch64.sve.uqdech.n64