| /external/llvm/test/MC/AArch64/ |
| D | neon-uxtl.s | 20 uxtl2 v0.8h, v1.16b
21 uxtl2 v0.4s, v1.8h
22 uxtl2 v0.2d, v1.4s
|
| /external/llvm-project/llvm/test/MC/AArch64/ |
| D | neon-uxtl.s | 20 uxtl2 v0.8h, v1.16b
21 uxtl2 v0.4s, v1.8h
22 uxtl2 v0.2d, v1.4s
|
| /external/vixl/src/aarch64/ |
| D | logic-aarch64.cc | 1756 LogicVRegister extendedreg = uxtl2(vform, temp2, src); in ushll2()
3104 LogicVRegister Simulator::uxtl2(VectorFormat vform, in uxtl2() function in vixl::aarch64::Simulator
3475 uxtl2(vform, temp1, src1); in uaddl2()
3476 uxtl2(vform, temp2, src2); in uaddl2()
3498 uxtl2(vform, temp, src2); in uaddw2()
3567 uxtl2(vform, temp1, src1); in usubl2()
3568 uxtl2(vform, temp2, src2); in usubl2()
3590 uxtl2(vform, temp, src2); in usubw2()
3659 uxtl2(vform, temp1, src1); in uabal2()
3660 uxtl2(vform, temp2, src2); in uabal2()
[all …]
|
| D | simulator-aarch64.h | 3469 LogicVRegister uxtl2(VectorFormat vform,
|
| D | assembler-aarch64.h | 2995 void uxtl2(const VRegister& vd, const VRegister& vn);
|
| D | assembler-aarch64.cc | 5047 void Assembler::uxtl2(const VRegister& vd, const VRegister& vn) { in uxtl2() function in vixl::aarch64::Assembler
|
| D | macro-assembler-aarch64.h | 2908 V(uxtl2, Uxtl2) \
|
| /external/llvm/lib/Target/AArch64/ |
| D | AArch64InstrInfo.td | 4905 // Vector shift uxtl2 aliases
4906 def : InstAlias<"uxtl2.8h $dst, $src1",
4908 def : InstAlias<"uxtl2 $dst.8h, $src1.16b",
4910 def : InstAlias<"uxtl2.4s $dst, $src1",
4912 def : InstAlias<"uxtl2 $dst.4s, $src1.8h",
4914 def : InstAlias<"uxtl2.2d $dst, $src1",
4916 def : InstAlias<"uxtl2 $dst.2d, $src1.4s",
|
| /external/llvm-project/llvm/lib/Target/AArch64/ |
| D | AArch64InstrInfo.td | 6179 // Vector shift uxtl2 aliases
6180 def : InstAlias<"uxtl2.8h $dst, $src1",
6182 def : InstAlias<"uxtl2 $dst.8h, $src1.16b",
6184 def : InstAlias<"uxtl2.4s $dst, $src1",
6186 def : InstAlias<"uxtl2 $dst.4s, $src1.8h",
6188 def : InstAlias<"uxtl2.2d $dst, $src1",
6190 def : InstAlias<"uxtl2 $dst.2d, $src1.4s",
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64InstrInfo.td | 5934 // Vector shift uxtl2 aliases
5935 def : InstAlias<"uxtl2.8h $dst, $src1",
5937 def : InstAlias<"uxtl2 $dst.8h, $src1.16b",
5939 def : InstAlias<"uxtl2.4s $dst, $src1",
5941 def : InstAlias<"uxtl2 $dst.4s, $src1.8h",
5943 def : InstAlias<"uxtl2.2d $dst, $src1",
5945 def : InstAlias<"uxtl2 $dst.2d, $src1.4s",
|
| /external/vixl/test/aarch64/ |
| D | test-trace-aarch64.cc | 2475 __ uxtl2(v6.V2D(), v16.V4S()); in GenerateTestSequenceNEON() local
2476 __ uxtl2(v22.V4S(), v20.V8H()); in GenerateTestSequenceNEON() local
2477 __ uxtl2(v20.V8H(), v21.V16B()); in GenerateTestSequenceNEON() local
|
| D | test-cpu-features-aarch64.cc | 2747 TEST_NEON(uxtl2_0, uxtl2(v0.V8H(), v1.V16B()))
2748 TEST_NEON(uxtl2_1, uxtl2(v0.V4S(), v1.V8H()))
2749 TEST_NEON(uxtl2_2, uxtl2(v0.V2D(), v1.V4S()))
|
| /external/vixl/test/test-trace-reference/ |
| D | log-disasm-colour | 2130 0x~~~~~~~~~~~~~~~~ 6f20a606 uxtl2 v6.2d, v16.4s
2131 0x~~~~~~~~~~~~~~~~ 6f10a696 uxtl2 v22.4s, v20.8h
2132 0x~~~~~~~~~~~~~~~~ 6f08a6b4 uxtl2 v20.8h, v21.16b
|
| D | log-disasm | 2130 0x~~~~~~~~~~~~~~~~ 6f20a606 uxtl2 v6.2d, v16.4s
2131 0x~~~~~~~~~~~~~~~~ 6f10a696 uxtl2 v22.4s, v20.8h
2132 0x~~~~~~~~~~~~~~~~ 6f08a6b4 uxtl2 v20.8h, v21.16b
|
| D | log-cpufeatures-custom | 2129 0x~~~~~~~~~~~~~~~~ 6f20a606 uxtl2 v6.2d, v16.4s ### {NEON} ###
2130 0x~~~~~~~~~~~~~~~~ 6f10a696 uxtl2 v22.4s, v20.8h ### {NEON} ###
2131 0x~~~~~~~~~~~~~~~~ 6f08a6b4 uxtl2 v20.8h, v21.16b ### {NEON} ###
|
| D | log-cpufeatures-colour | 2129 0x~~~~~~~~~~~~~~~~ 6f20a606 uxtl2 v6.2d, v16.4s [1;35mNEON[0;m
2130 0x~~~~~~~~~~~~~~~~ 6f10a696 uxtl2 v22.4s, v20.8h [1;35mNEON[0;m
2131 0x~~~~~~~~~~~~~~~~ 6f08a6b4 uxtl2 v20.8h, v21.16b [1;35mNEON[0;m
|
| D | log-cpufeatures | 2129 0x~~~~~~~~~~~~~~~~ 6f20a606 uxtl2 v6.2d, v16.4s // Needs: NEON
2130 0x~~~~~~~~~~~~~~~~ 6f10a696 uxtl2 v22.4s, v20.8h // Needs: NEON
2131 0x~~~~~~~~~~~~~~~~ 6f08a6b4 uxtl2 v20.8h, v21.16b // Needs: NEON
|
| D | log-all | 9514 0x~~~~~~~~~~~~~~~~ 6f20a606 uxtl2 v6.2d, v16.4s
9516 0x~~~~~~~~~~~~~~~~ 6f10a696 uxtl2 v22.4s, v20.8h
9518 0x~~~~~~~~~~~~~~~~ 6f08a6b4 uxtl2 v20.8h, v21.16b
|
| /external/vixl/doc/aarch64/ |
| D | supported-instructions-aarch64.md | 6151 void uxtl2(const VRegister& vd, const VRegister& vn)
|
| /external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/AArch64/ |
| D | AArch64GenAsmMatcher.inc | 12615 "l\005uxtl2\004uxtw\004uzp1\004uzp2\003wfe\003wfi\007whilege\007whilegt\007"
19944 …{ 6908 /* uxtl2 */, AArch64::USHLLv4i32_shift, Convert__VectorReg1281_1__VectorReg1281_2__imm_95_0…
19945 …{ 6908 /* uxtl2 */, AArch64::USHLLv8i16_shift, Convert__VectorReg1281_1__VectorReg1281_2__imm_95_0…
19946 …{ 6908 /* uxtl2 */, AArch64::USHLLv16i8_shift, Convert__VectorReg1281_1__VectorReg1281_2__imm_95_0…
19947 …{ 6908 /* uxtl2 */, AArch64::USHLLv4i32_shift, Convert__VectorReg1281_0__VectorReg1281_2__imm_95_0…
19948 …{ 6908 /* uxtl2 */, AArch64::USHLLv8i16_shift, Convert__VectorReg1281_0__VectorReg1281_2__imm_95_0…
19949 …{ 6908 /* uxtl2 */, AArch64::USHLLv16i8_shift, Convert__VectorReg1281_0__VectorReg1281_2__imm_95_0…
27317 …{ 6908 /* uxtl2 */, AArch64::USHLLv4i32_shift, Convert__VectorReg1281_1__VectorReg1281_2__imm_95_0…
27318 …{ 6908 /* uxtl2 */, AArch64::USHLLv8i16_shift, Convert__VectorReg1281_1__VectorReg1281_2__imm_95_0…
27319 …{ 6908 /* uxtl2 */, AArch64::USHLLv16i8_shift, Convert__VectorReg1281_1__VectorReg1281_2__imm_95_0…
[all …]
|